Data Processor Having 2n Bits Width Data Bus for Context Switching Function

1. An n-bit data processor including plural internal n-bit data buses comprising: an instruction decoding unit, having an output port, which decodes instructions; a control unit, coupled to the output port of said instruction decoding unit and having an output port, which generates control signals to control the execution of the instructions according to the output of said instruction decoding unit; first and second n-bit registers coupled respectively to first and second n-bit internal data buses; a 2n-bit internal data bus; a 2n-bit interface data register, having first and second internal n-bit input ports coupled, respectively, to said first and second n-bit internal data buses, a 2n-bit interface output port coupled to said 2n-bit internal data bus, and an input port coupled to the output port of said control unit to receive said control signals for storing either a single n-bit word transferred between said first n-bit register and said 2n-bit interface data register or storing a pair of n-bit words simultaneously transferred between said first and second n-bit registers and said 2n-bit interface data register and for simultaneously transferring either a single n-bit word or a pair of n-bit words through said 2n-bit interface output port as determined by the control signals resulting from the decoding of selected instructions; an address register which holds an operand address of an instruction; a memory, having a 2n-bit data transfer port coupled to said 2n-bit internal data bus, for storing data; and a memory access unit, coupled to said address register, said memory, and to said 2n-bit interface output port, which accesses said memory according to the address value held in said address register, and transfers a 2n-bit word to successive memory locations in said memory from said 2n-bit interface output port.

2. An n-bit data processor including plural internal n-bit data buses comprising: an instruction decoding unit, having an output port, which decodes instructions; a control unit, coupled to the output port of said instruction decoding unit and having an output port, which generates control signals to control the execution of the instructions according to the output of said instruction decoding unit; first and second n-bit registers coupled respectively to first and second n-bit internal data buses; a 2n-bit internal data bus; a 2n-bit interface data register, having first and second internal n-bit output ports coupled, respectively, to said first and second n-bit internal data buses, a 2n-bit interface input port coupled to said 2n-bit internal data bus, and an input port coupled to the output port of said control unit to receive said control signals for transferring either a single n-bit word between said 2n-bit interface data register and said first n-bit register or simultaneously transferring a pair of n-bit words between said 2n-bit interface data register and said first and second n-bit registers and for simultaneously storing either a single n-bit word or a pair of n-bit words transferred through said 2n-bit interface input port as determined by the control signals resulting from the decoding of selected instructions; an address register which holds an operand address of an instruction; a memory, having a 2n-bit data transfer port coupled to said 2n-bit internal data bus, for storing data; and a memory access unit, coupled to said address register, said memory, and to said 2n-bit interface input port, which accesses said memory according to the address value held in said address register, and transfers a 2n-bit word from successive memory locations in said memory to said 2n-bit interface input port.