Lamp Out Detection for Miniature Cold Cathode Fluorescent Lamp System

This invention relates to circuits for supplying power to fluorescent lamps. More specifically, this invention relates to circuits for supplying power to miniature cold cathode fluorescent lamps that shut down when a fluorescent lamp is defective or absent from a lamp socket.

Fluorescent lamps have "negative resistance." This means that the operating voltage decreases as power dissipation in the lamp increases. Therefore, circuits for supplying power to fluorescent lamps require a controllable alternating current power supply and a feedback loop to accurately monitor the current in the lamp in order to maintain operating stability of the circuit and to have an ability to vary the lamp brightness. Such circuits must be able to generate a high voltage to turn on the fluorescent lamp and then lower the voltage when current begins to flow in the lamp. If such a circuit is attempted to be operated when there is no lamp in the socket or a defective lamp is in the lamp socket, the voltage level in the socket will rise to a high level while waiting to sense a current in the absent or defective lamp. For purposes of this disclosure, a no lamp condition shall also mean a circuit having a lamp that is defective in a way to simulate an open circuit. This no lamp condition could damage circuit components and/or could be hazardous to humans. What is needed is a circuit for supplying power to a fluorescent lamp that senses when there is no lamp in the lamp socket and responds by shutting itself down.

Other devices have attempted to solve the problem of generating excessive voltage in the lamp socket. One such device is disclosed in Linear Technology's Application Note 55 by Jim Williams, entitled: "Techniques for 92% Efficient LCD Illumination." That device controls the output voltage when there is a open or broken lamp in the lamp socket by increasing the feedback in the lamp drive circuit. Another device is disclosed in a paper entitled: "Resonant Fluorescent Lamp Converter Provides Efficient and Compact Solution" by Mark Jordan and John A. O'Connor of Unitrode Integrated Circuits. That device disables the circuit outputs when an open lamp interrupts the current feedback loop. Both of these devices suffer from the disadvantage of continuing to consume excess power once an open lamp is detected. The Linear Technology device only limits the output voltage while allowing the lamp driver to continue operating. Further, because the Linear Technology device may put circuit components under higher thermal stress while limiting voltage at the transformer secondary, such components may need to be over-specified to survive this fault condition. The Unitrode device only disables the outputs while allowing the remainder of the circuit to continue operating. The Unitrode solution does not have means to limit the secondary transformer voltage during start-up, and could burn out a transformer during soft start at high supply voltages. The present invention does not consume excess power or suffer from these other disadvantages because it shuts down the entire lamp drive controller when a no lamp condition is present. This is an important feature to maximize the operating time of a device with a limited power supply capacity such as a battery powered lap top computer.

The invention is a circuit for supplying power to a fluorescent lamp. A control system comprises a buck regulator for supplying a buck current, an inverter circuit for receiving the buck current and for generating a lamp voltage, a circuit for sensing a current in a fluorescent lamp, a circuit for sensing a no lamp condition, and a controller for controlling the buck regulator and the inverter. The circuit for sensing a no lamp condition monitors a voltage level at the inverter transformer. The controller is coupled to the circuit for sensing a no lamp condition. If a no lamp condition is detected, the controller responds by shutting itself down. The controller can be reactivated by toggling an on/off signal to reset a latch.

FIG. 1 shows a schematic diagram of the preferred embodiment of the present invention.

FIG. 2 shows a schematic diagram of a first alternate embodiment of the present invention.

FIG. 3 shows a schematic diagram of a second alternate embodiment of the present invention.

FIG. 4 shows a block diagram of a closed loop control system of the present invention.

Referring to FIG. 1, a liquid crystal display (LCD) backlight integrated circuit controller 100 is shown along with external circuits that are needed to illuminate a fluorescent lamp. The integrated circuit controller 100 includes the portion of the diagram enclosed by the dotted lines. The controller 100, shown in FIG. 1 and bounded by the dotted lines, is an LCD Backlight Lamp Driver, part number ML4874, manufactured by Micro Linear Corporation, which is located at 2092 Concourse Drive, in San Jose, Calif. Micro Linear Corporation also manufactures an LCD Backlight Lamp Driver with Contrast, part number ML4876 and an LCD Backlight Lamp Driver w/Contrast Control, part number ML4864, which are similar to part number ML4874, except they have circuits to control an LCD contrast level. The controller 100 has pins 1-20 that interface with the external circuits.

Referring to portions of the diagram outside the dotted lines, a voltage source node Vcc is coupled to pin 12, to a first terminal of a capacitor C7, to a first terminal of a capacitor C8, to a first terminal of a resistor R1, to a drain of an n-channel MOSFET Q1, and to the drain of an n-channel MOSFET U2-A. A second terminal of the capacitor C7 is coupled to ground. A second terminal of the capacitor C8 is coupled to ground. A second terminal of the resistor R1 is coupled to a gate of the MOSFET Q1 and to pin 2. A source of the MOSFET Q1 is coupled to pin 13, to a first terminal of a capacitor C10, to a first terminal of a capacitor C1, to a first terminal of a capacitor C9 and to a first terminal of a primary winding of a transformer T2. A second terminal of the capacitor C10, a second terminal of the capacitor C1, and a second terminal of the capacitor C9 are coupled to ground. A second terminal of the primary winding of the transformer T2 is coupled to pin 19. A first terminal of a secondary winding of the transformer T2 is coupled to an anode of a diode D1. A second terminal of the secondary winding of the transformer T2 is coupled to a source of the MOSFET U2-A. The transformer T2 has voltage polarities of the primary and secondary windings that are the same, as shown by the dot conventions in FIG. 1. A cathode of the diode D1 is coupled to a gate of the MOSFET U2-A and to a drain of an n-channel MOSFET Q2. A source of the MOSFET Q2 is coupled to ground. A gate of the MOSFET Q2 is coupled to pin 20. A drain of an n-channel MOSFET U2-B is coupled to the source of the MOSFET U2-A. A source of the MOSFET U2-B is coupled to ground. A gate of the MOSFET U2-B is coupled to pin 11. A first terminal of an inductor L1 is coupled to the source of the MOSFET U2-A. A second terminal of the inductor L1 is coupled to a first terminal of a resistor R6 and to a center tap of a primary winding of a transformer T1. A second terminal of the resistor R6 is coupled to pin 10. A first terminal of a secondary winding of the transformer T1 is coupled to a first terminal of a fluorescent lamp 204. A second terminal of the secondary winding of the transformer T1 is coupled to a second terminal of the fluorescent lamp 204. A capacitor C11 for maintaining control stability in a lamp current feedback loop may be coupled in series with the fluorescent lamp 204, but is not always required. Further, it is known in the art that more than one fluorescent lamp may be coupled in parallel. A first terminal of the primary winding of the transformer T1 is coupled to a first terminal of a capacitor C6 and to a drain of an n-channel MOSFET Q3. A gate of the MOSFET Q3 is coupled to pin 16. A source of the MOSFET Q3 is coupled to a first terminal of a resistor R5. A second terminal of the primary winding of the transformer T1 is coupled to a second terminal of the capacitor C6 and to a drain of an n-channel MOSFET Q4. A gate of the MOSFET Q4 is coupled to pin 14. A source of the MOSFET Q4 is coupled to the first terminal of the resistor R5. The first terminal of the resistor R5 is coupled to pin 6 and to a first terminal of a resistor R3. A second terminal of the resistor R3 is coupled to a first terminal of a resistor R4, to a first terminal of a capacitor C4 and to pin 7. A second terminal of the resistor R4 is coupled to a voltage level BRIGHTNESS ADJUST to control the lamp brightness level. A second terminal of the capacitor C4 is coupled to pin 8. A first terminal of a capacitor C2 is coupled to pin 3. A second terminal of the capacitor C2 is coupled to ground. A first terminal of a capacitor C5 is coupled to pin 9. A second terminal of the capacitor C5 is coupled to ground. A first terminal of a resistor R2 is coupled to pin 4. A second terminal of the resistor R2 is coupled to ground. Pin 1 is a spare. Pin 18 and Pin 17 are coupled to ground. Pin 15 is coupled to a voltage level, ON/OFF. A first terminal of a capacitor C3 is coupled to Pin 5. A second terminal of the capacitor C3 is coupled to ground. Alternately, Q3 and Q4 could be bipolar transistors.

Referring to optional components of FIG. 1, a first terminal of a resistor R50 is coupled to pin 10. A second terminal of R50 is coupled to ground.

Referring to portions of the diagram comprising the controller 100, which are inside the dotted lines, pin 7 is coupled to an inverting input of a amplifier 101. A non-inverting input of the amplifier 101 is coupled to a reference voltage level of 0.2 volts. A terminal of the amplifier 101 is coupled to pin 3 to couple the optional soft start capacitor C2 to the amplifier 101. An output of the amplifier 101 is coupled to pin 8 and to an inverting input of a comparator 102. Pin 9 is coupled to a first terminal of an oscillator 103 to set the oscillation frequency with the timing capacitor C5. The non-inverting input to the comparator 102 is also coupled to pin 9. An output of the comparator 102 is coupled to a first input to an OR gate 104. An inverting input to a comparator 105 is coupled to pin 6. A non-inverting input to the comparator 105 is coupled to a voltage reference level of 0.5 volts. An output of the comparator 105 is coupled to a second input to the OR gate 104. An output of the OR gate 104 is coupled to a RESET terminal of a flip-flop 106. A second terminal of the oscillator 103 is coupled to pin 4 to set the oscillation frequency of the oscillator 103 with the timing resistor R2. A third terminal of the oscillator 103 is coupled to deliver a clock signal to a SET terminal of the flip-flop 106, to a first terminal of a one-shot circuit 107 and to a TOGGLE input to a flip-flop 108. A second terminal of the one-shot circuit 107 is coupled to an input terminal to a buffer 109. An output terminal of the buffer 109 is coupled to pin 19. A Q-not output of the flip-flop 106 is coupled to an input to a buffer 110. An output of the buffer 110 is coupled to pin 20. A Q output of the flip-flop 106 is coupled to an input of a negative edge delay 111. An output of the negative edge delay 111 is coupled to an input to a buffer 112. An output of the buffer 112 is coupled to pin 11. A Q-not output of the flip-flop 108 is coupled to an input to a buffer 113. An output of the buffer 113 is coupled to pin 14. A Q output of the flip-flop 108 is coupled to an input to a buffer 114. An output of the buffer 114 is coupled to pin 16. A forth terminal of the oscillator 103 is coupled to receive a signal from a first terminal of a resonant threshold detector 115 to synchronize the oscillator 103. Pin 10 is coupled to, deliver a zero voltage level signal to a second terminal of the resonant threshold detector 115 and to an inverting input to an error amplifier 116. A non-inverting input to the amplifier 116 is coupled to a reference voltage level of 16 volts. An output of the amplifier 116 is coupled to a SET input to a flip-flop 117. A Q-not output of the flip-flop 117 is coupled to deliver a control signal to a first terminal of a master bias & uvlo 118 to shut down power to the fluorescent lamp if a voltage at pin 10 exceeds 16 volts. Pin 15 is coupled to a second terminal of the master bias & uvlo 118 and to a RESET input to the flip-flop 117 to restore power to the fluorescent lamp after a shut down by toggling the voltage level at pin 15. A third terminal of the master bias & uvlo 118 is coupled to deliver a reference voltage level to pin 5. A forth terminal of the master bias & uvlo 118 is coupled to receive power from a first terminal of a linear regulator 119. A second terminal of the linear regulator 119 is coupled to receive power from pin 12. A third terminal of the linear regulator 119 is coupled to pin 2. Internal to the linear regulator 119, the third terminal of the linear regulator 119 is coupled to a cathode of a Zener diode DAZR (not shown). The anode of the diode DAZR is coupled to ground. A forth terminal of the linear regulator 119 is coupled to pin 13 and coupled to provide a supply voltage to the circuits within the dotted lines.

An invertor comprises T1, C6, LAMP, Q3, Q4 and R5. The inverter is known in the art as comprising a current fed Royer-type inverter. A resonant tank circuit comprises C6 and the primary winding of the transformer T1. Q3 and Q4 comprise a push-pull transistor pair. The controller 100 alternately turns Q3 and Q4 on. This draws current from the resonant tank circuit which in turn generates a voltage across the secondary winding of T1 to power the lamp. When a voltage at the center tap of the transformer reaches a zero voltage level, the controller turns on either Q3 or Q4 and turns off the other. Because the controller alternates only at zero voltage levels, the tank circuit is driven at its resonant frequency. An internal oscillator 103 provides the switching signals for start-up. The current through R5 is substantially proportional to the current through the lamp. The current through the lamp is substantially sinusoidal. The current drawn by Q3 and Q4 generates a voltage at Pin 6 which is sensed and monitored by the controller so the lamp current can be monitored for an over current condition. The voltage at the node that comprises the source of Q3, the source of Q4 and the first terminal of R5 is coupled to the inverting input of the amplifier 101 through R3. The output of the amplifier 101 is coupled to control the duty cycle of the buck regulator. The inverter does not regulate the lamp brightness by varying the switching frequency because the inverter drives the lamp at the resonant frequency of the tank circuit.

A buck regulator has power processing components which are: a primary switch U2-A, a synchronous rectifier U2-B, and a buck inductor L1. The primary switch, U2-A, has a high side drive circuit which consists of T2, D1, and Q2. The buck regulator provides a dc current signal to the inverter circuit though L1. The fluorescent lamp brightness is regulated by the controller by varying a duty cycle of the buck regulator. The buck regulator is synchronized to the inverter, and will turn U2-A on when the inverter transistors, Q3 and Q4, change state. U2-A and U2-B have a high current capacity, and in the preferred embodiment, are each a Dual 20 v, 0.10 Ohm, n-channel, MOSFET transistor manufactured by Motorola, under part number MMDF2N02. After a time determined by a lamp current feedback signal, U2-A is turned off and U2-B is turned on. U2-B stays on until the inverter transistors, Q3 and Q4, change state and U2-A is turned on again. In this way, the controller controls the duty cycle of the buck regulator. U2-B may be replaced with a rectifier, but the efficiency of the system may suffer.

The controller drives the gate of U2-A through the miniature pulse transformer T2. T2 can be made with a ferrite bead with one turn on the primary winding and two turns on the secondary winding. Alternatively, T2 may be a low cost, surface mount transformer, such as part number CP-4LBM, which is available from Sumida, 637 East Golf Road, Suite 209, Arlington Heights, Ill., 60005. When a controller output, a signal B-ON, is activated, the voltage generated at the secondary winding of T2 is greater than the voltage level of the signal B-ON because of the transformer. B-ON is a logic level voltage of approximately 5 volts. When the signal B-ON is activated, the diode D1 becomes forward biased so that the gate of U2-A becomes charged to a higher potential than B-ON (to approximately 10 volts). When B-ON is deactivated, the diode D1 then becomes reverse biased which captures the charge on the gate of U2-A and keeps U2-A turned on. When the signal B-OFF is activated, the gate of Q2, a small signal device, is driven high by the controller. This turns Q2 on and causes the charge captured on the gate of U2-A to drain off to ground through Q2, turning U2-A off.

Referring to FIG. 2, a schematic diagram of a first alternate embodiment of the present invention is shown. The circuit shown in FIG. 2 is substantially the same as the circuit shown in FIG. 1, as discussed above, except for the differences discussed below. The primary difference, from which the other differences arise, is that the circuit shown in FIG. 2 drives the push-pull transistor pair with an additional winding of a transformer T3 whereas the circuit shown in FIG. 1 drives the push-pull transistor pair with control signals from the controller 100. A first terminal of an inductor L1 is coupled to the source of the MOSFET U2-A. A second terminal of the inductor L1 is coupled to a first terminal of a resistor R6 and to a center tap of a first primary winding of a transformer T3. The second terminal of the inductor L1 is also coupled to a first terminal of a resistor R9. A second terminal of the resistor R6 is coupled to pin 10. A first terminal of the first primary winding of the transformer T3 is coupled to a first terminal of a capacitor C6 and to a collector of an npn bipolar transistor Q5. A second terminal of the first primary winding of the transformer T3 is coupled to a second terminal of the capacitor C6 and to a collector of an npn bipolar transistor Q6. A second terminal of the resistor R9 is coupled a first terminal of a second primary winding of the transformer T3 and to a base of the transistor Q5. A second terminal of the second primary winding of T3 is coupled to a base of the transistor Q6. A first terminal of a secondary winding of T3 is coupled to a first terminal of a fluorescent lamp 204. A second terminal of the secondary winding of T3 is coupled to a second terminal of the fluorescent lamp 204. A capacitor C11 for maintaining control stability in a lamp current feedback loop may be coupled in series with the fluorescent lamp 204, but is not always required. An emitter of the transistor Q5 and an emitter of the transistor Q6 are coupled to a first terminal of a resistor R5. The transistors Q5 and Q6 comprise a push-pull transistor pair. The first terminal of the resistor R5 is also coupled to pin 6 and to a first terminal of a resistor R3. A second terminal of the resistor R5 is coupled to the ground node. A second terminal of the resistor R3 is coupled to a first terminal of a resistor R4 and to a first terminal of a capacitor C4 and to pin 7. A second terminal of the capacitor C4 is coupled to pin 8. A second terminal of the resistor R4 is coupled to a voltage level BRIGHTNESS ADJUST. The voltage level at the center tap of T3 serves to bias the base of Q5 and the base of Q6 through the second primary winding of T3 so that the resultant operation of the inverter circuit shown in FIG. 2 is substantially the same as the operation of the inverter circuit shown in FIG. 1. Alternately, Q5 and Q6 could be MOSFET transistors which are driven by the second primary winding of T3.

Referring to FIG. 3, a schematic diagram of a second alternate embodiment of the present invention is shown. The circuit shown in FIG. 3 is substantially the same as the circuit shown in FIG. 1, as discussed above, except for the differences discussed below. The primary difference, from which the other differences arise, is that the circuit shown in FIG. 3 senses a current representative of the lamp current on the secondary side of the transformer T1 whereas the circuit shown in FIG. 1 senses a current representative of the lamp current on the primary side of T1. A first terminal of an inductor L1 is coupled to the source of the MOSFET U2-A. A second terminal of the inductor L1 is coupled to pin 10 and to a center tap of a primary winding of a transformer T1 and to a first terminal of a secondary winding of the transformer T1. A first terminal of the primary winding of the transformer T1 is coupled to a first terminal of a capacitor C6 and to a drain of an n-channel MOSFET Q3. A second terminal of the primary winding of the transformer T1 is coupled to a second terminal of the capacitor C6 and to a drain of an n-channel MOSFET Q4. A gate of the MOSFET Q3 is coupled to pin 16. A source of the MOSFET Q3 is coupled to a first terminal of a resistor R5. A gate of the MOSFET Q4 is coupled to pin 14. A source of the MOSFET Q4 is coupled to the first terminal of the resistor R5. The first terminal of the resistor R5 is coupled to pin 6. The second terminal of the resistor R5 is coupled to the ground node. A second terminal of the secondary winding of T1 is coupled to a first terminal of a capacitor C12. A second terminal of the capacitor C12 is coupled to a first terminal of a fluorescent lamp 204. The ballast capacitor C12 is for maintaining control stability in a lamp current feedback loop, but is not always required. Alternately two lamps may be coupled in parallel. If two lamps are used, a ballast capacitor is required to be coupled in series with each lamp. A second terminal of the fluorescent lamp 204 is coupled to a cathode of a diode D2 and to a first terminal of a resistor R7 and to a first terminal of a resistor R8. An anode of the diode D2 is coupled to the ground node. A second terminal of the resistor R7 is coupled to the ground node. A first terminal of a resistor R4 is coupled to a voltage level BRIGHTNESS ADJUST. A second terminal of the resistor R4 is coupled to a first terminal of a capacitor C4, to a second terminal of the resistor R8 and to pin 7. A second terminal of the capacitor C4 is coupled to pin 8 and to a first terminal of a capacitor C11. A second terminal of the capacitor C11 is coupled to the ground node. Alternately, Q3 and Q4 could be bipolar transistors.

Referring now to FIG. 4, a control loop of the present invention is shown. A reference signal 200 is supplied to a controller 201 to control a brightness level of the lamp 204. A feedback signal 205 is also supplied to the controller 201. Alternately, a feedback signal 206 is, supplied to the controller 201. The feedback signal 205 corresponds to the primary side lamp current sensing shown in FIG. 1 whereas the feedback signal 206 corresponds to the secondary side lamp current sensing shown in FIG. 3. The controller 201 controls a duty cycle of a buck regulator 202 based on the reference signal 200 and a feedback signal 205 or 206. The buck regulator 202 supplies current to an inverter 203 which powers the lamp 204. A current in the lamp is sensed and fed back to the controller 201 through the feedback signal 205 or 206 that is representative of the current in the lamp.

Fluorescent lamps of the type contemplated for use with this invention have negative resistance under certain frequencies and voltage levels. This means that the operating voltage decreases as power dissipation in the lamp increases. Referring to FIG. 1, the lamp 204 is mounted in a lamp socket. The lamp socket is coupled to the circuit for supplying power to the lamp. When there is no lamp in the socket and the circuit for supplying power to the lamp is turned on, the output voltage in the lamp socket will tend to rise to a high level anticipating the start of an actual lamp. This condition is sensed by resistor R6 which is coupled to pin 10. The voltage level at pin 10 is applied to the inverting input to the amplifier 116. A 16 volt reference voltage is coupled to the non-inverting input of the amplifier 116. The output of the amplifier sets the latch 117. The output of the latch 117 signals the master bias & uvlo circuit 118 to shut down the linear regulator 119 and thereby disables the controller 100. Thus, when the voltage at pin 10 rises above 16 volts, the controller 100 will suppress the output voltage to the lamp socket by shutting down. The latch 117 can be reset and power restored to the controller 100 by toggling the logic level at pin 15, the ON/OFF input to the controller 100.

To accommodate different lamp types, sometimes it is desirable to have a voltage higher than 16 volts at the center tap of the transformer T1. In this event, the resistor R50 can be added between pin 10 and ground to form a voltage divider.

The present invention has been described in terms of specific embodiments incorporating details to facilitate the understanding of the principles of construction and operation of the invention. Such reference herein to specific embodiments and details thereof is not intended to limit the scope of the claims appended hereto. It will be apparent to those skilled in the art that modifications may be made in the embodiment chosen for illustration without departing from the spirit and scope of the invention. Specifically, it will be apparent that to one of ordinary skill in the art that the device of the present invention could be implemented in several different ways and the apparatus disclosed above is only illustrative of the preferred embodiment of the invention and is in no way a limitation. For example, it would be within the scope of the invention to vary the values of the various components, frequencies and voltage levels disclosed herein.