Automatic Resynchronization of Transmitter in the Event of Corrupted Memory

The present invention relates generally to keyless entry systems. More particularly, the invention relates to a method for automatically resynchronizing the transmitter/receiver pair when synchronization is lost due to momentary power failure or a low battery condition, for example.

Rolling code authentication is a common form of vehicle entry security. In such a system, a transmitter is provided in the form of a key fob and a receiver is positioned in the vehicle where it is able to receive encoded transmission from the key fob transmitter. Rolling code authentication can be performed by employing a simple linear counter which advances with each key fob command. The receiver in the vehicle is configured to always expect an increasing value and therefore it disallows repeating counter values. Thus to be in sync the transmitter counter should never fall behind the count of the receiver, nor should the transmitter counter be permitted to get too far ahead of the receiver count. More complex authentication using linear shift feedback register (LFSR) technology is also used as a more secure technique for vehicle entry security.

For a number of reasons, a rolling code authentication system can occasionally fall out of synchronization when the counter values of the transmitter are less than that of the receiver or when the transmitter counter values are greater than those of the receiver by a predetermined number. One reason for losing synchronization is corrupted volatile memory, which can be due to momentary loss of battery power or low battery voltage.

One way to ensure against loss of synchronization is to outfit the transmitter with a nonvolatile memory such as an EEPROM which can be used to store the rolling values so they will not be lost. Being nonvolatile, the EEPROM will not lose synchronization due to a power interruption (e.g. loose battery connection or battery failure). The EEPROM protects the integrity of the counters when the internal RAM is powered-off.

However, EEPROM devices are comparatively expensive and it would be desirable to eliminate them from the rolling code authentication circuitry. This presents a problem, since without nonvolatile memory, a system would have to rely on RAM (volatile memory) to store counter values. The need to rely on RAM increases the possibility of corrupted counter values, since even temporary loss of power through a loose battery connection or loss of battery charge would break synchronization.

The present invention addresses the synchronization problem by providing a system which automatically resynchronizes the transmitter/receiver pair when corrupted memory is detected. Ordinarily the user is not even aware resynchronization is being performed. This is accomplished by calculating and storing a first checksum indicative of the state of the transmitter at a first instance in time. Thereafter, the communications sequence is initiated between transmitter and receiver and the initiation of this sequence automatically causes a second checksum to be calculated. The second checksum is indicative of the state of the transmitter at that second instance in time. The checksums are compared and if the checksums are different, the resynchronization sequence is automatically initiated.

For a more complete understanding of the invention, its objects and advantages, reference may be made to the following specification and to the accompanying drawings.

FIG. 1 is a block diagram of an exemplary four bit linear feedback shift register, useful in understanding the principles of the invention;

FIG. 2 is an overview flowchart diagram illustrating the principles of the invention;

FIGS. 3-6 are flowchart diagrams setting forth the synchronization method of the invention in detail.

In order to understand the method of synchronizing some understanding of linear feedback shift register technology may be helpful, since the invention can be used with LFSR security systems. Accordingly, in FIG. 1 a four bit linear feedback shift register (LFSR) is depicted at 10. The shift register includes four memory cells in which four bits are stored, designated bit 3, bit 2 . . . bit 0, consecutively. The shift register is configured so that each cycle or rotation causes the contents of one bit to be shifted or transferred to its rightmost neighbor (with the exception of bits which feed an exclusive OR device).

The LFSR device also includes one or more exclusive OR operations. In FIG. 1 a single exclusive OR 12 has been illustrated, with its output supplying bit 0 and with its inputs connected to the output of bit 1 and the output of bit 0, as illustrated. Thus with each cycle or rotation, the contents of bit 1 are combined with the contents of bit 0 in an exclusive OR operation and the resultant is then stored at bit 0. The linear feedback shift register 10 illustrated in FIG. 1 is merely provided as an example. In practice, the shift register can be any number of bits, typically a larger number than four bits, and the number and location of exclusive OR operations can vary to provide different encryption codes.

In the keyless entry system the linear feedback shift register works by rotating the authentication bits, n times, through the shift register with exclusive OR feedback taps between a few of the bit locations. With each transmission, the transmitter performs a linear feedback shift register (LFSR) shift operation, which scrambles the authentication information and sends this scrambled authentication information to the receiver along with the selected command (unlock, lock, trunk, etc.). An identical LFSR operation on the receiver authentication variables is performed in the receiver after it receives a command from the transmitter. The receiver compares the results of its own LFSR operation to the authentication variables sent by the transmitter. The authentication information is validated if the receiver comparison matches.

A synchronization issue can arise when the transmitter authentication variables are lost due to power interruption. The present invention provides a method for automatically detecting corrupted authentication variables and providing for a resynchronization of those variables.

Referring to FIG. 2, an overview of the synchronization method will be given. Thereafter, a detailed explanation will be given using FIGS. 3-6. Referring to FIG. 2, the synchronizing method is automatically invoked when the transmit sequence is initiated through a user-pressed key. This is illustrated at step 20. In response to step 20 a checksum is calculated at step 22 and this checksum is compared with a stored checksum calculated during the previous transmission sequence. If the checksums match, the user-selected command is sent as indicated at step 30. On the other hand, if the checksums do not match a resync command and a series of resync variables are sent at step 26. Thereafter, a new checksum is calculated at step 28 and the routine then branches back to repeat steps 22 and 24.

From FIG. 2 it is seen that if the checksums do not match, due to a temporary loss of power and resulting loss of the stored checksum, for example, the resynchronization routine ensure a checksum match on the next cycle. Also, by virtue of step 26, the receiver is supplied with resynchronization variables to allow it to also match the new authentication code.

Referring to FIG. 3, the synchronizing method is illustrated, beginning at the point at which a key fob key is pressed (state 100). From this state control proceeds to step 102 where the checksum previously stored is compared with the newly calculated checksum. If the checksums match the memory is declared not corrupted. On the other hand, if the checksums do not match the memory is declared corrupted. Thus, in step 104, if the memory is not corrupted, control proceeds to step 106. Step 106 ultimately leads to step 122 at which the user-selected command is executed. On the other hand, if the memory is corrupted control proceeds to step 126 whereby synchronization is re-established. The following will explain both possibilities.

If Memory Is Not Corrupted

When the memory is not corrupted as determined at step 104, the user's keypad input is debounced and decoded by the transmitter microprocessor. This is illustrated at step 106. Thereafter, the transmitter rolling code or cryptographic algorithm is sequenced, as indicated at step 108. Additional details regarding the sequencing operations are set forth in connection with FIGS. 4 and 5.

Once the rolling code has been sequenced, the transmitter assembles a message at step 110 and this message is broadcast at step 112 via RF or IR transmission to the receiver located in the vehicle. The vehicle receiver then receives the transmitted message at step 114 whereupon the receiver performs its rolling code or cryptographic algorithm sequencing at step 116. At this point, the authentication codes generated at steps 108 and 116, respectively are compared at step 118. If the authentication codes match and if the transmitted command properly decodes, then the transmitter is deemed to be authentic at step 120 and the process command is performed at step 122.

In the alternative, if the authentication codes do not match, or if the transmitted command is not meaningfully decoded, then step 120 will cause the process to branch to step 124 at which the sequence is deemed to be out of synchronization or alternatively an invalid key fob transmitter may be assumed. In other words, at step 124 either the wrong transmitter was used (in which case the command will never be successful) or the right transmitter was used but it is out of sequence with the receiver

If Memory Is Corrupted - The Resynchronization Procedure

If the memory is declared corrupted at step 104 control proceeds to step 126 where the resynchronization procedure is commenced. At step 126 the transmitter initializes its counter and loads its LFSR variables with random numbers. The transmitter then assembles a message at step 128 and this message is transmitted via RF or IR transmission at step 130 to the receiver. Next, at step 132 a checksum of the transmitter RAM is calculated and stored. Thereafter, at step 134 a comparison is made to determine whether any of the last five random numbers stored in the receiver match those broadcast by the transmitter. (Although the preferred embodiment tests five numbers, a larger or smaller set of numbers could be used, if desired.) If the numbers match, step 134 is declared to have failed and the LFSR variables sent by the transmitter are rejected by the receiver. In this case, the receiver and transmitter will stay out of synchronization. On the other hand, if any of the last five resynchronization numbers do not match, successful resynchronization is declared. Upon this declaration in step 136 the receiver acquires the resynchronization numbers sent from the transmitter and places them in its own rolling code LFSR variable registers, whereupon the transmitter and receiver will now both contain the same LFSR and counter variables and are therefore in synchronization.

Further Implementation Details

The LFSR sequence utilized by both transmitter and receiver is illustrated in FIG. 4. Beginning at step 140, the sequence proceeds to step 142 where the number of bytes in the sequence is supplied and a software loop is initiated to effect the LFSR rotation. As previously explained, one or more exclusive OR operations may be interposed between selected bits of a given byte or word. (In FIG. 1 a single exclusive OR operation was positioned between bit 1 and bit 0). In step 142 the selected position of one or more exclusive OR operations is set up, so that the appropriate exclusive OR operations will occur as the cycle proceeds. If desired, the selected configuration of exclusive OR operations can be supplied as a digital word or "mask" to be applied as a setup parameter. Alternatively the mask can be permanently or semi-permanently manufactured into the system or programmed into the system by the manufacturer or dealer.

Next, at step 144, a byte is fetched into the LFSR RAM variable so that the LFSR sequence can be performed upon it. This is illustrated at steps 146, 148 and 150. In step 146 a rotate-right operation is performed on the LFSR variable, with the most significant bit (MSB) having a forced zero in its carry register. The exclusive OR operations are performed at step 148, with the resultant being supplied as feedback terms in accordance with the setup mask established at step 142. Then, in step 150, the rotated byte resulting from steps 146 and 148 is stored into a temporary memory location. Next, at step 152, if there are additional bytes queued up for rotation, the sequence returns to step 144 where the next byte is fetched and the process is repeated.

Once all of the bytes have been rotated according to steps 144-150, the temporary memory (stored as step 150) is written to the LFSR variable in RAM and control returns (step 156) to the calling program.

FIG. 5 depicts, beginning at step 158, the manner of sequencing rolling codes. As depicted at step 160, the rolling counter variable is retrieved from RAM, this variable is then incremented by one (step 162) and stored back in RAM (step 164). Control then returns to the calling program (step 166).

The presently preferred embodiment assembles transmitter messages as illustrated in FIG. 6. Beginning at step 168, the transmitter message is assembled by first placing the transmitter ID in the first transmission byte (step 170). Next, a decision is made (step 172) as to whether the message is a resychronization message or a regular command. Regular commands are assembled (step 174) by placing the rolling bits and LFSR data in the next 39 bits to be transmitted. If the command is a resynchronization command, the message is assembled by first generating or fetching random numbers (step 176) which serve as LFSR/rolling number initial variables. Next, at step 178, the exclusive OR resync command is inserted into the message. Thereafter (step 180) the resynchronization bits are placed in the message along with the desired command into the next 39 transmission bits.

Once the message has been assembled (either regular or resynchronization) an error correction code or checksum is calculated for that message and it is also placed in the message at the last transmission byte location. In this way, the message to be sent from transmitter to receiver is assembled. The receiver is thus able to decode the message by following the reverse procedure. After the message is assembled the routine returns (step 184) to its calling program.

While a rolling code authentication using linear feedback shift register technology has been illustrated, the method of synchronizing transmitter and receiver is not limited to LFSR techniques. In general, the invention can be used with any cryptographic authentication which is capable of supporting the checksum technique.

While the invention has been described in its presently preferred embodiment, it will be understood that the invention is capable of modification without departing from the spirit of the invention as set forth in the appended claims.