Enchanced Stability Voltage Controlled RC Oscillator

The present invention relates to a voltage controlled oscillator (VCO), and more particularly to a circuit for a VCO suitable for manufacture as a monolithic integrated circuit.

Voltage controlled oscillators have many applications in generating an oscillating voltage whose frequency is dependent upon a control voltage. One application of a voltage controlled oscillator is in a phase locked loop (PLL) in which the output of the oscillator is locked to an input frequency and the control voltage of the VCO is used as a reference voltage for other circuits. For example, it may be desirable to adjust the frequency response of a filter circuit as a function of the input frequency.

U.S. Pat. No. 5,243,239 discloses an integrated MOSFET oscillator using storage cells to effect trimming of current and voltage. A constant current oscillator is disclosed which uses a capacitor charged by a constant current as a timing element, with the capacitor being discharged by a MOSFET connected across it. The MOSFET is used as a switch to discharge the capacitor, and the frequency of oscillation is not substantially dependent on its linear resistance.

It would be desirable to provide a voltage controlled oscillator whose input frequency is not substantially affected by variations in supply voltage. It would also be desirable to provide a voltage controlled oscillator whose frequency is substantially dependent on a control voltage applied to a timing element, preferably a grounded timing element, where a similar timing element could be incorporated in another circuit, for example a filter. The VCO could be incorporated in an integrated circuit having several timing elements in filters. The output of the VCO can be locked to a reference frequency, e.g., using a phase locked-loop (PLL), and the tuning voltage used to tune the filters, e.g. continuous time filters. Such an integrated circuit could be used in an Ethernet transceiver.

An object of the present invention is to provide a VCO whose output frequency is substantially dependent on the tuning voltage applied to a voltage-variable RC timing element, and which is substantially independent of supply voltage fluctuations.

In the present invention, a VCO incorporates an RC timing element as a frequency determining component, the resistor being provided by a voltage-variable resistance element whose resistance is dependent on the timing voltage input. The capacitor is provided with current from a current source whose output is also dependent on the tuning voltage. This results in a substantial dependence of the oscillator frequency on the tuning voltage.

Preferably, both the RC timing element and the current source include voltage-variable resistor elements having similar properties. A corresponding voltage-variable resistor element having similar properties can be included in a further circuit, such as a filter.

An embodiment of the present invention provides a voltage controlled oscillator arranged for connection to first and second supply voltages and to a control voltage input that provides an output having a frequency that is dependent on the control voltage input. The voltage controlled oscillator includes an RC timing element comprising a capacitor element and a voltage-variable resistor element, preferably connected in parallel, wherein the voltage-variable resistor element has an input for varying its resistance that is coupled to the control voltage input. Advantageously, one terminal of the voltage variable resistor element is coupled to ground. The voltage-variable resistor element can be a field effect transistor, for example, a MOSFET, having gate, drain, and source terminals. The control voltage input is coupled to the gate, with the source and drain terminals coupled across the capacitor element.

The voltage controlled oscillator further includes circuitry to supply a predetermined current to the timing element to charge the capacitor until the voltage across the timing element exceeds a first predetermined threshold, and thereafter to cut off the supply of current until the capacitor has discharged through the voltage-variable resistor to a second predetermined threshold voltage before resuming supply of the predetermined current, thereby producing repetitive oscillations. A comparator can be arranged to switch the predetermined current on and off in response to a voltage detected across the timing element.

The predetermined current is adjusted in dependence on the control voltage input. Increasing the control voltage decreases the resistance of the voltage-variable resistor, which tends to decrease the amount of time needed to charge the capacitor. By making the predetermined current dependent on the resistance of the voltage-variable resistor, the grounded parallel RC network can control the frequency of oscillation without a dependence on the supply voltage.

The predetermined current can be derived from the current flowing through the further voltage-variable resistor by means of a current mirror. Most preferably, the predetermined current is a predetermined multiple of the current through the voltage-variable resistor, the multiple being greater than one and preferably 2 or close to 2. The VCO could be incorporated in an integrated circuit having several timing elements in filters. The output of the VCO can be locked to a reference frequency, e.g., using a phase locked-loop (PLL), and the tuning voltage used to tune the filters. Such an integrated circuit could be used in an ethernet transceiver.

FIG. 1 is a simplified block diagram of a VCO according to the present invention.

FIG. 2 is a circuit diagram of a preferred embodiment of a VCO according to the present invention.

FIG. 3 is a schematic diagram for explaining charging of the timing element.

FIG. 4 is a schematic diagram for explaining discharging of the timing element.

FIG. 5 is a timing diagram showing how the voltages at various points in the circuit vary.

FIG. 6 is a block diagram of a PLL in which the VCO of the invention can be incorporated.

FIG. 7 is a circuit diagram of another embodiment of a VCO according to the present invention.

Referring to the simplified block diagram shown in FIG. 1, the operation of the circuit is explained.

A timing element 1 comprises a resistance element R(v), whose resistance is dependent on a voltage applied to a control terminal, and a capacitor C connected in parallel. Assuming the voltage across the timing element is zero, the capacitor is initially supplied with current from a switchable constant-current source 2. The capacitor charges, and the increasing voltage across the timing element is fed to a comparator with hysteresis 3 connected to a switch element 30 of the constant-current source.

When the voltage across the timing element exceeds a first switching threshold V.sub.T+ of the comparator, the comparator disables switch 30, turning off the supply of current. The capacitor then discharges through the voltage variable resistor until it falls to a second switching threshold V.sub.T-, lower than the first switching threshold, at which point the comparator enables switch 30, turning on the supply of current again, and the cycle repeats. Thus, the voltage across the timing element oscillates between V.sub.T+ and V.sub.T-. Preferably, the difference between these two voltages is at least 10% of the supply voltage, more typically at least about 40%. These two voltages must be relatively low and close together to keep the MOSFET in its triode region over the whole range.

It will be appreciated that oscillating voltages and currents will exist at many points in the circuit, and the output could in principle be obtained or derived from any of these, all of which are directly or indirectly related to the voltage across the timing element. In the preferred embodiment, the output is obtained from the comparator output, which provides a buffered square-wave output. Other buffering and pulse-shaping circuitry may be included as desired.

The circuit will now be described in more detail. Referring to FIG. 2, the resistance element R(v) is provided by the channel resistance R.sub.ds1 of N channel MOSFET 10 biased in the triode region or linear region, the drain and source of which are connected across a capacitor 12, integrated on the same substrate, and the gate of which is connected to a tuning voltage input. Biasing is achieved by the selection of operating voltages. Typically, the supply voltage=5 V, the drain of MOSFET 10 operates from 0.25 V to 0.9 V, and the control voltage ranges from about 3 V to 5 V. The source of MOSFET 10 and one terminal of the capacitor are connected to ground (negative supply) 50, and the drain of the MOSFET and the other terminal of the capacitor are connected to the output of a voltage-variable constant-current source 2 which will be described in more detail below, and to an input of a comparator with hysteresis 3. The output of the comparator 3 switches the constant current source 2 on and off via switch element 30, which may be a P-channel MOSFET, for example.

The comparator circuit will now be explained. In the circuit shown, the timing element is connected to the non-inverting input of a comparator element 32 which can be constructed as a conventional differential comparator or operational amplifier, and the output of the comparator element 32 is fed through an inverting buffer 34. This signal is fed via another inverting buffer 31 to provide a signal of the correct polarity (i.e., negative for on, positive for off) to drive the P-channel MOSFET switch element 30. The other (inverting) input of the comparator element 32 is connected to a potential divider comprising a resistor 38 connected to positive supply 52, and resistor 40 connected to ground (negative supply input) 50. The output of the inverting buffer 34 is also connected to the inverting input via a resistor 36. The effect of this feedback is that when the output of the inverting buffer 34 is high, which will occur when the output of comparator element 32 is low, i.e., when the voltage across the timing element 1 is less than the voltage at the inverting input, the voltage at the inverting input is raised. Conversely, when the output of the inverting buffer 34 is low, the voltage will be lowered.

Thus, when the voltage across the timing element 1 is low, the comparator will not switch until a first reference voltage level V.sub.T+ is exceeded, and when the voltage across the timing element is high, the comparator will not switch until it falls below a second reference level V.sub.T-, lower than the first. The precise values of these levels will depend on the values of resistors 36, 38, 40, and can be calculated readily by one skilled in the art for given circuit parameters. Typically, V.sub.T+ .apprxeq.0.9 V and V.sub.T- .apprxeq.0.25 V. It will, of course, be apparent to one skilled in the art that numerous other configurations are possible for providing a comparator with hysteresis and providing a signal of the correct polarity to switch the constant current source 2. For example, the inputs to the comparator 32 may be swapped, in which case the inverting buffer 34 may be dispensed with. The use of buffers may be desirable to maintain signal levels to produce a well-defined waveform. A square wave output can be obtained from any of the comparator element 32 and the buffer 34. Waveforms at the output of the buffer 34 (output voltage) and at the input of the comparator 32 v(t) are shown in FIG. 5

The constant-current source 2 will now be described in more detail. A second voltage-variable resistance element comprising MOSFET 14 in this embodiment has a source connected to the negative supply input (ground) 50, and a gate connected to the tuning voltage input. MOSFET 14 is biased in the triode region, providing a variable resistance R.sub.ds2 between source and drain terminals. The drain of MOSFET 14 is maintained at a reference voltage V.sub.R by means of a voltage source comprising a differential amplifier 18 and a MOSFET 16 supplied with current from an input arm of a current mirror. The non-inverting input of the amplifier 18 is connected to a reference voltage supplied by a potential divider comprising two resistors 20, 22 connected between the positive supply 52 and the ground 50. The inverting input of the amplifier 18 is connected to the drain of the N channel MOSFET 14, and the output is connected to the gate of N channel MOSFET 16. Thus, if the voltage at the junction of the drain of MOSFET 14 and source of MOSFET 16 is less than the voltage at the junction of resistors 20, 22, the output of the amplifier 18 will be high, driving MOSFET 16 on, thus increasing the current flowing through MOSFET 14 until the voltage across the MOSFET 14 is substantially equal to the reference voltage. Since the current flowing through the gate of MOSFET 16 is negligible, the current supplied to the drain of MOSFET 16 will be substantially identical to the current flowing through the MOSFET 14, which will be equal to the reference voltage divided by the drain-source resistance R.sub.DS2 of the MOSFET 14. This current is supplied by MOSFET 24 forming the input arm of a current mirror comprising MOSFETs 24 and 26, the MOSFETs being dimensioned to form a current mirror producing an output current substantially equal to twice the input current. This multiple may of course be changed as desired by altering the dimensions of the MOSFETs. The output current may be switched off by means of P channel MOSFET 30, which has a source connected to the positive supply input 52, and a drain connected to the source input of the P-channel MOSFET 26, the output being provided by the drain terminal thereof. A P-channel MOSFET 28 of corresponding properties to MOSFET 30 is coupled between the positive supply input 22 and the source of the MOSFET 24. The gate of MOSFET 28 is coupled to ground. This further MOSFET 28 is provided to balance out the effects of MOSFET 30, so that MOSFETs 24 and 26 have similar positive supply inputs to their source terminals. Thus, when the gate input to MOSFET 30 is low, the output current at the drain of MOSFET 26 will be equal to the predetermined multiple of the current flowing through the MOSFET 14. When the gate input to MOSFET 30 is high, the output current will be substantially zero, as no current will flow through MOSFET 30.

In the above described circuit, MOSFET 14 has substantially identical properties to MOSFET 10, and multiplication of the current is provided by the ratio of the properties of MOSFET 26 to MOSFET 24. It is possible for the properties of MOSFET 14 to differ from those of MOSFET 10. For example, if MOSFET 14 has half the resistance for a given control voltage input as MOSFET 10, a 1:1 current mirror may be provided by MOSFETs 26 and 24 to achieve the same ratio of output current. It is desirable for the output current of the current source to be greater than the current which would flow through MOSFET 10 at the reference voltage (i.e., the current flowing through MOSFET 14 when MOSFETs 14 and 10 are identical), or the voltage across timing element 1 must be significantly lower than the reference voltage, and the comparator must switch between two relatively low threshold voltages. Low-amplitude oscillation in the voltage across timing element 1 may result in instabilities, sensitivity to noise, and problems with maintaining an accurate operating frequency.

The calculation of the operating frequency will be described below with reference to FIG. 3, which shows the effective charging circuit, and FIG. 4, which shows the effective discharging circuit for the capacitor. The times can be calculated as follows.

If the voltage across the capacitor, v(t) equals V.sub.T- at time t.sub.o, then at subsequent times (t is greater than t.sub.o), the voltage across the capacitor (and hence across the timing element) is given by equation (1), where V=2IR.sub.ds.

When this voltage reaches the upper threshold voltage V.sub.T+, the current is switched off and the capacitor will discharge through the resistor. If the voltage v(t) across the capacitor equals V.sub.T+ at time t.sub.1, then for subsequent times (t greater than t.sub.1), the voltage across the timing element will be given by equation 2:

Equation 1 can be used to calculate the charge time t.sub.c by solving for v(t)=V.sub.T+, according to equations 3 and 4.

Similarly, the discharge time can t.sub.D be calculated from equation 2, using equations 5 and 6.

The oscillator frequency F=1/(T.sub.C +T.sub.D), and this depends on R.sub.ds1, C, V, V.sub.T+, and V.sub.T-, where V=2I R.sub.ds1 and where R.sub.ds1 is the resistance R(V) of MOSFET 10, and R.sub.ds2 is the resistance of MOSFET 14.

2I is the output from the current source comprising a 2:1 current mirror, and is equal to twice the current flowing through MOSFET 14, so I=V.sub.R /R.sub.ds2 =V.sub.R /R.sub.ds1 (because MOSFET 14 is identical to MOSFET 10), so V=2V.sub.R, the resistance of the MOSFET channel being cancelled out. If the ratio of the current mirror is different, V will vary accordingly. From equation 4, it can be seen that if V.ltoreq.V.sub.T+, t.sub.c becomes undefined (i.e. oscillation is not possible) because the capacitor can never charge to V.sub.T+.

V.sub.T+, V.sub.T-, and V.sub.R are, in this embodiment, provided by potential dividers, so all are directly proportional to the supply voltage.

Therefore, the term (V.sub.T+ -V.sub.T-)/(V-V.sub.T-) in equation 4 has both numerator and denominator proportional to supply voltage, so is independent of supply voltage. Similarly, the term V.sub.T+ /V.sub.T- in equation 6 is independent of supply voltage.

Thus, the oscillator frequency will be substantially independent of supply voltage and is substantially dependent on the RC time constant of the timing element, which is controlled by the tuning voltage.

The circuitry responsible for determining the frequency of the voltage controlled oscillator is a parallel RC network, of which one terminal is connected to ground, and this combination can be used in a filter, such as a continuous-time filter. The resistor ratios which set V.sub.T- and V.sub.T+ can be known to a high degree of accuracy by monolithic matching. The VCO can be incorporated in a PLL as shown in FIG. 6. A filter and VCO combination may be employed in an Ethernet transceiver, for example.

The VCO may be connected between a positive supply and ground, or between positive and negative supplies. References to ground in this specification and claims shall be construed as references to any voltage level to which circuitry outside the VCO can be related, including a negative supply voltage.

FIG. 7 shows another embodiment of the present invention. In the embodiment shown in FIG. 2, the frequency controlling voltage-variable resistor 10 (MOSFET M1 in the triode region) was kept in the triode region by virtue of the fact that the two thresholds of comparator A.sub.2 were kept near a ground potential (typical threshold values were 0.25 V and 0.9 V, respectively). In some instances, it might be desirable for the threshold voltages to be further apart for less sensitivity to noise. Also, as the capacitor voltage varies throughout the charge/discharge cycle, the MOSFET drain voltage is varying as well, and there is a small modulation of the drain resistance. This produces the conflicting requirements of a large voltage swing of capacitor voltage for noise immunity, but a small voltage swing for minimal modulation of drain resistance.

In the embodiment of FIG. 7, a "shield" transistor 15 is used to pin the drain of transistor M1 to a constant voltage, keeping both the drain resistance and the drain current constant as a consequence. The drain of the shield or cascode transistor 15 has the same voltage as the capacitor (varying over time) on its drain, but isolates the drain of the voltage-variable resistor M1.

The operation of this circuit is somewhat different from the embodiment of FIG. 2, due to the fact that the current Ic through the capacitor C switches between +I and -I instead of following the previous exponential curve typical of an RC network.

Assume for analysis that the V.sub.RC starts at 0 V. Vcs will then be 0 V, which turns on P-channel device M.sub.7. This enables a current of magnitude 2I to flow out of the drain of M.sub.5. This current will split at node V.sub.RC, resulting in a current I flowing into M.sub.8 and another current I flowing into capacitor C. Note that drain current of M.sub.8 must equal I since the ratios of M.sub.8 and M.sub.1 are matched to the ratios of M.sub.3 and M.sub.2, which establishes the drain current I for M.sub.3 dependent on V.sub.R and the drain resistance of M.sub.2. If control is sufficiently high in voltage relative to V.sub.R, M.sub.1 and M.sub.2 will both be in the triode region.

Capacitor C now charges until V.sub.RC reaches upper threshold voltage V.sub.T+, at which time A.sub.2 switches and V.sub.cs goes to V.sub.DD, turning off M.sub.7. This results in C being discharged by current I into M.sub.8. The discharge continues until V.sub.RC reaches lower threshold voltage V.sub.T-, and the cycle then repeats indefinitely.

Note that this circuit retains the unique idea of basing the charge/discharge current on a voltage proportional to V.sub.DD and on the resistance of a MOSFET matched to M.sub.1. When the thresholds V.sub.T+ and V.sub.T- are also based on V.sub.DD, the V.sub.DD dependence of the oscillator frequency is very small; i.e. the frequency depends substantially on M.sub.1 -C, as is desired. Derivation of the frequency is as follows: ##EQU1## (I.sub.C is constant for whole charge portion of cycle) ##EQU2## Note, if V.sub.T+, V.sub.T-, V.sub.R are all proportional to V.sub.DD, the V.sub.DD term cancels out. ##EQU3##

One of the advantages of the enhanced circuit shown in FIG. 7 is that the drain of M.sub.1 is kept at an approximately constant voltage, which implies a constant drain resistance. The oscillator frequency is dependent on this resistance. The circuit shown in FIG. 2 made the implicit assumption that the drain resistance "averaged" to a nominal value equal to that of M.sub.2 as the drain voltage varied. This assumption does not need to be made with the enhanced circuit.

Keeping M.sub.1 under the same bias conditions as M.sub.2 also implies that a constant current flows in M.sub.1 (as it does in M.sub.2). This means that the capacitor current will be either I if M.sub.7 is on or -I if M.sub.7 is off. The linear charge and discharge rate of C that results makes the analysis and design of the circuit straightforward and gives a simple control of the duty cycle. The circuit and analysis in FIG. 2 assumes a current mirror ratio of 2:1 on M.sub.5 to M.sub.4, which results in a 50% duty cycle. By changing the current mirror ratio from 2:1 (but always remaining greater than 1:1), the duty cycle can be varied in a direct fashion that is easy to calculate.

The above description is illustrative and not restrictive. Many variations of the invention will become apparent to those of skill in the art upon review of this disclosure. The scope of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims along with their full scope of equivalents.

For example, the current mirror comprised of MOSFET 24 and 26 can be cascoded to approximate an ideal current mirror more closely. The switching element comprising MOSFET 30 may be improved to result in rapid turn-off of the supply of current; in the illustrated circuit, when the current is switched off, MOSFET 30 is high impedance, so the current is not immediately switched off, due to parasitic capacitance holding the source of MOSFET 26 high. In the preferred embodiment, this effect is minimized by keeping the oscillation frequency relatively low (typically of the order of 1 MHz).