Digitally Controlled Capacitive Load

A. Field of the Invention

This invention relates to digital waveform processing and, more particularly, to the deskewing and delaying of a waveform under digital control.

B. Description of the Prior Art

Digitally-controlled capacitive devices may serve a number of uses which include being used as digitally-controlled delays in clock generator circuits. The digitally-controlled delays are necessary in such circuits for precision deskewing of output waveforms. Circuit implementations of the digitally controlled delays have generally involved attaching a capacitive load to a signal line with a transmission gate coupled between the capacitive load and the signal line. The signal line carries the waveform to be delayed and the transmission gate acts as a digital switch to selectively connect or disconnect the capacitive load to the signal line. When the capacitive load is connected to the signal line, the waveform carried by the signal line is correspondingly delayed. Conversely, when the capacitive load is disconnected from the signal line, the waveform carried by the signal line is not delayed.

Prior art implementations of digitally-controlled capacitive loads suffer from the problems associated with the transmission gate used as a switch to connect and disconnect the capacitive load to the signal line. In general, the prior art transmission gate itself adds a significant amount of capacitance to the signal line, even when the gate is switched off. Moreover, the prior art transmission gate is known to cause glitches on the signal line each time the gate is switched. Considering objectionable characteristics in the prior art digitally-controlled capacitive loads, an improved digitally-controlled capacitive load is desired.

An integrated circuit for selectively providing delay to a waveform carried on a signal line is described. With the present invention, a digitally-controlled capacitive load is coupled to the signal line which carries the waveform. An enable line is directly coupled to the capacitive load so as to selectively activate and deactivate the capacitive load. When the enable line is in an active state, the capacitive load has maximum capacitance and the delay of the waveform being carried on the signal line is correspondingly maximized. When the enable line is in an inactive state, the capacitive load has minimum capacitance and the delay of the waveform being carried on the signal line is minimized accordingly.

FIG. 1 is a schematic of a prior art digitally-controlled capacitive load.

FIG. 2 is a schematic of the presently preferred embodiment of an improved digitally-controlled capacitive load.

FIG. 3 is block diagram of an embodiment using N of the presently preferred digitally-controlled capacitive loads to variably delay a waveform being carried by the signal line.

An integrated circuit for selectively providing delay to a waveform carried on a signal line is described. In the following description, numerous specific details are set forth such as specific circuits in order to provide a thorough understanding of the present invention. The present invention, however, may be practiced without these specific details. In other instances, the details of well-known circuitry are not shown here in order not to obscure the present invention unnecessarily. In the following description, the presently preferred embodiment is used as part of a delay interpolator. The invention may also be used, however, in other similarly configured circuits.

FIG. 1 is a schematic of a prior art digitally-controlled capacitive load 101. Capacitive load 101 is coupled to signal line 117 at node 103 through transmission gate 111. Signal line 117 carries a waveform which enters signal line 117 at IN 113 and is output at OUT 115. Transmission gate 111 selectively connects and disconnects capacitive load 101 to signal line 117 in response to DLYEN 105. Capacitive load 101 is comprised of a p-type MOS transistor 109 and an n-type MOS transistor 107. Transistors 107 and 109 have commonly connected gates. The drain and source of transistor 107 are both coupled to V.sub.ss and the drain and source of transistor 109 are both coupled to V.sub.cc.

Operation of prior art digitally-controlled capacitive load 101 is simple. When DLYEN 105 is high, transmission gate 111 conducts and connects capacitive load 101 to signal line 117 at node 103. When DLYEN 105 is low, transmission gate 111 is cut-off and capacitive load 101 is disconnected from signal line 117 accordingly.

One of the problems associated with prior art capacitive load 101 shown in FIG. 1 is that transmission gate 111 itself adds a significant amount of capacitance to signal line 117, even when DLYEN 105 is inactive. The added capacitance is an effect produced by the drain-diffusion capacitance of transmission gate 111. As a result of this additional capacitance, the number of prior art digitally-controlled capacitive loads 101 that can be coupled to signal line 117 is limited to a relatively low value because of the reliability problems created by excessive loading of signal line 117.

An additional problem associated with prior art digitally-controlled capacitive load 101 is realized during DLYEN 105 transitions from active to inactive, and vice-versa. Particularly, when DLYEN 105 changes states, a small glitch appears at node 103 on signal line 117. The glitch is an effect of the capacitive coupling from DLYEN 105 to node 103. As a result, a large number of prior art digitally-controlled capacitive loads 101 cannot be connected to a signal line 117. If all of the large number of capacitive loads 101 were enabled or disabled simultaneously, the resulting glitch amplitude on signal line 117 could become prohibitively excessive.

FIG. 2 is a schematic of the presently preferred embodiment of a digitally-controlled capacitive load 201. Capacitive load 201 is coupled to signal line 221 at node 203. Signal line 221 carries a waveform which enters signal line 221 at IN 217 and is output at OUT 219. Capacitive load 201 includes n-type MOS transistor 207 and p-type MOS transistor 209, transistors 207 and 209 having commonly connected gates that are directly coupled to node 203. The source and drain of n-type MOS transistor 207 are coupled to the output of logical-NOT gate 211. Similarly, the source and drain of p-type MOS transistor 209 are coupled to the output of logical-NOT gate 215. DLYEN 205 is directly coupled to the input of logical-NOT gate 211 and DLYEN 205 is coupled to the input of logical-NOT gate 215 through logical-NOT gate 213.

When DLYEN 205 is low, the source and drain of n-type MOS transistor 207 are at V.sub.cc, while the source and drain of p-type MOS transistor 209 are at V.sub.ss. In this condition, both transistors 207 and 209 are cut-off. In the cut-off condition, there is no inversion layer in transistors 207 and 209. This absence of an inversion layer effectively lowers the gate capacitances of the respective transistors 207 and 209 to a very low minimal value.

The absence of inversion layers which minimize the capacitances of transistors 207 and 209 can be understood by considering an inversion layer as one of the two plates of a capacitor. The other one of the two plates is the gate of the transistor. The absence of an inversion layer is equivalent to separating the capacitor plates by a large amount. Thus, the absence of an inversion layer correspondingly reduces the capacitance of each transistor 207 and 209 to a minimal value.

Conversely, when DLYEN 205 is high, inversion layers are created in transistors 207 and 209. Accordingly, the capacitances in transistors 207 and 209 are maximized. In the presently preferred embodiment, maximum capacitance is achieved as long as the gate voltage is one threshold voltage above V.sub.ss in the n-type MOS transistor 207, and the gate voltage is one threshold voltage below V.sub.cc in the p-type MOS transistor 209.

Thus, by having the gates of transistors 207 and 209 directly coupled to signal line 221 at node 203, the presently preferred capacitive load 201 solves the problems associated with prior art capacitive load 101. There is no need in the presently preferred embodiment for a gate corresponding with the prior art intermediating transmission gate 111. As a result, the presently preferred embodiment does not suffer from the problems associated with transmission gate 111. When DLYEN 205 is low, the capacitive loading on node 203 is very low, when compared with prior art capacitive load 101, since there is no undesirable drain diffusion connected to signal line 221 by presently preferred capacitive load 201. Hence, a greater number of presently preferred capacitive loads 201 can be reliably connected to a signal line 221. When DLYEN 205 switches, no significant glitching occurs since the capacitor associated with each transistor 207 and 209 switches in the opposite direction of the other and effectively cancels out the glitch caused by the other. In the presently preferred embodiment, transistors 207 and 209 have the same gate dimensions in order to ensure the glitch canceling characteristics of the transistors 207 and 209 during DLYEN 205 transitions.

FIG. 3 illustrates an alternative embodiment utilizing the present invention. In the FIG. 3, N of the presently preferred capacitive loads 313 are coupled to signal line 309 at node LOAD 319 through node DLY 311. A waveform enters signal line 309 through IN 301 and gate 303. The waveform is output from signal line 309 at LOAD 319 through gate 305 and OUT 307. Each of the N capacitive loads 313 can be individually enabled under control of the signals carried by DLYEN <0:N-1> line 317 which is coupled to the N capacitive loads 313 at DLYEN terminal 315. With the embodiment illustrated in FIG. 3, the waveform on signal line 309 at LOAD 319 can be variably delayed in response to the control signals carried by DLYEN<0:N-1>317. For minimal delay between IN 301 and OUT 307, none of the N capacitive loads 313 are enabled. For maximum delay between IN 301 and OUT 307, all of the N capacitive loads 313 are enabled. The delay between IN 301 and OUT 307 can be computed using the following linear equation:

where n is the number of signals active in DLYEN<0:N-1>317, t.sub.DLY (n) is the delay between IN 301 and OUT 307 with n of the signals active in DLYEN<0:N-1>317, t.sub.DLY (0) is the delay between IN 301 and OUT 307 with none of the signals active in DLYEN<0:N-1>317, and t.sub.UNITDLY is the delay between IN 301 and OUT 307 with a single one of the capacitive loads activated in capacitive loads 313.

Test simulations have been run modeling the N capacitive loads 313 illustrated in FIG. 3. In the simulations, when the N capacitive loads 313 were incorporated using presently preferred digitally-controlled capacitive loads 201, the linear relationship set forth in Equation 1 was followed extremely well. On the other hand, when prior art digitally-controlled capacitive loads 101 were used in simulation, the resulting circuit deviated significantly from the linear relationship set forth in Equation 1. Thus, the presently preferred embodiment of capacitive load 201 is particularly well suited for the application embodied in FIG. 3, and the prior art capacitive load 101 is unacceptable.

The embodiment described in FIG. 3 using N digitally-controlled capacitive loads 313 is also utilized with the circuitry described in pending patent application, Ser. No. 08/394,174, filed on Feb. 24, 1995, and entitled "DELAY INTERPOLATION CIRCUITRY now U.S. Pat. No. 5,489,864."

Thus, an improved digitally-controlled capacitive circuit is described. The described digitally-controlled capacitive circuit provides a digitally-controlled delay without the detrimental characteristics and non-linear behavior of the prior art digitally-controlled capacitive delay. Although the present invention has been described in terms of a preferred embodiment, it will be appreciated that various modifications and alterations might be made by those skilled in the art without departing from the spirit and scope of the present invention.