Bridge Between Two Buses of a Computer System With a Direct Memory Access Controller With Accessible Registers to Support Power Management

1. Field of the Invention

The present invention relates to the field of digital computer systems, and more particularly, to power management in a system having a direct memory access controller.

2. Description of Related Art

In computer systems, electronic chips and other components are connected with one another by buses. A variety of components can be connected to the bus providing intercommunication between all of the devices that are connected to the bus. One type of bus which has gained wide industry acceptance is the industry standard architecture (ISA) bus. The ISA bus has twenty-four (24) memory address lines which therefore provides support for up to sixteen (16) megabytes of memory. The wide acceptance of the ISA bus has resulted in a very large percentage of devices being designed for use on the ISA bus. However, higher-speed input/output devices commonly used in computer systems require faster buses. A solution to the general problem of sending and receiving data from the processor to any high-speed input device is a local bus. Unlike the ISA bus, which operates relatively slowly with limited bandwidth, a local bus communicates at system speed and carries data in 32-bit blocks. Local bus machines remove from the main system bus those interfaces that need quick response, such as memory, display, and disk drives. One such local bus that is gaining acceptance in the industry is the peripheral component interconnect (PCI) bus. The PCI bus can be a 32 or 64-bit pathway for high-speed data transfer. Essentially, the PCI bus is a parallel data path provided in addition to an ISA bus. The system processor and memory can be attached directly to the PCI bus, for example. Other devices such as graphic display adapters, disk controllers, etc. can also attach directly or indirectly (e.g., through a host bridge) to the PCI bus.

A bridge chip is provided between the PCI bus and the ISA bus in order to provide communication between devices on the two buses. The bridge chip essentially translates the ISA bus cycles to PCI bus cycles, and vice versa.

In a digital computer, a microprocessor operates on data stored in a main memory. Since there are practical size limitations on the main memory, bulk memory storage devices are provided in addition to and separately from the main memory. When the microprocessor wants to make use of data stored in bulk storage, for example, a hard disk, the data is moved from the hard disk into the main memory. This movement of blocks of memory inside the computer is a very time consuming process and would severely hamper the performance of the computer system if the microprocessor were to control the memory transfers itself.

In order to relieve the microprocessor from the chore of controlling the movement of blocks of memory inside the computer, a direct memory access (DMA) controller is normally used. The DMA controller receives information from the microprocessor as to the base location from where bytes are to be moved, the address to where these bytes should go, and the number of bytes to move. Once it has been programmed by the microprocessor, the DMA controller oversees the transfer of the memory data within the computer system. Normally, DMA operations are used to move data between input/output (I/O) devices and memory.

Many computer systems now use some type of "power management" to temporarily place the computer system into a suspend mode in which power is conserved. For example, if the computer system is a laptop computer, a power management device may cause a computer system to enter the suspend mode to save power whenever the laptop is closed. The suspend mode may also be entered if a key on the keyboard has not been pressed for a prolonged period of time. There are numerous other events which will cause a power management device to place the computer system into a suspend mode, and there are numerous available power management devices.

After some period of time, or a defined event occurs (such as the opening of the laptop cover), the power management device enters a resume mode. In the resume mode, the power management device essentially restores the computer system to the state it was in before it entered the suspend mode. This requires that certain information be stored before the computer system enters the suspend mode. One type of information that needs to be stored and available for the resume mode is the addresses contained in address registers of the DMA controller. In particular, the base addresses, indicating the starting address for a destination of transfer data, need to be stored so that the power management software will know where an original DMA transfer address was prior to entering the suspend mode.

In prior power management arrangements, "shadow registers" were used to store the DMA address (the initial base address) when the base address register and the current address register in the DMA controller are written with the base address. (When the current address register is written, the base address register is written simultaneously.) In other words, the power management device will take a write cycle off the PCI bus, although not claiming it as its own, and place the DMA address (the base address) into its shadow register. These shadow registers are needed since the base registers in conventional DMA controllers are not readable, and the power management device would otherwise have no way of knowing what the base address was prior to entering the suspend mode.

This problem is even greater when the computer system is equipped with a scatter/gather programmer that programs the DMA controller with the base address, since the scatter/gather programmer is closely coupled to the DMA controller. This close coupling means that during programming of the DMA controller, the base address does not appear on a bus from which the power management device could see the write cycle and write the base address into a shadow register.

A major disadvantage to using shadow registers is the amount of circuitry and logic that these shadow registers add to the design. A shadow register is needed for each base register in a DMA controller. In a conventional DMA controller for 16-bit operation there are fourteen base registers. If this is extended to 32-bit operation, a DMA controller may have twenty-eight base registers. Power management requires a separate shadow register for each of these twenty-eight base registers.

There is a need for a bridge chip that supports power management, including the saving of base addresses in a DMA controller, without providing a shadow register for each base address register in the DMA controller.

This and other needs are met by the present invention which provides a bridge for interfacing between buses of a computer system that has a first bus and a second bus, the bridge comprising a direct memory access (DMA) control circuit programmable by programming signals to perform a DMA transfer and having registers for storing base addresses and registers for storing current addresses. The base addresses and the current addresses indicate destinations of transfer data in the DMA transfer. A power management device is coupled to the DMA control circuit and has logic for causing the computer system to enter a suspend mode. A base address register read circuit is coupled between the base address registers and the power management device and is responsive to a CPU to provide one of the base addresses to be read by the CPU to disk storage.

The earlier stated needs are also met by another embodiment of the present invention which provides a direct memory access (DMA) control circuit programmable by programming signals to perform a DMA transfer in a computer system that includes a power management device that causes the computer system to enter a suspend mode. The DMA control circuit comprises base address registers for storing base addresses and current address registers for storing current addresses. The base addresses and the current addresses indicate destinations of transfer data in the DMA transfer. A multiplexer circuit is coupled to the base address registers and the current address registers. The multiplexer circuit is responsive to a signal from the power management device to provide a base address to be read from one of the base address registers by the CPU prior to the power management device causing the computer system to enter the suspend mode, and otherwise producing the current addresses as an output of the DMA control circuit.

The present invention provides the advantages of reducing the amount of logic required by a power management device since shadow registers are no longer required. Instead, since the base address register is readable according to the present invention, the base address from the base address register is read by the CPU and stored on disk prior to the computer being placed into the suspend mode. When the resume operation is started, the power management device can simply reprogram the DMA controller with the base address and restart any DMA transfer operation that was interrupted by the suspend mode.

The advantages of the present invention are particularly apparent when used in a system supporting 32-bit DMA addressing, as with the PCI bus, since an even larger number of registers would otherwise have to be shadowed than for 16- or 24-bit DMA addressing. Furthermore, the present invention improves diagnostic capabilities by providing a mechanism by which the base address registers can be read. During a diagnostic operation, for example, the base address registers can be written and then read for testing purposes.

The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

FIG. 1 is a perspective view of a computer system of the present invention.

FIG. 2 is a block diagram of the computer system of FIG. 1 constructed in accordance with an embodiment of the present invention.

FIG. 3 is a block diagram of an exemplary embodiment of a DMA control circuit constructed in accordance with an embodiment of the present invention.

FIG. 4 is a basic block diagram of a DMA control circuit constructed in accordance with an embodiment of the present invention having high address extension and high count extension logic.

FIG. 5 is a block diagram of an exemplary embodiment of the high address extension and high count extension logic.

FIG. 6 is a block diagram of a scatter/gather unit constructed in accordance with an embodiment of the present invention.

FIG. 7 is a timing diagram of an exemplary scatter/gather program cycle according to the present invention.

FIG. 8 is a state diagram of a scatter/gather program controller constructed in accordance with an embodiment of the present invention.

FIG. 9 is a block diagram of an exemplary embodiment of a power management device according to the present invention.

FIG. 10 is a block diagram of a page register and a multiplexer circuit constructed in accordance with an embodiment of the present invention.

FIG. 11 is a block diagram of the computer system of FIG. 1 constructed in accordance with an embodiment of the present invention.

With reference now to the Figures and in particular with reference to FIG. 1, a conventional computer, or PC, designated 10, is of the environment to which the invention has particular utility. Computer 10 which preferably, but not necessarily, is of a type utilizing an IBM personal computer or a similar system, includes a console housing 12 in which a circuit board containing the necessary circuitry including a microprocessor and BIOS chips, controllers, random access memory and other hardware are arranged. The computer will also include a video display 14 and a keyboard 16 connected to the housing 12 through cable 18. Mass storage media includes a hard disk drive within the housing and is non-accessible to the user, and user-accessible floppy disks, as well as, optionally, CD-ROM drives 20 and 22.

FIG. 2 is a block diagram of a computer system constructed in accordance with an embodiment of the present invention. The system includes a PCI bus 30, an ISA bus 32, with a plurality of ISA masters 36 and ISA slaves 38. A plurality of PCI memory slaves 40 are coupled to the PCI bus 30.

The bridge chip 34, which provides an interface between the PCI bus 30 and the ISA bus 32, contains an ISA interface 42 coupled between the ISA bus 32 and a system bus 44. A PCI interface 46 is provided between the PCI bus 30 and system bus 44. The bridge chip 34 also has a DMA control circuit 50, programmable I/O (PIO) registers 52, and a scatter/gather unit 54. The DMA control circuit 50 is coupled to the ISA bus 32. A power management device 35 is arranged on the bridge chip 34 in the embodiment of FIG. 1, although in other embodiments it is located off-chip. The power management device 35 is coupled directly to the DMA control circuit 50 and is also coupled to the PCI bus 30. The function and operation of the power management device 35 will be described in more detail later.

The ISA bus interface 42 in the bridge chip 34 translates ISA bus cycles into system bus cycles for use by the bridge chip 34. The PCI bus interface 46 converts PCI bus cycles from the PCI bus 30 into system bus cycles for the bridge chip 34. The DMA control circuit 50 controls DMA control of memory accesses within the system. The DMA control circuit 50 provides a plurality of separate DMA channels over which memory accesses involving the individual ISA masters 36 are respectively communicated.

The DMA control circuit 50 is programmable over either the ISA bus 32 as in the prior art, or by the scatter/gather unit 54. Allowing the DMA control circuit 50 to still be programmed over the ISA bus 32 permits compatible PIO operation to occur when the DMA controller is programmed, so that if compatibility software is running, it appears that the DMA control circuit 50 is residing on the ISA bus 32. The operation of the scatter/gather unit 54 will be described later with respect to FIGS. 6 and 7.

Either the DMA control circuit 50 or the ISA bus master 36 can generate transfer cycles, since the DMA control circuit 50 acts as a bus master on the ISA bus 32. Both the ISA master 36 and the DMA control circuit 50 can access memory located on either the ISA bus 32 or the PCI bus 30. For ease of explanation in the following description, however, examples will be described in which the ISA bus master 36 is generating transfer cycles. When this occurs, the DMA control circuit 50 acts as an arbitration device.

When the ISA bus master 36 generates a transfer cycle, the ISA bus master 36 produces a memory address. This is the starting address and indicates the designation of transfer data.

As stated earlier, the 32-bit addressing capability of the PCI bus 30 provides a memory addressing capacity of 4 gigabytes. By contrast, since an ISA bus master 36 can only generate 24-bit addresses, it is limited to addressing memory within a 16 megabyte segment. The prior art solution uses external circuitry to set the most significant bit of a 32-bit PCI address high, when a master signal is detected on the ISA bus 32. This reallocates the 16 megabytes of memory to a specific different location within the 4 gigabytes of memory. However, all accesses to the memory on the PCI bus 30 by the ISA bus masters 36 would be to this same location. By contrast, the present invention provides memory access to any memory location within the 4 gigabytes of memory addressable over the PCI bus 30.

FIG. 3 is a block diagram of an exemplary embodiment of a DMA control circuit 50 which provides dynamic configuration of the DMA channels. The DMA control circuit 50 includes a pair of cascaded DMA controllers 60, 62 and a multiplexer circuit 64.

Preferred embodiments of the present invention use a commercially available DMA controller, such as the 8237 DMA controller manufactured by Intel. Each 8237 DMA controller provides four separate DMA channels which can be used independently for memory transfers. Certain well-known computer systems, such as the IBM PC/AT design, contain two 8237 DMA controllers. The DMA control circuit 50 of FIG. 3 also uses two conventional DMA controllers 60, 62. One channel of the first DMA controller 60 is used to cascade the second DMA controller 62, as is known in the prior art. The pair of DMA controllers 60, 62 therefore provide a total of seven DMA channels, with four channels provided by the first DMA controller 60, and three channels provided by the second DMA controller 62.

A number of different signals, such as the clock signal, etc., have not been shown in FIG. 3 so as not to obscure the invention. However, one of ordinary skill in the art would recognize that these conventional signals would be used in practice.

The first and second DMA controllers 60, 62 produce sixteen bits (15:0) of the memory address to the PCI bus 30. As will be explained in more detail with respect to FIG. 5, the DMA control circuit 50 also has a low page register, a high page register, and a high count register, although these registers can in certain embodiments be separate from the DMA control circuit 50.

The first DMA controller 60 provides DMA channels 0-3 in response to request signals DREQ#0-DREQ#3. Addresses are programmed in the DMA controller 60 over lines ADR#0-ADR#3. Data is received over input lines DAT#0-DAT#7. Acknowledge signals are generated by the first DMA controller 60 as signals DACK#0-DACK#3.

The eight least significant bits of a 16-bit address are produced as output signals on pins A0-A7. The eight most significant bits of the 16-bit address are provided as outputs from D0-D7 when the address strobe signal ADSTB is enabled. When the address strobe is not enabled, the data signals are provided as the output from D0-D7. A hold request output (HRQ) from the first DMA controller 60 is coupled to the DREQ#0 input of the second DMA controller 62 and DACK#0 of the second DMA controller 62 is connected to the hold acknowledge input (hlda) of the first DMA controller 60 to provide the cascading of the pair of controllers 60, 62, as is well known in the art.

The second DMA controller 62 provides DMA channels 5-7 and receives DREQ#5-DREQ#7 at inputs DREQ#1-DREQ#3. The second DMA controller 62 provides at output pins DACK#1-DACK#3 the output signals DACK#5-DACK#7. The outputs of the address lines A0-A7 and data lines D0-D7 are the same as for the first DMA controller 60. Data lines D0-D7 receive as inputs DATA#0-DATA#7, the same as the first DMA controller 60. However, the second DMA controller 62 receives at inputs A0-A3 the signals ADR#1-ADR#4. This ensures that the first and second DMA controllers 60, 62 do not respond to the same I/O programming address.

The addresses generated by the first and second DMA controllers 60, 62 are received by the multiplexer circuit 64, shown in dashed lines. The multiplexer circuit 64 comprises two 8-bit address latches 66, 68, an 8-bit 2-to-1 multiplexer 70, and two 8-bit 4-to-1 multiplexers 72, 74.

The 8-bit 2-to-1 multiplexer 70 is a data multiplexer that receives the data signals D0-D7 from each of the first and second DMA controllers 60, 62. The data multiplexer 70 selects which set of data signals will be produced as output data (7-0) when reading the registers out of the first and second DMA controllers 60, 62.

When the data lines D0-D7 of the first and second DMA controllers 60, 62 are used as address lines for the most significant bits 15-8, these bits are latched in the respective 8-bit address latches 66, 68. The latches 66, 68 are under the control of the address strobe signal ADSTB from the first and second DMA controllers 60, 62.

The 8-bit 4-to-1 multiplexer 72 is a least significant bit multiplexer that produces as an output the least significant 8 bits of each address. The 8-bit 4-to-1 multiplexer 74 is a most significant bit multiplexer and produces the most significant bits 15-8 of each address.

The first multiplexer 72 has four inputs. At the first input are the least significant 8 bits of the address generated by the first DMA controller 60. At the second input, the first multiplexer 72 receives the least significant seven bits (6-0) of the least significant bits of the address generated by the first DMA controller 60. However, these bits are shifted to the left by one position and a zero is provided as the least significant bit of the 8-bits input into the multiplexer 72. The second input therefore represents the least significant bits of the memory address shifted by one position to the left, with a zero being placed into the least significant bit position. The third input of the first multiplexer 72 are the least significant 8 bits (7-0) of the unshifted memory address generated by the second DMA controller 62. The fourth input of the first multiplexer 72 receives a shifted memory address from the second DMA controller 62. This shifted memory address has been shifted in the same manner as the memory address received at the second input.

The second multiplexer 74 receives at its first input the most significant bits (15-8) of the address generated by the first DMA controller 60. These bits are provided by the 8-bit address latch 66. At its third input, the second multiplexer 74 receives the most significant bits (15-8) generated by addresses from the second DMA controller 62, through the 8-bit address latch 68. The second multiplexer 74 receives at its second and fourth inputs a shifted version of the most significant bits from the bits from the first and second DMA controllers 60, 62, respectively. In bit position 8, the output of address line A7 is provided. The upper seven bits in positions 15-8 are provided by bits (14-9) of the shifted memory address. Thus, the address bits provided at the second and fourth inputs correspond to bits (14-7) of the unshifted memory address, but shifted into positions 15-8. The second multiplexer 74 therefore receives the eight most significant bits of an unshifted memory address from each of the first and second DMA controllers 60, 62 and the eight most significant bits of a shifted memory address from each of the first and second DMA controllers 60, 62.

For reasons to be described later, it is necessary to preserve the shifted bit 15 so that the information contained in this bit is not lost. The shifted bit 15 is provided at outputs (one for each DMA controller 60, 62) as address bit 16 (DMA1A16, DMA2A16).

The DMA control circuit includes a programmable register 76 which contains information for each DMA channel as to whether that channel is an 8-bit channel or a 16-bit channel. The acknowledge signals (DACK#0-DACK#3; DACK#5-DACK#7) for the seven DMA channels are provided as inputs to a seven-to-two multiplexer 77 that produces an output signal that indicates which DMA controller 60 or 62 carries the DMA channel that will be used for the transfer. Based upon the information in the register 76 and the signal from the multiplexer 77, simple encoding logic 79 produces a select signal that causes the multiplexers 72, 74 to provide the required output.

In preferred embodiments of the invention, upon system power-up, the register 76 defaults to the IBM PC/AT design of configuring DMA channels 0-3 as 8-bit channels and DMA channels 5-7 as 16-bit channels.

Two examples of operation will be described. Assume for the first example that DMA channel 5 is currently programmed in the DMA control circuit to be an 8-bit channel. When a DMA control cycle is performed, only unshifted memory address should be produced as an output from the DMA control circuit. The signal from the encoding logic 79 corresponding to DMA channel 5 being an 8-bit channel causes the first multiplexer 72 to select the third input having the least significant bits (7-0) of the unshifted memory address in the second DMA controller 62 to be produced at the multiplexer output as address (7-0). The same control signal causes the second multiplexer 74 to select the most significant 8-bits of the unshifted memory address from the second DMA controller 62 to produce at the multiplexer output the address bits (15-8). Since these bits have not been shifted from the address generated by the second DMA controller 62, either odd or even accesses to memory are possible, thereby providing 8-bit memory accesses.

In the second example, the DMA channel 2 is programmed to be a 16-bit channel provided by the first DMA controller 60. The control signal from the encoding logic 79 causes the multiplexer 72 to select the second input which corresponds to the least significant bits of the shifted memory address and a zero in the least significant position. This is provided at the multiplexer output as address bits (7-0) of a memory access. The control signal also causes the second multiplexer 74 to select the most significant bits of the shifted memory address (second input) to be produced as the output address bits (15-8).

The above are examples only, as DMA channel 5 can be readily programmed to be a 16-bit channel, while DMA channel 2 can be programmed to be an 8-bit channel.

The circuitry of FIG. 3 provides the lower 16 bits of a memory address. The upper 16 bits (31:16) are produced by high address and high count extension logic 80, as shown in the basic block diagram of FIG. 4. The logic 80 also produces a count extension by providing the upper 8 bits (23:16) of a 24-bit transfer count, which in the prior art has been limited to 16 bits. The logic 80 can be considered as part of the DMA control circuit 50 or a separate unit.

FIG. 5 is a block diagram of an exemplary embodiment of the high address and high count extension logic 80. The logic 80 includes a low page register 82, a high page register 84, and a high count register 86. The low page register 82 has been used in prior art designs (such as the IBM PC/AT) to provide another eight (8) bits of memory addressing capability, for a total of twenty-four (24) bit addressing capability, or 16 megabytes. The high page register 84 of the present invention provides an additional eight bits of memory addressing capability for a total of thirty-two (32) bit addressing capability, or 4 gigabytes. These additional 8 bits are sent to the PCI bus 30 (concatenated with the lower 24 bits of the memory address) by the high page register 84 when an ISA bus master 36 gains control of a DMA channel. The contents of the high page register 84 can be loaded with different values for each of the seven different DMA channels, so that the seven ISA bus masters 36 are able to access seven different 16 megabyte segments of memory within the 4 gigabytes of memory on the PCI bus 30. The high page register 84 is programmable, so that the allocation of a specific memory location for a 16 megabyte segment for an individual ISA bus master 36 can be changed.

The addition of a high page register to the existing design of a DMA controller circuit used in the IBM PC/AT computer system extends DMA transfer addresses from 24 bits to 32 bits, and all these bits may increment as well. This will be described below, as well as the features which allow incrementing and decrementing across any boundary. This was not possible in the original IBM PC/AT design, although it uses a low page register. Before describing the details of the logic 80, the concept of boundary crossing will be explained.

Assume that the starting address of a DMA transfer is 1. When a DMA controller is in an "increment" mode, the next DMA transfer will access address 2. Similarly, a DMA controller can decrement the address on subsequent transfers. However, in prior art devices such as the IBM PC/AT, the address could not be incremented or decremented across "boundaries" A boundary is located between bytes of an address, for example, such as between bits 15 and 16, and bits 23 and 24. When in the increment mode the next address causes the bits below a boundary (for example, bits 15:0) to become all zeros, and a 1 to enter the bit above the boundary (bit 16), the boundary has been crossed. In the IBM PC/AT design, the lower 16 bits can increment across boundaries, but the next 8 bits (23:16) cannot do so. Because of this limitation, the maximum number of transfers that can be performed in a PC/AT compatible system is 64K bytes for each transfer request. After 64K bytes have been transferred, if the starting address was originally zero, the same memory location would be re-accessed by the next address.

Now referring to FIG. 5, the CPU 20 initially programs the registers of a Programmed I/O control and registers unit 88 (hereinafter "PIO 88") with the starting address, the transfer count and the mode. This information in the registers of the PIO 88 provides the DMA control circuit 50 with the information it needs to perform a transfer. The PIO 88 and the high address extension architecture basically decode the address and I/O read and write commands to detect when to read or write several of the internal registers inside the first and second DMA controllers 60, 62 and the external registers for the DMA control circuit 50. The PIO 88 also generates chip select signals to the first and second DMA controllers 60, 62 for address decodes.

The chip select 1 signal is received at the chip select input of the first DMA controller 60. The chip select 2 signal is received at the second DMA controller 62. The chip select signals are asserted for cycles accessing the registers in the respective DMA controller 60, 62. Inside the PIO 88 are extended mode registers which are extensions to the mode registers inside the DMA controllers 60, 62. The extended mode register is an 8-bit register. Five of the bits contain information which indicates to the DMA controllers 60, 62 whether the channel an 8- or 16-bit channel (see register 76 in FIG. 3), what speed the cycle is going to be, and whether the transfer will be a compatible cycle or a faster version. The PIO 88 receives the acknowledge DACK signals which are used to select the values to read out of the high and low page registers during DMA transfers and ensure that the correct channel information is routed to the address bus.

The low page register 82 contains 14 bytes of information. It contains the base address register for all seven channels, i.e. 7 bytes, and the current address register for all seven channels, another 7 bytes. When the low page register 82 is programmed, both the base and the current address registers are written simultaneously. As the DMA control circuit 50 performs its transfer, the current address register in the low page register 82 is updated at the end of each writeback cycle.

The base address remains the initial value that was programmed in the base address register. This value supports a DMA mode termed "auto-initialize" in which upon completion of a DMA transfer, the base contents are restored to the current register and the same transfer can then proceed once again.

The high page register 84 is constructed essentially the same as the low page register 82. The high page register 84 contains the high page information for base and current addresses and an associated multiplexer to steer the data out.

An 8/7 bit up/down counter 90 is the counter for address bits 23-16 and is loaded by the low page register 82 upon initiation of a DMA transfer and drives address bits (23-16) out onto the bus through a multiplexer 92. The only bit that is actually multiplexed is bit 16. In this mode, the counter 90 counts in a manner that accounts for the fact that the least significant bit of the address is now being driven up from the lower 16 bits by shifting.

In order to provide IBM PC/AT compatibility, in unshifted operation, the 8/7 bit up/down counter 90 operates as a conventional 8 bit counter, since the least significant bit of the address is not being driven up from the lower 16 bits. When the low page register 82 is accessed, the high page register 84 is cleared (all zeros placed into the register 84) and counting of the high address extension is disabled. The accessing of the lower order addresses or counts places "ff" into the high count register 86. These actions cause the DMA control circuit 50 to operate and appear to the other devices as a PC/AT compatible DMA control circuit. The accessing of the high page register 84 automatically changes the DMA control circuit 50 from the PC/AT compatible mode to the high address extension mode, in which high address counting is enabled.

A high page 8-bit up/down counter 94 is loaded with the contents of the high page register 84 upon initiation of the DMA transfer. Both the 8-bit up/down counter 94 and the 8/7-bit up/down counter 90 are cascaded with a carry-out bit. The 8/7 up/down counter carry-out bit feeds into the carry-in of the 8-bit up/down counter 94 to propagate counts across address boundaries. The carry-in to the 8/7-bit up/down counter 90 is driven by a 4-to-1 multiplexer 96 of boundary crossing detection logic 98.

The up/down counters 90, 94 can also be referred to as "address counters".

The 4-to-1 multiplexer 96 selects its output in dependence on whether the DMA control circuit 50 is in 8-bit mode or 16-bit mode and whether it is incrementing or decrementing. The signals entering the AND gates 100-106 driving the multiplexer 96 are the address bits from the first and second DMA controllers 60 and 62, i.e., the lower 16 bits of the address.

When the DMA is in an increment count by bytes mode, i.e. an increment by 8-bit mode, the first AND gate 100 of the multiplexer 96 is sampled. If "ff" (hexadecimal) is sampled, this indicates to the DMA control circuit 50 that the address is about to cross a boundary upon a completion of the current transfer. If the current transfer is to "ffff", the next transfer should then be to 10000. To increment that bit properly, the carry-in bit will now become activated to the 8/7-bit up/down counter 90.

If the DMA control circuit 50 is presently in the 16-bit mode and an increment mode, the second AND gate 102 is sampled. A boundary will be crossed if the current address is "fffe" because the next address will be 10000. This situation also causes the carry-in to be provided to the 8/7-bit up/down counter 90.

The third input to the multiplexer 90 from the AND gate 104 is sampled when the DMA control circuit 50 is in the decrement mode and an 8-bit transfer mode (i.e., counting by bytes). When the address is 0000, the next decrement will cross a boundary. A carry is generated to the counter 90 to allow it to decrement properly so that the next count will be "ffff". This causes the 8/7-bit up/down counter 90 to decrement.

The fourth input to the multiplexer 96 from the AND gate 106 is used in the decrement mode and a 16-bit transfer mode. When the lower address ends in 0001, this indicates to the 8/7-bit up/down counter 90 that there will be a decrement across the 16-bit boundary. Again, a carry is generated to the counter 90 so that the counter 90 will decrement properly across the boundary.

A 2-to-1 8-bit multiplexer 108 selects the contents of the low page register 82 or the contents of the high page register 84. This multiplexer 108 allows programmed I/O reads of these registers 82, 84 and is decoded by the PIO 88. Preceding each of the low page and the high page registers 82, 84 is an 8-bit 2-to-1 multiplexer 110, 112. The 8-bit 2-to-1 multiplexers 110, 112 selects either: the data from the internal system bus of the bridge chip 34 to the DMA control circuit 50 to write the page registers 82, 84 initially; or the outputs of the up/down counters 90, 94 to do a write back operation to the page registers 82, 84. This allows the current address which has just been incremented to be written back into the page registers 82, 84.

To control this high address extension and high count extension logic 80, a counter control state machine 114 is provided. The state machine 114 loads the contents of the low page and high page registers 82, 84 into the counters 90, 94 when either of the first or second DMA controllers 60, 62 becomes active. The state machine 114 increments those counters 90, 94 upon completion of a transfer cycle. As long as transfer cycles are occurring and the addresses are incrementing, count instructions will be allowed to change the counters if a carry-in is detected from the boundary crossing detection logic 98. If a carry-in is not detected, the counters 90, 94 will not change their state, and so will not change their value. If an address boundary is crossed, the carry-in will be enabled and a count enable will be enabled by the counter control state machine 114 simultaneously to cause the counters 90, 94 to increment or decrement.

Upon completion of a DMA transfer cycle or series of DMA transfer cycles, the contents of the counters 90, 94 are written back into the page registers 82, 84 by the counter control state machine 114. The 8-bit 2-to-1 multiplexers 110, 112 at the inputs of the low page and high page registers 82, 84 are selected by the state machine 114 to use the counter output contents and perform a write back cycle into the low and high page registers 82, 84. This completes the DMA transfer cycle and the current address register is not updated.

The 2-to-1 multiplexer 116 receives bit 16 from the first and second DMA controllers 60, 62 as DMA1A16 and DMA2A16. The multiplexer is used to select between these shifted address 16th bits generated from the first or second DMA controller 60 or 62 for purposes of a 16-bit shifted address operation. The output of the multiplexer 116 is provided to the 2-to-1 multiplexer 92 which ultimately is selected to generate bit 16 of the address which is driven externally by the DMA control circuit 50. This allows the overwriting of bit 16 for 16-bit address shifter compatibility.

The high count register 86 provides a count extension to 24 bits. The operation of this high count register 86 is analogous to the address extension logic in that the same control signals from the counter control state machine 114 control the loading of the high count register 86 and the incrementing of the high count and writing back the high count value to the high count register 86. The high count register 86 contains 7 bytes; the current count for each of the seven DMA channels.

As with the low and high page registers 82, 84, the high count register 86 is coupled to an 8-bit 2-to-1 multiplexer 118 and an 8-bit down counter 120. A down counter is used since the count is only decremented, and is not incremented.

A signal from the first and second DMA controllers 60 and 62 to an AND gate 122 detects when all internal bits from these controllers 60, 62 are 1 in the 16-bit transfer count. This is the indication to the high counter 120 to decrement.

The count signals are sampled directly to determine when a decrement boundary is going to be crossed in order to clock the high count extension. Unlike the address extension logic which is programmed through the PIO 88, in preferred embodiments, the count extension is only programmable by a scatter gather program. Scatter gather programs are well-known to those of ordinary skill in the art.

With the present invention as described above, an ISA bus master 36 is able to operate in a conventional manner to address 16 megabytes. The accessing of memory above the 16 megabyte limit and the count extension is transparent to the ISA bus masters 36, as it is performed by the bridge chip 34 using the DMA control circuit 50.

In order to provide backward compatibility, the DMA controller circuit defaults to PC/AT compatible mode, i.e. 16-bit addressing with a low page register. Once the high order byte is programmed, however the DMA control circuit 50 changes from the default PC/AT mode into a 32-bit mode.

FIG. 6 is a block diagram of an exemplary embodiment of the scatter/gather unit 54 depicted in FIG. 2. The scatter/gather unit 54 is connected to the DMA control circuit 50 on the bridge chip 34.

Before discussing the exemplary embodiment of the scatter/gather unit 54, a brief explanation of scatter/gather will be provided. The programming of a DMA controller by a central processing unit (CPU) requires the intervention of the processor for a relatively long time, since program input/output (I/O) cycles are run with standard ISA cycles. The processor cannot run other programs when it is programming the DMA controller. To improve system efficiency, scatter/gather units take over from the CPU the programming of the DMA controller.

A scatter/gather unit essentially fetches descriptors, which are small blocks of memory, and programs these descriptors into the DMA controller. A descriptor includes a DMA address, a transfer count, and an end of link bit. The DMA address indicates the address where the data will be sent to or retrieved from; the transfer count indicates how large a block of data will be transferred; and the end of link bit indicates whether or not chaining is being used. When chaining is used, so that the end of link bit is cleared, the scatter/gather unit recognizes that there is another descriptor with a subsequent eight bytes (contiguous addressing), which contains another scatter/gather transfer.

In operation, therefore, the CPU will program a scatter/gather descriptor table in memory, which requires much less time than writing to slow I/O devices. The CPU then sends an instruction to the DMA controller to instruct it to prepare to perform a transfer, and an instruction to the scatter/gather unit to begin the transfer. The CPU's role is complete at this point and the scatter/gather unit retrieves the descriptor information from memory and programs the DMA controller with the information. The DMA controller is activated and operates as usual. The DMA controller is not aware that it was programmed by a scatter/gather unit and not the CPU with slow I/O accesses.

The "scatter" operation is a DMA transfer from I/O to memory, so that data is being read from a peripheral I/O device or a floppy disk, etc., and is scattered into memory. In a "gather" operation, the DMA controller is programmed to read memory and write to I/O by gathering different non-contiguous segments of memory and then writing them to I/O in a continuous manner.

The scatter/gather unit 54 of the present invention has a PCI bus master 130, a PCI slave 132, a program controller 134, and a multiplexer 136. The PCI master 130 fetches descriptor control blocks from memory, which can be located on either the ISA bus 32 or the PCI bus 30. The PCI slave 132 is coupled to the PCI bus 30 and functions as the programmed I/O registers for the scatter/gather unit 54. The PCI slave 132 contains a plurality of registers which stores for the scatter/gather unit 54 the starting address of the descriptor table in memory, as well as status and commands.

The program controller 134 uses the data fetched from memory by the PCI master 130 and programs this data into the DMA control circuit 50. This data includes a 32-bit DMA address and a 24-bit transfer count. The end of link bit is placed into a status register of the scatter/gather unit 54.

The multiplexer 136 receives from the program controller 134 at one set of inputs an I/O write signal (sgb.sub.-- iow.sub.-- n), an 8-bit data signal (sgb.sub.-- data), and a 12-bit address signal (sgb.sub.-- addr). The multiplexer 136 receives at another set of inputs that are coupled to the ISA bus 32 an I/O write signal (isa.sub.-- iow.sub.-- n), an 8-bit data signal (isa.sub.-- data), and a 12-bit address signal (isa.sub.-- addr). The address signal is an I/O address that selects the appropriate DMA register in which the data contained in the data signal will be written.

In response to a select signal (sgb.sub.-- active) from the program controller 134, the multiplexer 136 selects which of the sets of input signals are produced as output signals to program the DMA control circuit 50. When the scatter/gather unit 54 is to program the DMA control circuit 50, the select signal causes the multiplexer 136 to select the signals directly from the program controller 134. When compatibility software is run on the system, the scatter/gather unit 54 is inactive and the select signal causes the multiplexer 136 to program the DMA control circuit 50 with the signals from the ISA bus 32. The DMA control circuit 50 is not aware of the source of the programming signals.

The present invention takes advantage of the location of the scatter/gather unit 54 on the bridge chip 34 by performing the programming operations of the DMA control circuit 50 (also on the bridge chip 34) at the 33 MHz speed of the bridge chip 34. The scatter/gather unit 54 does not run any ISA cycles at 8 MHz, and is free from compatibility requirements of an ISA cycle. Although the present invention allows the DMA control circuit 50 to be programmed with ISA bus cycles for compatibility reasons, programming of the DMA control circuit 50 by the program controller 134 is approximately an order of magnitude faster than with ISA bus cycles.

An exemplary program cycle using the scatter/gather unit of the present invention is depicted in the timing diagram of FIG. 7. In this example, the PCI master 130 has already fetched the descriptor information from memory. The scatter/gather unit 54 has been initiated by the CPU 41 and is therefore active. The select signal causes the multiplexer 136 to select the signals from the program controller 134 to directly program the DMA control circuit 50, without running ISA bus cycles on the ISA bus 32.

During clocks 1 and 2, a byte pointer is cleared by the assertion of the address for a DMA byte pointer clear operation. A byte pointer is needed in the 8237 DMA controllers 60, 62 since only an 8-bit I/O address is used to program the 16-bit address in the DMA controllers 60, 62. The byte pointer points to either the low order byte or the high order byte. The byte pointer is cleared in the first operation so that the pointer is pointing to the least significant byte so that the least significant byte in the DMA controller 60 or 62 will be written with the current address.

During clocks 1 and 2, the data (chnl) sent to the DMA control circuit 50 is the DMA channel number (0-3; 5-7) that is being accessed. Note that the DMA control circuit 50 writes the address and data only when the write signal IOW# is active (low).

During clocks 3-6, the current address registers within the DMA controllers 60, 62 are written to. The current.sub.-- address is the address of the register within the DMA controllers 60, 62 that is being written to, and addr0 is the current address bits 7-0 for the DMA channel that is being accessed. The data addrl is the current address bits 15-8 for the DMA channel that is being accessed.

During clocks 7 and 8, an address (lowpage) for the low page register 82 is provided and addr2, the current address bits (23-16) for the DMA channel, are written to this address. Similarly, the high page register 84 is written to in clocks 9 and 10, with data addr3 (the current address bits (31-24) at the hi.sub.-- page address.

The clear byte pointer operation and the writes to the current address registers are accesses directly to the internal design of the DMA controllers 60, 62. These I/O writes are asynchronous because the DMA controllers 60, 62 latch the information on the rising edge of the IOW# signal itself. Thus, the address and data must remain valid for one clock after the actual I/O cycle to ensure that the hold times of the DMA controllers 60, 62 are met. By contrast, the low page register 82 and the high page register 84 are synchronous registers. The address and data need not remain valid for one clock after the actual I/O cycle. However, the address and data are driven one clock prior to the I/O cycle to ensure that setup times are not violated. The combination of these requirements causes the two clock delay between writing to the current address register and the low page register.

The byte pointer for the count is cleared in clock 11-13, restoring the internal byte pointer of the DMA controllers 60, 62 to the lowest byte of the count. During these cycles, the data (chn1) sent to the DMA control circuit 50 is the DMA channel number (0-3; 5-7) that is being accessed.

The current count address is the address where the current count bits (15-0) will be written to, during clocks 14-17. The data being written to this address are cnt0 (current count bits (7-0)) and cnt1 (current count bits (15-8)).

In clocks 18 and 19, the high count register is addressed (highcnt) and written to with cnt2 (current count bits (23-16)). The programming I/O cycle is then complete and the DMA control circuit 50, now programmed, performs the DMA transfer.

The current count registers are asynchronous so that the address and data must remain valid for one clock after the actual I/O cycle to ensure that the hold times of the DMA controllers 60 and 62 are met. The high count register is synchronous and the address and data need not remain valid for one clock after the actual I/O cycle. However, the address and data are driven one clock prior to the I/O cycle to ensure that setup times are not violated. There is therefore a two clock delay between writing to the current count register and the high count register.

The scatter/gather unit 54 supports conventional scatter/gather functions, such as chaining through an end of link bit.

With the present invention, the amount of time required to run I/O program cycles to the DMA control circuit 50 are significantly reduced in comparison to the prior art. The I/O program cycles are "hidden cycles" since they are not run on the ISA bus and are thus not observable off the bridge chip. Very fast DMA register accesses can therefore be performed. For comparison purposes, with the present invention, an I/O write cycle can be performed in one 33 MHz clock. By contrast, in the prior art, each I/O write cycle requires several (for example eight) 8 MHz clocks on the ISA bus.

The concepts of data chaining and block mode operation have already been described briefly. In both of these operations, the DMA control circuit 50 will perform a DMA transfer and then enter into an idle state. In order to perform the next transfer in the chain or in the block, the DMA control circuit 50 needs to be reinitiated. As explained below, the program controller 134 of the present invention reinitiates the DMA control circuit 50 to cause the DMA control circuit 50 to perform the additional transfers in the chain or block.

FIG. 8 is a state diagram of the program controller 134. In state 150, the program controller 134 is in an idle state. When it is activated by the CPU 41 (see FIG. 2) to perform a scatter/gather operation, the program controller 134 enters state 152 in which the DMA byte pointer is cleared. (See also the timing diagram of FIG. 7). In state 154, the program controller 134 writes the current address bits (7-0) for the DMA channel. Similarly, in states 156, 158, and 160, the program controller 134 writes the current address bits (15-8), (23-16) and (31-24) respectively. The DMA byte pointer is cleared when the program controller 134 enters state 162. In state 164, the program controller 134 writes the current count bits (7-0) for the DMA channel. Similarly, in states 166 and 168, the program controller 134 writes the current count bits (15-8) and (23-16) respectively.

After the current count bits (23-16) are written into the DMA control circuit 50 by the program controller 134, the program controller 134 returns to an idle state via path 170. The program controller 134 did not have to intervene with the DMA control circuit 50 for this initial transfer since initial programming of the DMA transfer is defined to start the DMA control circuit 50 itself. This is because a mask bit in a mask register within the DMA controllers 60, 62 is cleared when the DMA control circuit 50 is initially programmed. When the mask bit is set, the DMA control circuit 50 ignores DMA requests. When the mask bit is clear, the DMA control circuit 50 will recognize DMA requests and arbitrate for control of the bus on behalf of the DMA slave. A mask register is provided in conventional 8237 DMA controllers, such as those used as the DMA controllers 60, 62 in the exemplary embodiment of the present invention.

Once programmed, the DMA control circuit 50 will perform its transfer (assuming that a slave has asserted a request DREQ#), and at the end of the transfer, will set its mask bit. Upon returning to the idle state 150, the program controller 134 will determine if chaining is enabled or not by checking the end of link bit in the first descriptor. If this bit is set, it indicates that this is the end of the transfer; if it is clear, then more data is to be transferred.

When chaining is enabled (i.e., the end of link bit is not set) the program controller 134 suppresses the terminal count signal generated internally by the DMA control circuit 50 from being asserted externally and halting a slave. After fetching the next 8-byte descriptor, the program controller 134 will re-execute the state machine as in states 152-168 to program the DMA control circuit 50 again. However, since chaining is enabled, the program controller 134 now enters state 172 instead of following path 170 back to an idle state. In state 172, the program controller 134 clears the mask bit that was set in the DMA control circuit 50 following completion of the first link. This reinitiates the DMA control circuit 50 to allow it to perform another DMA transfer. The program controller 134 returns to the idle state via path 174, and the DMA control circuit 50 performs the next DMA transfer in the chain and sets its mask bit upon completion of the transfer.

The above process continues for however many links there are in the data chain. Upon reaching the final link in the chain, the program controller 134 recognizes that the end of link bit is set and allows the terminal count to be asserted out of the DMA control circuit 50 to the devices on the ISA bus 32. This ends the DMA transfer of the chain.

Another mode of operation provided by conventional DMA controllers is the block mode. In this mode, when the DMA control circuit 50 gains control of the system, it will perform all of its transfers without relinquishing control of the bus until it reaches terminal count. However, after an initial transfer of a block, a slave can deassert DREQ#. If data chaining was desired when the DMA control circuit 50 was operated in the block mode, a conventional DMA control circuit 50 would not be aware that it is to start again to perform another block transfer of a link in the chain. The present invention supports data chaining when the DMA control circuit 50 is in the block mode.

The present invention takes advantage of a software initiated mechanism provided for conventional DMA controllers that allows software to initiate DMA transfers without the DMA controller receiving an external DMA request DREQ#. This is known as a "soft request". If the soft request bit is set in the soft request register of a DMA controller, the DMA controller will arbitrate for control of the bus on behalf of the DMA channel that has been soft requested and perform transfers until the requested transfer is completed. The soft request operation automatically clears the mask bit in the mask register. The soft request can only be used when the DMA controller is in block mode.

In the present invention, after state 168, an additional state machine path 176 is provided to state 178 in which the program controller 134 detects whether the block mode has been selected and whether a data chaining operation is being performed (i.e., is end of link bit clear). The program controller 134 in this state performs a set single soft request bit operation to the DMA control circuit 50 during subsequent data chaining program cycles. This ensures that after the first transfer block is completed and the DMA control circuit 50 is idle, that the DMA control circuit 50 is automatically restarted for all following links in the chain, without waiting for a DREQ# signal. By comparison, if the path to state 172 were followed (non-block mode operation), the DMA control circuit 50 would have to wait for another DREQ# signal before starting to perform the programmed transfer.

The present invention therefore supports data chaining by reinitiating the DMA control circuit 50, when the DMA control circuit 50 is either in block mode or non-block mode of operation.

FIG. 9 is a block diagram of an exemplary embodiment of a power management device 35 that is shown coupled to the DMA control circuit 50. The power management device 35 performs the conventional power management functions and as such, the blocks for performing these functions are not shown in FIG. 9.

The base registers of the first and second DMA controllers 60, 62, implemented as conventional 8237 DMA controllers, cannot be read. Shadow registers 202 are therefore required as in the prior art to store the base addresses written into the base registers of these DMA controllers 60, 62.

Although the exemplary embodiment uses shadow registers, this is only because conventional DMA controllers are used. The present invention still reduces the number of shadow registers otherwise required to store 32-bit DMA addresses by 14 bytes. This represents a significant improvement in the amount of logic and circuitry required for supporting the suspend function. In preferred embodiments of the DMA control circuit 50 that do not employ 8237 DMA controllers, however, all of the base address registers can be configured to be readable as in the present invention. This eliminates entirely the need for shadow registers.

The DMA control circuit 50 receives a base read signal from the configuration register 37 in the preferred embodiment, although the signal can originate from other sources such as the power management device 35 in other embodiments. This signal causes the DMA control circuit 50 to provide the upper two bytes of the base address of the current DMA channel for reading by the CPU 41 into storage such as onto a disk 43.

The configuration register 37 is located on the bridge chip 34 and is loaded by the CPU 41 to contain configuration bits that specify how the bridge chip 34 is presently configured. The only bit of the configuration register 37 relevant to the present invention is the base read bit which, when set, allows the power management device 35 to read the base address registers of the DMA control circuit 50 (at least the upper two bytes). The base read bit is toggled by the CPU 41, or the power management device 35 in certain embodiments, prior to entering the suspend mode.

The base read bit forms the base read signal to the DMA control circuit 50. FIG. 10 is a block diagram of an exemplary embodiment of one of the page registers 82 or 84 for explaining how the base read signal is used to allow the base address registers of the page register 82 or 84 to be read prior to the entering of the suspend mode.

The page register (low page register 82, for example) provides a separate 8-bit register for the base address and the current address for each of the seven DMA channels. Each of the seven 8-bit base address registers 208 receives a base address from a separate 8-bit 2-to-1 multiplexer 206. The multiplexers 206 are selectable to produce to the base address registers 208 either the base address fed back from the output of the base address register 208 or the base address input from the DMA programming by the CPU 41 or the scatter/gather unit 54.

Like the base address registers 208, there are seven 8-bit current address registers 212. These are coupled to 8-bit multiplexers 210 that are 4-to-1 multiplexers that are used to select between providing as inputs to the current address registers 212: (0) a fed back current address; (1) CPU write data (conditioned with the clear.sub.-- upper signal); (2) the base address; and (3) the output of the current address counter.

A base address register read circuit 214 is provided that allows the CPU 41 to read the base address in a base register 208. The base register read circuit 214, in this exemplary embodiment is implemented as a multiplexer circuit 214. The illustrated embodiment of the present invention shows the multiplexer circuit 214 as part of the low page register 82, but other embodiments provide the multiplexer circuit 214 separately from the low page register 82.

The multiplexer circuit 214 includes an 8-bit 7-to-1 base address register multiplexer 216 and an 8-bit 7-to-1 current address register multiplexer 218. A 7-to-3 encoder 220 decodes a register select signal and provides it to the multiplexers 216, 218 as their select signals.

The outputs of the multiplexers 216, 218 are provided to separate inputs of a power management multiplexer 222. The select signal for the power management multiplexer 222 is formed by the base read bit from the configuration register 37. When this bit has been set, the base read signal causes the power management multiplexer 222 to select the output of the base address register multiplexer 216. The base address that is then provided as an output can be sent to a data multiplexer (not shown) for instance, and subsequently read off the bridge chip 34 to the PCI bus 30. The address used to read the base address registers 206 is the current address I/O programming address.

When the base read bit is not set, the base read signal causes the power management multiplexer 222 to select the output of the current address register multiplexer 218 to be provided to the data multiplexer. The output of the current address register multiplexer 218 is also provided directly to the 8/7 bit up/down counter 90 (or to the 8-bit up/down counter 92 for the high page register 84).

In operation, when the power management device 35 is to cause the computer system to enter into a suspend mode, the base read bit in the configuration register 37 is toggled to be set, either by the CPU 41 or the power management device 35. The base read signal formed from this base read bit controls the power management multiplexer 222 to select the output (a base address) from the base address read register multiplexer 216 as an output. This base address is read by the CPU 41 and placed onto disk 43. Once the base address has been read from the low and high page registers 82, 84, the power management device 35 can continue its operations to place the computer system into a suspend mode.

Upon entering a resume mode, the CPU/power management software will reprogram the base addresses back into the low and high page registers 82, 84. In the exemplary embodiment which utilizes conventional 8237 DMA controllers 60, 62, the least significant 16 bits (2 bytes) of the base address are provided at this time from the shadow registers 202. In other embodiments which do not use conventional 8237 DMA controllers containing unreadable base registers, all of the bytes of the base address are provided from the stored address. Once the DMA control circuit 50 has been reprogrammed by the CPU 41, a DMA transfer that was interrupted by entering of the suspend mode can be started over.

Although not explicitly shown in the Figures, the present invention is extendable to the reading of base count registers. For example, in certain embodiments, the high count register 86 is provided with the same circuitry as the page registers 82, 84 as shown in FIG. 10. This permits the CPU/power management software to read the base counts in the high count register 86.

FIG. 11 is a block diagram of another embodiment of the computer system of FIG. 1. This embodiment is similar in most respects to that of FIG. 2, but the power management device 35 is not part of the bridge chip 34. In other embodiments, the power management device 35 is a functional block within the CPU 41 itself and can be considered software run by the CPU 41.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.