Compound Semiconductor Field Effect Transistor

1. Field of the Invention

The present invention relates generally to a compound semiconductor field effect transistor. More specifically, the invention relates to a compound semiconductor field effect transistor having a gate electrode formed in a recess portion.

2. Description of the Related Art

A compound semiconductor, typically GaAs, is characterized in higher electron mobility and lower noise in comparison with Si. Therefore, in the application for performing high speed and high frequency amplification with low noise, transistors employing the compound semiconductor have been frequently used. In such case, it is typical to use the compound semiconductor as MESFETs having Schottky gates for effectively utilizing high mobility property thereof. On the other hand, in case of a transistor for large output, a recess structure is employed for elevating a breakdown voltage by reducing concentration of electric field to a drain of the gate without increasing source resistance Rs.

FIG. 1 is a section showing the conventional GaAs field effect transistor (MESFET) for large output having a recess structure (hereinafter, this prior art will be referred to as "first prior art"). In FIG. 1, 1 denotes a semi-insulative GaAs substrate formed with an undoped GaAs buffer layer (not shown) on the surface. On the substrate, an n-type GaAs layer 2 serving as channel layer is formed. 0n the surface of the n-type GaAs layer 2, an n.sup.+ type GaAs layer 4 is formed for ohmic contact with a source/drain electrode. In the n.sup.+ -type GaAs layer 4 and the n-type GaAs layer 2, a recess portion 20 is formed by removing the entire depth of the n.sup.+ -type GaAs layer 4 and in the partial depth of the n-type GaAs layer 2 by etching, in a width greater than a predetermined gate region. At the center of the recess portion 20, a gate electrode 7 in Schottky contact with the n-type GaAs layer 2 is formed. On the other hand, on the n.sup.+ -type GaAs layer 4, a source electrode 8 and a drain electrode 9 are formed.

It should be noted that this type of the power MESFET has been known in IEEE Transactions on Electron Devices, Vol ED-25, No. 6, pp 563-567, "Improvement of the Drain Breakdown Voltage of GaAs Power MESFET's by a Simple Recess Structure", for example.

This first prior art has a problem in that a transistor characteristic may be degraded by applying a power at high temperature. FIG. 2 is a graph showing variation of a drain current when the transistor of FIG. 1 is formed to have a gate length of 1 .mu.m and a gate width of 5 mm, and 12 V drain voltage is applied with maintaining a temperature at 250.degree. C., as high temperature burn-in test. As can be seen a drain current is gradually lowered after about 500 hours. This degradation of the characteristics is considered to be caused by occurrence of crystal dislocation in the drain side end of the recess and by propagation of the dislocation due to continuing of application of power under high temperature.

After forming the shown MESFET, a protective layer is formed. Then, the MESFET is assembled in a package. Since the MESFET has different thermal expansion coefficient to the protective layer and the semiconductor crystal of the package or so forth, a stress is created within a crystal. For example, when the FET is mounted on a Cu package, since Cu has greater thermal expansion coefficient than GaAs, compression stress is exerted on the GaAs as cooled after mounting. Then, the stress resided within the crystal concentrates at the corner portion of the recess. Also, at the drain side end of the recess, concentration of the electric field is caused to concentrate the current at this portion. Therefore, when high voltage is applied to the drain as in the high temperature burn-in test, significant electric field concentration and high current concentration is caused at the drain side end of the recess to make the corresponding portion high temperature, locally. Then, by the stress as set forth above and concentration of the electric field and the current, crystal dislocation is caused at the end portion of the recess. When application of power is maintained, the defect thus caused extends to a channel region. As a result, degradation of the transistor characteristics is caused.

On the other hand, Japanese Unexamined Patent Publication (Kokai) No. Heisei 4-280640 proposes to provide a InGaAs layer serving as an etching stopper below a contact layer (hereinafter, this prior art will be referred to as "second prior art"). It should be noted that the semiconductor disclosed in the above-identified publication is not directed to a power transistor. FIG. 3 shows a section showing a structure of a transistor proposed in the above-identified publication. The shown transistor is fabricated through the following process.

On a semi-insulative GaAs substrate 11, an undoped GaAs layer 12 as a channel layer, n-type AlGaAs layer 13 as a carrier supply layer, an undoped GaAs layer 14 as a cap layer of a gate metal, InGaAs layer 15 as an etching stop layer and n.sup.+ -type GaAs layer 16 as a contact layer are grown in order. On the n.sup.+ -type GaAs layer 16, a source electrode 18 and a drain electrode 19 are formed. Thereafter, the n.sup.+ -type GaAs layer 16 and InGaAs layer 15 in the region where a gate electrode should be formed, are removed. Then, the removed portion, the gate electrode 17 is formed.

However, as set out later, in comparison with GaAs, InGaAs is not easily cause crystal dislocation and the propagation speed of the dislocation is low. Therefore, even when a means for forming the InGaAs layer on the upper portion of the recess is applied to the power MESFET, as disclosed in the second prior art, crystal dislocation is started from GaAs and thus, dislocation occurrence suppressing effect cannot be expected. Furthermore, since a stress at the hetero interface of GaAs/InGaAs is added, spreading of dislocation is rather promoted.

It is an object of the present invention to provide a compound semiconductor field effect transistor which has a structure difficult to cause dislocation and difficult to expand defect even when high temperature burn-in test is performed.

In a compound semiconductor field effect transistor according to the present invention, a first semiconductor layer to be a channel layer, a second semiconductor layer forming corner portions of a recess and a third semiconductor layer to be a contact layer for a source and a drain electrodes are deposited on a semi-insulative semiconductor substrate. The recess is formed through the third semiconductor layer and extends at the intermediate depth position of the second semiconductor layer. On the bottom of the recess, a gate electrode is formed. On the third semiconductor layer, the source and drain electrodes are formed. In the compound semiconductor field effect transistor according to the invention, the second semiconductor layer is formed of a material (InGaAs layer and so forth) having lower dislocation speed than the first semiconductor layer (GaAs layer and so forth).

In the alternative construction, the recess may be formed into a two level recess.

The corner portions of the recess are subjected to the greatest stress in the crystal, also subjected to concentration of electric field and current. Therefore, crystal dislocation is caused at this portion and propagate in the channel. However, since the material difficult to cause dislocation, such as InGaAs is arranged at the corner portions of the recess having the highest possibility of causing dislocation, occurrence of dislocation can be suppressed and propagation of defect can be suppressed to prevent degradation of characteristics.

As set forth above, since the field effect transistor according to the present invention forms the corner portions at the bottom of the recess of the material difficult to cause dislocation, such as InGaAs and so forth, occurrence of dislocation at the corner portion, propagation of the dislocation can be successfully suppressed. Therefore, degradation of characteristics in high temperature burn-in test can be improved.

The present invention will be understood more fully from the detailed description given herebelow and from the accompanying drawings of the preferred embodiment of the invention, which, however, should not be taken to be limitative to the present invention, but are for explanation and understanding only.

In the drawings:

FIG. 1 is a section showing the first prior art;

FIG. 2 is a characteristics curve chart showing a characteristic of the first prior art;

FIG. 3 is a section showing the second prior art;

FIGS. 4A and 4B are sections in the order of fabrication process steps for explaining a fabrication process of the first embodiment of a compound semiconductor field effect transistor according to the present invention;

FIGS. 5A-5C are sections in the order of fabrication process steps for explaining a fabrication process of the second embodiment of a compound semiconductor field effect transistor according to the present invention; and

FIG. 6 is a characteristics chart for explaining the effect of the present invention.

Next, the preferred embodiments of the present invention will be discussed with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be obvious, however, to those skilled in the art that the present invention may be practiced without these specific details. In other instance, well-known structures are not shown in detail in order to unnecessary obscure the present invention.

FIG. 4B is a section showing the first embodiment of the invention, and FIG. 4A is a section in an intermediate step for explaining the fabrication process thereof.

At first, as shown in FIG. 4A, a substrate 1 is fabricated by growing an undoped GaAs layer in a thickness of approximately 4000.ANG., as a buffer layer, by MBE (Molecular Beam Epitaxy) method on a semi-insulative GaAs substrate. On the substrate 1, n-type GaAs layer 2 in a thickness of 2000.ANG. and having Si concentration of 1.times.10.sup.17 cm.sup.-3, undoped InGaAs (i-In.sub.0.2 Ga.sub.0.8 As) layer 3 in a thickness of 200 .ANG., n.sup.+ -type GaAs layer 4 in a thickness of 1000.ANG. and having Si concentration of 3.times.10.sup.17 cm.sup.-3 are grown sequentially.

Next, by CVD (Chemical Vapor Deposition) method, a SiO.sub.2 layer 5 in a thickness of 4000.ANG. is deposited. Subsequently, a photoresist layer 6 having an opening 21 at a gate region is formed.

Next, with taking the photoresist layer 6 as a mask, the SiO.sub.2 layer 5 is etched by diluted hydrofluoric acid. In this case, as shown in FIG. 4A, an opening 22 is formed in the SiO.sub.2 layer 5 by side etching until the width becomes a recess width and in a length of 0.5 .mu.m, for example, beyond the opening width of the photoresist layer 6.

Next, as shown in FIG. 4B, with taking the SiO.sub.2 layer 5, in which the opening 22 is formed, as a mask, n.sup.+ -type GaAs layer 4 is etched with an etching liquid of phosphoric acid and hydrogen peroxide. After completely removing n.sup.+ -type GaAs layer 4 positioned within an opening 22 of the SiO.sub.2 layer 5, with the same etching liquid, the undoped InGaAs layer 3 is etched in an intermediate depth, i.e. in a depth of 100.ANG.. By this, a recess 23 is formed in the undoped InGaAs layer 3 and the n.sup.+ -type GaAs layer 4.

Next, vacuum deposition of A1 is performed. Then, A1 layer is formed on the photoresist layer 6 (FIG. 4A) and on the undoped InGaAs layer 3 at the portion positioned within the opening 21 of the photoresist layer 6. Subsequently, by removing the photoresist layer 6, the A1 layer on the photoresist layer 6 is lifted off to form a gate electrode 7 consisted of the A1 layer on the undoped InGaAs layer 3. The gate electrode 7 is formed at the center within the recess 23 in a width smaller than the recess 23. Finally, after removing the SiO.sub.2 layer 5, AuGe-Ni layer is deposited by vacuum deposition. By patterning the AuGe-Ni layer and subsequently providing heat treatment at 400.degree. C., the source electrode 8 and the drain electrode 9 in ohmic contact with the n.sup.+ -type GaAs layer 4 are formed.

In the compound semiconductor field effect transistor constructed as set forth above, since the material which is difficult to dislocate, such as InGaAs layer 3, is provided at the corner portion of the recess 23 where the dislocation is easily caused, the dislocation is prevented from propagating and defect is difficult to spread. Therefore,degradation of characteristics can be prevented.

Next, the second embodiment of the present invention will be discussed with reference to FIGS. 5A to 5C. FIG. 5C is a section of the second embodiment of a compound semiconductor field effect transistor, and FIGS. 5A and 5B are sections showing intermediate steps in fabrication process for explaining the fabrication process. The transistor of the shown embodiment is a MESFET having two level recess structure. In FIGS. 5A to 5C, the like elements to those in FIGS. 4A and 4B will be represented by the same reference numerals and the detailed description therefor will be neglected for avoiding redundancy and for keeping the disclosure simple enough to facilitate understanding of the invention.

At first, as shown in FIG. 5A, on the substrate 1 which is fabricated by growing undoped GaAs layer on the semi-insulative GaAs substrate, respective semiconductor layers 2, 3 and 4 are grown by epitaxial growth. Also, on the n.sup.+ -type GaAs layer 4, the SiO.sub.2 layer 5 is grown. The layer thickness, impurity concentration and so forth of these layers are the same as those in the first embodiment.

Subsequently, on the SiO.sub.2 layer 5, the photoresist layer 6 with an opening 24 in the gate region is formed. With taking this photoresist layer 6 as a mask, the SiO.sub.2 layer 5 is etched by the diluted hydrofluoric acid. In this case, as shown in FIG. 5A, the side etching of the SiO.sub.2 layer 5 should be limited at approximately 0.2 .mu.m, for example. After the side etching of the SiO.sub.2 layer 5, n.sup.+ -type GaAs layer 4 is etched in a depth of 300.ANG.. By this, a recess 25 is formed in the SiO.sub.2 layer 5 and n.sup.+ -type GaAs layer 4.

Next, as shown in FIG. 5B, the side etching of the recess 25 of the SiO.sub.2 layer 5 and the n.sup.+ -type GaAs layer 4 is expanded to 0.5 .mu.m. Thereafter, crystal etching is again performed so that the bottom of the recess 25 (first recess) at the upper portion lies at the intermediate position in the depth direction of the undoped InGaAs layer 3. For example, the undoped InGaAs layer 3 is etched in the depth of 100 .ANG.. At this time, at the center portion of the opening 24, etching is advanced at the portion corresponding to the width of the recess 25 formed in the n.sup.+ -type GaAs layer 4 in the process step of FIG. 5A. Therefore, a second recess 26 in the depth of approximately 300.ANG. is formed at the center portion of the first recess. In the second recess 26, the undoped InGaAs layer 3 is completely removed, and the surface of the n-type GaAs layer 2 is slightly removed.

Subsequently, with taking the photoresist layer 6 as a mask, gate electrode 7 and A1 layer 7a are formed on the n-type GaAs layer 2 at the center portion of the second recess 26 and on the photoresist layer 6 by vacuum deposition of the A1 layer.

Thereafter, as shown in FIG. 5C, together with the photoresist layer 6, an unnecessary A1 layer 7a on the photoresist layer 6 is removed. Furthermore, the SiO.sub.2 layer 5 is removed. Subsequently, AuGe--Ni is deposited. After patterning the AuGe--Ni layer, heat treatment is performed at a temperature of 400.degree. C. to form the source electrode 8 and the drain electrode 9 of ohmic contact.

In the shown embodiment, the gate electrode 7 forms Schottky junction with the GaAs layer 2 having wider band gap than the InGaAs layer 3, the gate leak voltage can be limited to be lower than that in the first prior art.

On the other hand, even in the shown embodiment, since the corner portion of the first recess 25, at which concentration of the stress and the electric field becomes highest, is formed of the InGaAs layer 3, degradation at the high temperature burn-in test can be prevented.

Since the second recess 26 is formed in a manner slightly cutting into the GaAs layer 2 for certainly form the gate electrode 7 above the GaAs layer 2, the corner portion of the second recess 26 is formed within the GaAs layer 2. Even at the corner portion of the second recess 26, there are certain magnitude of concentration of the stress. However, this portion is depleted by the voltage applied to the gate electrode, current may not flow therethrough. Accordingly, elevation of the temperature due to concentration of the current may not be caused. Therefore, degradation of the electrical characteristics will not create a problem.

FIG. 6 is a graph showing the result of high temperature burn-in test performed with respect to the shown embodiment of the field effect transistor. As shown in FIG. 6, when drain current is measured by forming a transistor having the gate length of 1 .mu.m and the gate width of 5 mm and by applying a drain voltage of 12 V with maintaining the temperature of 250.degree. C., it has been found that the drain current can be maintained at the initial value for a long period.

Although the invention has been illustrated and described with respect to exemplary embodiment thereof, it should be understood by those skilled in the art that the foregoing and various other changes, omissions and additions may be made therein and thereto, without departing from the spirit and scope of the present invention. Therefore, the present invention should not be understood as limited to the specific embodiment set out above but to include all possible embodiments which can be embodies within a scope encompassed and equivalents thereof with respect to the feature set out in the appended claims.