Frequency Doubler

The present invention relates to a frequency doubler which is capable of receiving four input signals in quadrature and combining them to produce a pair of antiphase output signals at twice the input frequency.

According to the present invention there is provided a frequency doubler circuit for receiving first to fourth input signals in quadrature and comprising: a first set of logic gates having inputs for receiving the input signals and providing outputs therefrom; and a second set of logic gates which have as their inputs only the outputs from the first set of logic gates and which supply as their outputs two signals in antiphase at twice the frequency of the input signals.

In the described embodiment the first set of logic gates comprises a first logic gate connected to receive the first and second input signals, a second logic gate connected to receive the second and third input signals, a third logic gate connected to receive the third and fourth input signals and a fourth logic gate connected to receive the first and fourth input signals, the signals supplied to each logic gate being 90.degree. apart in phase and having a duty cycle close to 50%. The second set of logic gates comprises a fifth logic gate connected to receive the outputs of the first and third logic gates and a sixth logic gate connected to receive the outputs of the second and fourth logic gate.

The logic gates are preferably NAND gates, but it is also possible to use NOR gates. However, the switching frequency of the logic gate will limit the maximum operating frequency of the circuit. NAND gates are preferred because they have faster switching speed than NOR gates.

The frequency doubler confers a particular advantage when used to double the frequency of quadrature outputs of a quadrature oscillator, which outputs are subject to buffering and conversion. It is usually difficult to make the oscillator, buffer and convertor operate fast enough but with the present frequency doubler they need operate only at a relatively low frequency. The frequency doubler is then the only circuit which is required to run at a high frequency. This is easier to achieve because it can be designed in high speed CMOS logic and could probably have the facility to be powered by a full supply voltage, whereas the oscillator may be restricted to operate at low supply voltages (of less than 3 V ). An oscillator with which the present invention has particular advantage is described in our copending Application entitled "Quadrature Oscillator," by Trevor Kenneth Monk and Andrew Mendlicott Hall having a PCT Application No. of PCT/GB 94/00892 and a filing date of Apr. 27, 1994, the contents of which are herein incorporated by reference.

For a better understanding of the present invention, and to show how the same may be carried into effect reference will now be made by way of example to the accompanying drawings.

FIG. 1 is a circuit diagram of a first embodiment of a frequency doubler;

FIG. 2 shows the waveforms of signals in the frequency doubler of FIG. 1;

FIG 3 is a circuit diagram of a second embodiment of a frequency doubler; and

FIG. 4 shows the waveforms of signals in the frequency doubler of FIG. 3.

FIG. 1 shows a frequency doubler connected to receive 4-phase quadrature signals .o slashed.1, .o slashed.2, .o slashed.3, .o slashed.4. The input signals .o slashed.1 to .o slashed.4 can come for example from CMOS-level convertors which are connected to the outputs of a quadrature oscillator. The input signals .o slashed.1 to .o slashed.4 are fed to a first layer of NAND gates 2,4,6,8. The first NAND gate 2 receives as its inputs .o slashed.1, .o slashed.2 which are 90.degree. apart. The second NAND gate 4 receives as its inputs the input signals .o slashed.2, .o slashed.3 which are 90.degree. apart. The third NAND gate 6 receives the input signals .o slashed.3, .o slashed.4 which are 90.degree. apart. The fourth NAND gate 8 receives input signals .o slashed.1, .o slashed.4 which are 90.degree. apart. The timing of the input signals is shown in the top two diagrams of FIG. 2 labelled .o slashed.1 to .o slashed.4 respectively. A second layer of NAND gates comprises fifth and sixth NAND gates 10,12. The fifth NAND gate 10 has as its inputs outputs from the first and third NAND gates 2,6. The sixth NAND gate 12 has as its inputs outputs from the second and fourth NAND gates 4,8. The first layer of NAND gates 2 to 8 combine the inputs .o slashed.1 to .o slashed.4 to produce four new signals S1 to S4 which go low in turn for 25% of the period. This is shown in the next two diagrams in FIG. 2. The waveforms for S1 and S3 are shown in FIG. 2 but it will be appreciated that S2 and S4 have equivalent waveforms at different parts of the cycle.

The second layer of NAND gates 10, 12 combine the signals S1 to S4 to produce a pair of output signals Out1, Out2 which alternate high and low twice in every period of the input signals. Thus, the output is toggling at twice the frequency of the input. This is shown in the last diagram of FIG. 2.

For minimum distortion of mark/space ratio, the NAND gates 10,12 of the second layer are best implemented as symmetrical designs, that is the delay from input to output is identical for each input.

A feature of this circuit is that no feedback is required between the layers of NAND gates. Thus, the second layer has as its inputs only inputs from the first layer and the first layer has as its inputs only the 4-phase input signals. There is no feedback from the first layer to the input or from the second layer to the first layer. FIG. 3 is a schematic diagram of a second embodiment of a frequency doubler. In this second embodiment, the NAND gates of FIG. 1 are replaced with NOR gates.

In operation, a first set of NOR gates 14, 16, 18, and 20 receive the inputs .o slashed.1, .o slashed.2, .o slashed.3, and .o slashed.4, and respectively generate the signals S5, S6, S7, and S8. A second set of NOR gates 22 and 24 respectively receive the signals S5 and S6, and S7 and S8, and generate the output signals Out3 and Out4.

For minimum distortion of mark/space ratio, the NOR gates 22 and 24 of the second stage can be made to have identical or nearly identical delays from their respective inputs to their respective outputs.

Furthermore, like the frequency doubler of FIG. 1, a feature of the frequency doubler of FIG. 3 is that no feedback is required between the two stages of NOR gates.

FIG. 4 is a diagram showing the signals of FIG. 3 and their approximate timing relative to one another. As shown, the output signals Out3 and Out4 oscillate at a frequency that is twice that of the frequency of the input signals .o slashed.1-.o slashed.4.

From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.