Semiconductor Integrated Circuit With a Test Circuit for Input Buffer Threshold

1. A digital semiconductor integrated circuit of the CMOS transistor structure having a plurality of input buffers, comprising: a first logic gate provided for each of said input buffers, for outputting an output logic value determined by an output logic value of a corresponding input buffer, and a second logic gate for designating a logic value to be outputted from said first logic gate, in accordance with an output logic determined by an external control signal, an output node of said first and second logic gates being interconnected to the same signal line, so that when at least one of said plurality of input buffers outputs a logic signal different from a logic signal expected in response to an input signal applied from an external source and in accordance with said external control signal, the output logic values of said first and second logic gates become different from each other, whereby a signal collision occurs on said signal line, resulting in an increased power supply current.

2. A semiconductor integrated circuit claimed in claim 1 wherein said first logic gate is any one of a tristate buffer, a transfer gate, a clocked inverter, a NAND gate, a NOR gate, an AND gate and an OR gate.

3. A digital semiconductor integrated circuit of the CMOS transistor structure having a plurality of input buffers each receiving an external input signal to transfer the received signal to an internal circuit, comprising: a first logic gate provided for each of said input buffers, for outputting an output logic value determined by an output logic value of a corresponding input buffer, and a second logic gate for generating an output logic value determined in accordance with an external control signal, an output node of said first and second logic gates being interconnected to a common signal line, so that when said first logic gate outputs a logic signal different from a logic signal outputted from said second logic gate determined in accordance with said external control signal, so that said output logic values of said first and second logic gates collide with each other on said common signal line, whereby a power supply current of the integrated circuit increases constantly, and activation/deactivation of the output of said first logic gates being controlled in bundle by a common control signal, wherein the same potential DC input signal is simultaneously applied to said plurality of input buffers, and said first logic gates are both put into an output activated condition, so that whether or not all of said input buffers output the logic level signal previously expected from said external control signal, is converted into a binary value on the basis of whether or not said power supply current increases constantly, thereby to enable discrimination of whether or not the input threshold voltage of all said input buffers exceeds the value determined by the potential of said potential DC input signal.

4. A digital semiconductor integrated circuit of the CMOS transistor structure having a plurality of input buffers, comprising: a precharge circuit for previously charging or discharging a potential monitor signal line in accordance with an external control signal, and switches each on-off controlled by a logic value of an output signal of a corresponding input buffer, for discharging or charging said potential monitor signal line, so that whether or not said input buffer generates an output signal of a logic value expected on the basis of an external input signal given to the input buffer, is determined on the basis of whether said logic value flips on the previously charged or discharged potential monitor signal line, and occurrence/non-occurrence of the flip of the logic value is converted into a binary value, which is in turn outputted to the external output terminal.

5. A digital semiconductor integrated circuit of the CMOS transistor structure having a plurality of input buffers each receiving an external input signal to transfer the received signal to an internal circuit, comprising: a monitor signal line the potential on which can be taken out to an external output terminal; a precharge circuit for previously charging or discharging said monitor signal line in accordance with an external control signal for a predetermined period of time; analog switches connected to said monitor signal line, each of said analog switches being provided for a corresponding one of said plurality of input buffers, so as to on-off control a current path between said monitor signal line and a fixed potential point in accordance with the logic value of the output signal of said corresponding input buffer, so that when at least one of said analog switches is turned on, a current of the charging or discharging of said monitor signal line by said precharging circuit flows into said fixed potential point, whereby after the charging or discharging of said predetermined period of time, the logic value of said monitor signal line when all said analog switches are off, is opposite to the logic value of said monitor signal line when at least one of said analog switches is on; and switch control circuits each provided between each of said input buffers and a corresponding one of said analog switches, for controlling a control terminal of said corresponding analog switch in accordance with the output signal of the corresponding input buffer, the activation and deactivation of the output of said switch control circuits being controlled in bundle by a common signal; wherein the same level DC input signal is simultaneously applied to said plurality of input buffers, and said switch control circuits are put in bundle into an output activated condition, so that it is possible to discriminate whether or not the input threshold voltage of all said input buffers exceeds the value determined by the potential of said potential DC input signal, by converting whether or not all of said input buffers output the logic level signal previously expected from said DC input signal, is converted into a binary value indicative of whether or not the logic value of said monitor signal line flips.

6. A semiconductor integrated circuit claimed in claim 5 further including means for holding, on said monitor signal line, the discrimination data determined by the signal logic value appearing on said monitor signal line.

7. A semiconductor integrated circuit of the CMOS transistor structure comprising: a plurality of input circuits each including an input buffer receiving an external input signal to transfer the received input signal to an internal circuit, a first two-input NOR gate having one input receiving an output signal of said input buffer, a first MOS transistor of the n-channel type having its gate receiving an output of said first NOR gate, its source connected to ground, and its drain connected to a monitor signal line, a second two-input NOR gate having one input receiving an inverted signal of said output signal of said input buffer, a second MOS transistor of the n-channel type having its gate receiving an output of said second NOR gate, its source connected to said ground, and its drain connected to said monitor signal line; a precharge circuit including a first two-input NAND gate having its one input receiving a first control signal from an external and its other input receiving a delay signal of an inverted signal of said first control signal, and a third MOS transistor of the p-channel type having its gate receiving an output of said first NAND gate, its source connected to a high voltage line and its drain connected to said monitor signal line; an output buffer for amplifying a signal appearing on said monitor signal line to output the amplified signal to an external; a data hold circuit composed of a first inverter having an input connected to said monitor signal line and a second inverter having an output connected to said monitor signal line and an input connected to an output of said first inverter; and a control circuit including a second two-input NAND gate receiving said first control signal and a second control signal supplied from an external source, and a third two-input NAND gate receiving an inverted signal of said second control signal and said first control signal, an output signal of said second NAND gate being supplied to the other input of said first NOR gate of each input circuit, and an output signal of said third NAND gate being supplied to the other input of said second NOR gate of each input circuit, and an output signal of said output buffer being outputted to the external.

8. A semiconductor integrated circuit of the CMOS transistor structure comprising: a plurality of input circuits each including an input buffer receiving an external input signal to transfer the received input signal to an internal circuit, a selector selecting either an output signal of said input buffer or an inverted signal of said output signal in accordance with a logic level of a given selection signal, a two-input NAND gate receiving an output signal of said selector and a first control signal supplied from an external, and a first MOS transistor of the p-channel type having its gate receiving an output of said NAND gate, its source connected to a high voltage line, and its drain connected to a monitor signal line; a precharge circuit including a two-input NOR gate receiving an inverted signal and a non-inverted delayed signal of said first control signal, and a second MOS transistor of the n-channel type having its gate receiving an output of said NOR gate, its source connected to a ground line and its drain connected to said monitor signal line; an inverting output buffer for amplifying and inverting a signal appearing on said monitor signal line to output the amplified and inverted signal to an external output terminal; a data hold circuit composed of a third MOS transistor of the p-channel connected to form a current path between said monitor signal line and said high voltage line, and having its gate connected to receive an output signal of said inverting output buffer; a control circuit composed of a two-input AND gate receiving said first control signal and a second control signal applied from the external source; an output of said AND gate of said control circuit being supplied to said selector as said selection signal, and an output signal of said output buffer being outputted to the external.