Communication Protocol Between Master and Slave Device With Register Information Sharing

This invention relates in general to communication between semiconductor devices, and more specifically to a method and apparatus for full duplex communication between a master device and a slave device

Electronic devices, such as pagers, often incorporate communication between different semiconductor devices. In many electronic devices, the communication between semiconductor components involves data transference between a master device, e.g., a microprocessor, and a slave device, e.g., a support chip.

In conventional pagers, the slave device is capable of generating an external signal received by the master device which can cause an interrupt. Because the interrupt can be generated by many sources, rapid determination of a highest priority interrupt must be made by the master device. Under some circumstances, the determination of the highest priority interrupt may not be rapid enough to meet the needs of a system. Such a circumstance could arise, for example, when the slave device in a pager detects that a battery providing primary power has been removed from the pager, i.e., when the interrupt source is a "gone cell" interrupt. Subsequent to receiving the interrupt and ending communication, the master device normally shuts down the sections of the pager that draw high current, e.g., the receiver circuitry, and switches the power from the main battery to a backup battery. If too much time passes before the power is switched to the backup battery, the supply voltage could become low enough so that the memory of the pager is lost. This critical event would result in the loss of any messages that have been received by the pager.

Thus, what is needed is a more rapid method of data transference between the slave device and the master device.

According to a first aspect of this invention, a method for data transference between a master device and a slave device comprises the steps of the master device providing a communication initiation signal to the slave device, the master device providing a signal to the slave device, the slave device, substantially coincident with the master device providing the signal, providing an information signal to the master device.

According to a second aspect of this invention, an electronic device having full duplex data transference between semiconductor devices, comprises a master device and a slave device. The slave device comprises registers for storing information and a controller for receiving information signals and updating the information in response to the information signals. The master device is coupled to the slave device by an interface in such a manner that provides for full duplex communication between the master device and the slave device. The interface comprises a first line for providing a communication initiation signal to the slave device from the master device. Thereafter, a second line provides the updated information to the master device from the slave device simultaneously with a third line providing a signal to the slave device from the master device.

FIG. 1 is a diagram of a conventional communication interface between a master semiconductor device and a slave semiconductor device.

FIG. 2 is a flowchart illustrating a conventional method of data transference between the semiconductor devices of FIG. 1.

FIG. 3 is a timing diagram for the conventional method of data transference of FIG. 2.

FIG. 4 is a block diagram of a selective call receiver in accordance with a preferred embodiment of the present invention.

FIG. 5 is a flowchart illustrating a method of data transference in accordance with a preferred embodiment of the present invention.

FIG. 6 is a timing diagram of the method of data transference of FIG. 5 in accordance with a preferred embodiment of the present invention.

A conventional interface between a master device and a slave device in an electronic device, such as a pager, is illustrated in FIG. 1. The master device 101 is coupled to the slave device 102 via a serial peripheral interface (SPI) 103 for data transference. The SPI 103 comprises four lines connected between the master device 101 and the slave device 102. The four lines include a slave select line (SS) 104 controlled by the master device 101 to initiate communication with the slave device 102, a master out slave in (MOSI) line 105 for transferring data from the master device 101 to the slave device 102, a master in slave out (MISO) line 106 for transferring data from the slave device 102 to the master device 101, and a serial clock line (SCK) 107 which is active during address and data transfers. The serial clock is used to synchronize the movement of data both into and out of the master device on the MISO line 106 and the MOSI line 105. Four possible timing relationships between the SCK line 107 and the transferred data. The timing relationship is controlled by bits located in a serial peripheral control register (SPCR) internal to the master device 101.

In conventional pagers, the slave device 102 generates an interrupt signal received by the master device 101 which causes an interrupt. The interrupt signal is generated by the slave device 102 in response to an interrupt event. Interrupt events are, by way of example, a battery voltage that has fallen below a predetermined level or a modulo timer which signals a timeout to the slave device 102. When an interrupt event occurs, the slave device 102 pulls an interrupt line 108, coupled to the master device 101, low.

FIG. 2 is a flowchart illustrating a conventional method of full duplex data transference between the master device 101 and the slave device 102. Full duplex data transference can occur in such a manner that the falling edge of every clock cycle of the SCK line 107 causes a bit to be transferred simultaneously from the master device 101 on the MOSI line 105 and from the slave device 102 on the MISO line 106. When an interrupt event occurs 201, the slave device 102 updates 202 internal register information and pulls the interrupt line 108 (FIG. 1) low 203 to inform the master device 101 that data is ready to be transferred. The master device 101 initiates communication by taking the SS line 104 low 204. The master device 101 then sends 205 a request for information, i.e., a byte containing the address of an interrupt status register contained in the slave device 102. Simultaneously, in accordance with the full duplex communication mode, the slave device 102 sends 206 an wasted byte, which contains no useful information, over the MISO line 106. Subsequent to receiving the address of the interrupt status register from the master device 101, the slave device 102 sends 207 the information contained in the interrupt status register, while the master device 101 simultaneously sends 208 a wasted byte over the MOSI line 105. The slave device 102 then takes 209 the interrupt line 108 high. Thereupon, the master device 101 may take 210 the SS line 104 high, ending communication with the slave device 102. The master device 101 thereafter proceeds to act 211 upon the data received. For example, if a modulo timer times out, creating an interrupt, the master device 101 resets the timer in response to the data that has been transferred from the slave device 102 to the master device 101. Thus, the full duplex communication mode, while providing more rapid intercommunication between the slave device 102 and the master device 101, regrettably requires the transference of useless wasted bytes 206 and 208 in conventional interrupt communication.

The conventional interrupt communication process is also depicted in FIG. 3, wherein a timing diagram illustrates full duplex data transference via the SPI 103. Subsequent to the master device 101 taking the SS line 104 low 204, the SCK line 107 clock begins to cycle. At the first falling edge 302 of the clock cycle, the master device 101 may send 205 the request for information, i.e., the address of the interrupt status register, on the MOSI line 105. Because the slave device 102 has not yet received the request from the master device 101, the slave device 102 sends 206 a wasted byte on the MISO line 106. This data is cleared on the eighth falling edge 304 of the SCK line 107 clock cycle, and another full duplex data transfer is begun, wherein the master device 101 sends 208 an empty byte on the MOSI line 105 while the slave device 102 sends 207 the information contained in the addressed interrupt status register on the MISO line 106. Thereafter, the slave device 102 takes 209 the interrupt line 108 high, and the master device 101 may take 210 the SS line 104 high, ending communication with the slave device 102.

Referring next to FIG. 4, a selective call receiver 400, such as a pager, comprises an antenna 401 that receives a radio frequency (RF) modulated selective call signal and provides the signal to receiver circuitry 402 for demodulation thereby. A microprocessor 403 processes the demodulated signal to decode an address and optional message data contained therein. The recovered message may be stored in a memory 412 for subsequent presentation by an output device 414, such as a liquid crystal display or an audio transducer. In operation, the microprocessor 403 compares a decoded address contained in the signal with predetermined addresses. The user is alerted by an alert mechanism 416 that a message has been received if the decoded address correlates with one of the predetermined addresses. If the signal contains optional message data, the output device 414 will present the message automatically or when manually selected by user actuated controls 418.

Support circuitry 419 coupled to the receiver circuitry 402, the microprocessor 403, a battery 404 and the user actuated controls 418 provides supporting circuitry for operation of the selective call receiver 400. In accordance with the present invention, the support circuitry 419 and the microprocessor 403 have the relationship of a slave device and a master device (see FIG. 1) and are coupled by a serial peripheral interface (SPI) 420. A controller 422 internal to the support circuitry 419 receives signals from both internal interrupt sources and external interrupt sources, such as the battery 404 and the user actuated controls 418.

The internal interrupt sources are, for example, modulo timers 406 which count down from a predetermined number, clock recovery determination circuitry 408 which detects the baud rate of the RF modulated selective call signal, and a bit synchronizer 410 which maintains synchronization to the demodulated signal. Upon reception of a signal from an interrupt source, the controller 422 pulls an interrupt line 424 low to initiate communication with the microprocessor 403. The battery 404 could provide interrupt sources such as "low power" when the battery power is depleted below a minimum threshold or "gone cell" when the battery cell is removed from the selective call receiver 400. The user actuated controls 418 could comprise one or more user actuated buttons, and an interrupt source would be provided from the activation of each of the buttons.

Information about the various interrupt sources, both internal and external, is contained in a plurality of interrupt status registers 421 internal to the support circuitry 419 and coupled to the controller 422, which updates the information in response to signals received from the interrupt sources.

Referring to FIG. 5, when an interrupt event occurs 201, the support circuitry 419 updates 202 the information contained in the interrupt status registers 421. The support circuitry 419 pulls the interrupt line 424 low 203 to inform the microprocessor 403, acting as a master device, that data is ready to be transferred. The microprocessor then initiates communication by taking the SS line of the SPI 420 low 204.

Conventionally, as seen in FIG. 2, the master device, after initiating communication, requests specific interrupt information by sending 205 the address of a particular status register to the slave device. In accordance with the present invention, however, the microprocessor 403 sends 501 an empty byte, i.e., one that contains no useful information, to the support circuitry 419 at the first falling edge of the SCK line of the SPI 420 clock cycle. Rather than waiting for the master device to identify 205 (FIG. 2) the address of the particular interrupt status register, the support circuitry 419 automatically sends 502 a first byte of data, hereafter referred to as a global status register, over the MISO line of the SPI 420 at the first falling edge of the SCK line clock cycle. The global status register comprises selected information from the interrupt status registers 421 about all of the various interrupt sources and can be sent by the slave device whether the SPI 420 is in a read or a write mode. Conventionally, the slave device could only send data to the master device if the SPI 420 was in a read mode.

Subsequent to receiving the global status register information, the microprocessor 403 takes the SS line of the SPI 420 high 503, ending communication with the support circuitry 419. The microprocessor 403 then proceeds to act 504 upon the information received. As can be seen by referring back to prior art FIG. 2, steps 205, 206, and 207 of the prior art have been removed from the communication process of the present invention. The master device is advantageously able to respond to information received from the slave device more quickly because the slave device immediately sends 502 the interrupt information contained in the global status register to the master device rather than waiting for a request for information from the master device. The master device receives the interrupt information on which to act from within the global status register information.

Referring to FIG. 6, a timing diagram illustrates the process of communication in the preferred embodiment of the present invention. After the microprocessor 403 takes 204 the SS line of the SPI 420 low, data transference begins on the first falling edge 602 of the SCK line clock cycle. The microprocessor 403 then sends 501 an empty byte on the MOSI line of the SPI 420, while the support circuitry 419 sends 502 the interrupt information in the form of the global status register on the MISO line of the SPI 420. Communication could be ended after only eight cycles, rather than the conventional sixteen cycles, of the clock because, during the first eight clock cycles, the support circuitry 419 sends 502 the interrupt information contained in the global status register to the microprocessor 403. Prior art FIG. 3 illustrates a conventional communication process requiring sixteen clock cycles wherein conventional data transference of interrupt information requires twice the time of that required in accordance with the present invention.

The use of the global status register allows selected information about all of the various interrupt sources to be transferred in the first byte of data, which is normally not used to transfer any useful information. When an interrupt source instructs the slave device to generate an interrupt signal, in accordance with the present invention, a master device receives the information in the first byte of data, thereby eliminating the need for provision of an additional second byte to complete the data transference. In the case of a critical event, e.g., loss of power from the main battery, the master device would be able to respond more rapidly to correct any problems indicated by interrupt information communicated by the slave device.

By now it should be appreciated that there has been provided a more rapid method of data transference between a master device and a slave device.