System for Inexpensive Phase Coherent Subcarrier Generation

The present invention relates generally to television signal encoding, and more particularly to the generation of a phase coherent National Television Standards Committee (NTSC) subcarrier.

Specialized combinations of computer hardware and software, such as QuickTime.RTM. by Apple Computer, Inc., allow users to create and edit video movies using a combination of video, graphics, and sound data. Each frame of a movie exists in a digitized baseband (usually red, green, and blue, or RGB) component format, which allows the images to be stored and manipulated by a computer. While the digitized baseband format is ideal for creating and editing movie frames on a computer, this format is not compatible with interlaced television systems or video cassette recorders (VCRs), which require a composite television signal (such as NTSC) as an input.

As is well known to those skilled in the art, the RGB component format can be easily transformed to a basis suitable for NTSC television signal encoding. NTSC composite television signals are generated by combining a baseband luminance (Y) component with two QAM encoded chrominance components (I and Q). Quadrature amplitude modulation encoding, or QAM, is the suppressed carrier amplitude modulation of two subcarriers in quadrature. That is, the baseband I signal is used to modulate an analog sinusoidal subcarrier f.sub.sc, and the baseband Q signal is used to modulate a 90.degree. phase shifted version of f.sub.sc. In the NTSC standard, f.sub.sc is defined to be a 3.579545 MHz (.+-.1 Hz) sinusoidal signal. This, and other signal parameters of the NTSC standard can be found in "Report 624-4, Characteristics of Television Systems," Reports of the CCIR, 1990.

Currently, there are several ways to generate the sinusoidal subcarrier required for QAM encoding of the chrominance components. In the simplest, least accurate systems, f.sub.sc can be generated with an oscillator unlocked to the scan or sample rates of the system. This can lead to difficulties in maintaining the phase coherency of the subcarrier. Other, more complex systems incorporate phase locked loop circuitry to more accurately generate a phase coherent subcarrier. In yet another approach, a digital frequency synthesizer is used to generate a sequence of samples that may be used to derive f.sub.sc.

While each of these systems works for its intended purpose, the systems capable of generating a highly accurate phase coherent subcarrier are expensive, and can be difficult to implement in a system where the subcarrier frequency is not conveniently related to the video sampling rate or one of its harmonics. For example, the duration of a horizontal scan line is defined to be (in the NTSC standard) 63.5555 .mu.sec, 10.7 .mu.sec of which is used for horizontal blanking. Thus, 52.8555 .mu.sec per scan line contains picture information. In a system having 640 pixels per scan line, each pixel is presented for (52.8555 .mu.sec per line/640 pixels per line)=82.586717 nsec per pixel. This implies that a sample rate of (1/82.586717 nsec)=12.108484 MHz must be used to accurately sample each pixel.

As can be shown with simple division, the relationship between this sample rate and f.sub.sc is not a simple one: (12.108484 MHz/3.579545 MHz)=3.382688. Thus, deriving f.sub.sc by using the horizontal sampling frequency as a reference is not practical.

Accordingly, an object of the present invention is to simply and efficiently generate a phase coherent NTSC subcarrier by using commonly available digital video processing signals as a reference, when such signals do not have a simple relationship to the NTSC subcarrier frequency.

Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part become apparent to those skilled in the art upon examination of the following, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the claims.

The present invention includes a system for inexpensive phase coherent generation of a periodic signal. Such a system includes a binary counter, a lookup table, a parallel to serial converter, and a bandpass filter. An output from the binary counter is used to address the lookup table, which then generates a digital output signal representative of a periodic signal. The digital output of the lookup table is converted to a serial digital signal by the parallel to serial converter, and then the serial digital signal is filtered to reconstruct the continuous signal.

The accompanying drawing, which is incorporated in and constitutes a part of the specification, schematically illustrates a preferred embodiment of the invention and, together with the general description given above and the detailed description of the preferred embodiment given below, serves to explain the principles of the invention.

FIG. 1 is a block diagram of a system for phase coherent NTSC subcarrier generation according to the present invention.

The present invention will be described in terms of the preferred embodiment, which is a system for inexpensive phase coherent NTSC subcarrier generation (PCSG). Such a system is shown in FIG. 1, where the PCSG is referred to by general reference numeral 20.

In the NTSC standard (and distinct from other composite television standards), the subcarrier frequency f.sub.sc is defined to be 227.5 times the horizontal line frequency. This implies that a uniform sampling of the subcarrier will generate a sequence that repeats every two lines. It is this relationship between the horizontal line frequency and f.sub.sc that allows PCSG 20 to economically generate a phase coherent NTSC subcarrier.

Referring now to the drawing, FIG. 1 shows a block diagram of PCSG 20 according to the present invention. PCSG 20 may be incorporated in a video processing system (not shown) which generates the baseband YIQ (or RGB) signals to be encoded. PCSG 20 includes a binary counter 22, a lookup table 24, a parallel to serial converter 26, a band pass filter 28, and a control logic circuit 30.

In a preferred embodiment, counter 22 is clocked (by clock signal 32) at 2.25 MHz, which is a frequency commonly used in the art to sample digital video signals. Binary counter 22 generates as its output a parallel output signal 34, which increases with every cycle of clock signal 32. Binary counter 22 is reset every two horizontal lines, which is every (2.times.63.5555 .mu.sec)=127.111 .mu.sec. This implies that parallel output signal 34 must be able to represent at least ((2.25.times.10.sup.6 cycles/second).times.(127.111.times.10.sup.-6 seconds))=286 cycles of clock signal 32. Therefore, parallel output signal 34 must be at least 9 bits wide in the preferred embodiment, although parallel output signal 34 may have more or fewer bits depending on the frequency of clock signal 32, and the frequency with which binary counter 22 is reset.

Parallel output signal 34 is used to address lookup table 24, which contains a series of coded values that precisely represent the sinusoidal subcarrier f.sub.sc, preferably sampled at the rate of 8 times the clock signal 32 (here, 2.25 MHz) at one bit resolution and then grouped into 8 bit samples. Because the frequency of clock signal 32 may be less than the frequency of f.sub.sc, parallel output signal 36 generated by lookup table 24 may represent more than one cycle of f.sub.sc. In a preferred embodiment, parallel output signal 36 is 8 bits wide, although more or fewer bits may be used.

Control logic circuit 30 receives information about the status of binary counter 22 via status signal 37. Status signal 37 may include information such as the value of parallel digital output signal 34. Control logic circuit 30 may also review information about the status of an external video processing system (not shown) via status signal 39.

Control logic 30 generates a reset signal 38 used to reset counter 22 after the end of each two line sequence. Preferably, counter 22 is also reset at the start of the first line of each odd field to maintain correct synchronization between f.sub.sc and the external video processing system. Counter 22 may also be reset as needed throughout the NTSC four field color frame to maintain SubCarrier-Horizontal (SCH) phase. In applications where the SCH phase must be varied, the contents of lookup table 24 may simply be offset by a predetermined amount to represent a constant phase shift. SCH phase, and other details of the NTSC standard are well known to those skilled in the art, and will not be discussed further to avoid obscuring the present invention.

Lookup table 24 may contain data that represents the sampled subcarrier sine wave in a number of different but equivalent ways. The most straightforward representation is that of linear pulse code modulation (PCM). However, since PCM requires a digital-to-analog converter (not shown), it is not the most cost effective implementation. Also, PCM cannot be implemented if the frequency of clock signal 32 is less than two times f.sub.sc.

In a preferred embodiment, f.sub.sc is represented as a sequence of binary values, most easily chosen as +1 when sin(2.pi.f.sub.sc t) is greater than zero, and as 0 when sin(2.pi.f.sub.sc t) is less than or equal to zero. This technique will be referred to as "sign bit" modulation. Delta modulation and delta-sigma modulation are also possible.

The 8-bit parallel output 36 of lookup table 24 is used as an input by parallel-to-serial converter 26. In a preferred embodiment, parallel-to-serial converter 26 is a shift register. Parallel-to-serial converter 26 converts the 8-bit parallel signal 36 into a 1-bit serial output signal 40. Since the 8-bit parallel signal 36 is preferably sampled at 2.25 MHz, parallel-to-serial converter 26 must generate serial output 40 at a rate of (8.times.2.25 MHz)=18 MHz. Clock signal 42 is used to provide parallel-to-serial converter 26 with an 18 MHz reference. In an alternative embodiment, lookup table 24 may itself generate the serial output signal 40, eliminating the need for parallel to serial converter 26; however, lookup table 24 must operate at 8 times the speed required in the preferred embodiment.

Serial output signal 40 is a digital signal that alternates between 1 (logic high) and 0 (logic low). Since signal 40 is sampled at 18 MHz, and f.sub.sc is 3.579545 MHz, signal 40 is an alternating series of 2 or 3 logic high samples, followed by a series of 2 or 3 logic low samples. This results in what is essentially a square wave, with the logic high and logic low portions separated by a predetermined voltage or range of voltages.

Next, serial output 40 is filtered by band pass filter 28, which generates as its output 44 a sinusoidal subcarrier f.sub.sc having a frequency of approximately 3.579545 MHz, and reasonably good spectral purity. The requirements of filter 28 are fairly modest, and can be met easily with a single parallel resonant inductor-capacitor (LC) circuit.

It will be apparent to those skilled in the art that the frequencies of clock signals 32 and 42 may be changed, depending on the type and frequency of external signals available to PCSG 20. It will also be apparent that the frequency of clock signal 42 must equal the frequency of clock signal 32 times the number of bits in output signal 36.

If the frequency of clock signal 32 is high enough, other well known binary encoding schemes, such as pulse width modulation, delta modulation, or delta-sigma modulation may be used to encode the representation of f.sub.sc stored in lookup table 24. These other schemes may be used to suppress outband components (i.e., harmonics) which may occur with the simple "sign bit" modulation technique described above.

The present invention has been described in terms of a preferred embodiment. The invention, however, is not limited to the embodiment depicted and described. Rather, the scope of the invention is defined by the appended claims.