Non-Arithmetical Circular Buffer Cell Availability Status Indicator Circuit

The present invention relates to status indicator circuits for use with circut buffer and, in particular, to a status indicator circuit that indicates which cells of a circular buffer are available for access, without the need for complicated arithmetic logic.

Circular buffers are well known in the art. An example of a ten-cell circular buffer 10 (i.e., an N-cell circular buffer, where N is equal to 10) is shown in FIG. 1. Circular buffer 10 has ten circular buffer cells (CBC.sub.x, for x=0 through 9). Circular buffers such as circular buffer 10 are typically accessed sequentially. For example, CBC.sub.9 is accessed after CBC.sub.8. After the last circular buffer cell is accessed, a "wrap-around" occurs such that the next circular buffer cell to be accessed is the first circular buffer cell. That is, referring to circular buffer 10, CBC.sub.0 is accessed after CBC.sub.9 is accessed. Thus, for a circular buffer cell of arbitrary length N, each circular buffer cell, CBC.sub.x is accessed after CBC.sub.((x-1)+N) REM N, where "REM" is a function that yields, in a division operation, the number that is the undivided part of the dividend (i.e., the remainder).

Circular buffers are of particular utility in data communications devices. For example, in a data receiver, received data would typically be inserted sequentially into a circular buffer. Once data is inserted into a particular cell of the circular buffer, this cell becomes unavailable for access until the received data is processed. At that point, this cell again becomes available for access.

The circular buffer 10, of FIG. 1, has a ten-cell availability status circuit 20, associated with it. Each status cell of ten-cell availability status circuit 20 (CAS.sub.x, for x=0 through 9) corresponds to one of the circular buffer cells (CBC.sub.x, for x=0 through 9, respectively). The state of a particular status cell, CAS.sub.x, of the availability status circuit 20 indicates whether the corresponding circular buffer cell, CBC.sub.x, is available for access.

As shown in FIG. 1, the states of the status cells, CAS.sub.x, of the cell availability status circuit 20 are determined by CAS determination logic 30. The CAS determination logic 30 responds to an available address indicator signal, AV.sub.-- ADD, that indicates which of the circular buffer cells is the first circular buffer cell available for access; and to an unavailable address indicator signal, UNAV.sub.-- ADD, that indicates which of the circular buffer cells is the first circular buffer cell unavailable for access. For example, if AV.sub.-- ADD indicates that CBC.sub.2 is the first circular buffer cell available for access, and if UNAV.sub.-- ADD indicates that CBC.sub.5 is the first circular buffer cell unavailable for access, then CAS determination logic 30 sets cell availability status circuits CAS.sub.2, CAS.sub.3, and CAS.sub.4 to indicate that corresponding circular buffer cells CBC.sub.2, CBC.sub.3, and CBC.sub.4 are available for access. Likewise, CAS determination logic 30 sets cell availability status circuits CAS.sub.0, CAS.sub.1, CAS.sub.5, CAS.sub.6, CAS.sub.7, CAS.sub.8, and CAS.sub.9 to indicate that corresponding circular buffer cells CBC.sub.0, CBC.sub.1, CBC.sub.5, CBC.sub.6, CBC.sub.7, CBC.sub.8, and CBC.sub.9 are not available for access.

Conventional CAS determination logic circuits employ arithmetic circuitry to determine how to set the availability status circuits. However, such arithmetic circuitry is complicated. In particular, since circular buffers "wrap-around", the arithmetic circuitry of conventional CAS determination logic circuits must perform complicated modular arithmetic.

Therefore, what is desired is an availability status indicator circuit with CAS determination logic circuitry that can determine, without complex arithmetic circuitry or high-overhead masking logic, how to set availability status circuits.

The present invention is an availability status indicator circuit for simultaneously indicating which of N circular buffer cells (CBC.sub.x, for x=0 through N-1) are available for access.

N cell status circuits are provided that correspond to the separate circular buffer cells. Each cell status circuit includes an output terminal at which a cell availability status signal is provided to indicate the availability status of the corresponding circular buffer cell. A first input terminal of the cell status circuit is connected to receive the cell availability status signal from the previous cell status circuit.

The cell availability status signal is generated in response to the cell availability status signal of the previous cell, to an available address indicator signal that indicates whether the corresponding circular buffer cell is a first circular buffer cell available to be accessed, and to an unavailable address indicator signal that indicates whether the corresponding circular buffer cell is a last circular buffer cell available to be accessed. The cell availability status signal has a first state if the corresponding circular buffer cell is available for access and has a second state if the corresponding circular buffer cell is not available for access.

A better understanding of the features and advantages of the invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized.

FIG. 1 schematically illustrates a circular buffer circuit and an associated cell availability status circuit, with cell availability status determination logic for setting the cell availability status circuit.

FIG. 2 is a block diagram showing a cell determination logic circuit in accordance with the present invention.

FIG. 3 schematically illustrates a first embodiment, in accordance with the present invention, of a cell status circuit of the cell determination logic circuit of FIG. 2.

FIG. 4 schematically illustrates a second embodiment, in accordance with the present invention, of a cell status circuit of the cell determination logic circuit of FIG. 2.

FIG. 5 schematically illustrates a third embodiment, in accordance with the present invention, of a cell status circuit of the cell determination logic circuit of FIG. 2.

FIG. 2 is a block diagram showing a cell determination logic circuit 130 in accordance with the present invention. For simplicity of illustration, the cell determination logic circuit 130 shown in FIG. 2 indicates the availability of the cells of a four cell circular buffer (i.e., N equals 4).

Reffering to FIG. 2, a first decoder (AV.sub.-- DECODE) 132 receives a two bit start address signal (AV.sub.-- ADD [0.1] that indicates which of the N corresponding circular buffer cells is the first circular buffer cell available for access. For example, if circular buffer cell 1 is the first circular buffer cell available for access, then AV.sub.-- .sub.-- ADD has the value of 01 h. First decoder (AV.sub.-- DECODE) 132 operates in a conventional manner. That is, first decoder (AV.sub.-- DECODE) 132 asserts one of its output bits, AV.sub.-- ADD.sub.-- DEC [0.3], in response to the available address signal, AV.sub.-- ADD. The separate output bits of the first decoder (AV.sub.-- DECODE) 132 output, AV.sub.-- ADD.sub.-- DEC, are provided to separate corresponding cell status circuits, CSC.sub.x (for x=0 through 3, respectfully).

It is the cell status circuits, CSC.sub.x which generate the cell availability status signals, CAS.sub.x. Each cell status circuit, CSC.sub.x provides the corresponding cell availability status signal, CAS.sub.x, at its output.

Similar to the first decoder (AV.sub.-- DECODE) 132 a second decoder (UNAV.sub.-- DECODE) 134 receives a two bit end address signal (UNAV.sub.-- ADD [0..1]) that indicates which of the N corresponding circular buffer cells is the first circular buffer cell unavailable for access. For example, if circular buffer cell 3 is the first circular buffer cell unavailable for access, then UNAV.sub.-- ADD has the value of 03h. Second decoder (UNAV.sub.-- DECODE) 134 operates in a conventional manner. That is, second decoder (UNAV.sub.-- .sub.-- DECODE) 134 asserts one of its outputs, UNAV.sub.-- ADD.sub.-- DEC.sub.x, in response to the unavailable address signal, UNAV.sub.-- ADD. The separate bits of the second decoder (UNAV.sub.-- DECODE) 134 output, UNAV.sub.-- ADD.sub.-- DEC, are provided to the separate corresponding cell status circuits, CSC.sub.x.

As is discussed below with reference to the several described embodiments of the invention (FIGS. 3-5), it is an important feature of the present invention that each cell status circuit, CSC.sub.x, is additionally connected to receive the cell availability status signal generated by the "previous" cell status circuit. "Previous" is meant in the "circular" sense. That is, each cell status circuit, CSC.sub.x, is connected to receive CAS.sub.((X-1)+N) REM N. Furthermore, each cell status circuit, CSC.sub.x, is configured such that the cell availability status signal, CAS.sub.x, that it provides to its output, is identical to the cell availability status signal, CAS.sub.((X-1)+N) REM N, provided by the "previous" cell availability status circuit, CSC.sub.((X-1)+N) REM N, unless:

(1) AV.sub.-- ADD.sub.-- DEC.sub.x does not indicate that CBC.sub.x is the first circular buffer cell available for access; and

(2) UNAV.sub.-- ADD.sub.-- DEC.sub.x does not indicate that the CBC.sub.x is the first circular buffer cell unavailable for access.

Otherwise, if AV.sub.-- ADD.sub.-- DEC.sub.x does indicate that CBC.sub.x is the first circular buffer cell available for access in which case the cell availability status signal, CAS.sub.x, provided by the cell status circuit, CSC.sub.x, has a first state, to indicate that CBC.sub.x is available for access. Finally, if UNAV.sub.-- ADD.sub.-- DEC.sub.x does indicate that the CBC.sub.x is the last circular buffer cell available for access, the cell availability status signal, CAS.sub.x, provided by the cell status circuit, CSC.sub.x, has a second state to indicate that CBC.sub.x is unavailable for access.

FIGS. 3-5 illustrates different embodiments (300, 400, and 500, respectively) of a cell status circuit, CSC.sub.x, of the cell determination logic circuit 130. Throughout the foregoing description, it is assumed that the cell availability status signal indicates availability with a "high" level and indicates nonavailability with a "low" level. Also, it is assumed that the decoded available and unavailable address indicators, AV.sub.-- ADD.sub.-- DEC.sub.x and UNAV.sub.-- ADD.sub.-- DEC.sub.x, respectively, are active low. However, based on the teaching provided herein, it would be well within the ability of one skilled in the art to implement the invention utilizing reverse polarity from that described above.

Referring now to FIG. 3, a first two-to-one data selector 310 has its first data input "D0" connected to receive a constant signal having a level at ground, and its second data input "D1" connected to receive the cell availability signal, CAS.sub.((X-1)+N) REM N, generated by the "previous" cell availability status circuit, CSC.sub.((-1)+N) REM N. One of the signals provided to first data input "D0" and second data input "D1" of the first data selector 310 is selected to be provided to the output "Q" of data selector 310 under the control of AV.sub.-- ADD.sub.-- DEC.sub.x, provided to the select input "S" of data selector 310.

A second two-to-one data selector 320 has its first input "D0" connected to receive a constant signal having a level at V.sub.cc, and its second input "D1" connected to receive the signal output from the output "Q" of the first data selector 310. One of the signals provided to first data input "D0" and second data input "D1" of the second data selector 320 is selected to be provided to the output "Q" of data selector 320 under the control of UNAV.sub.-- ADD.sub.-- DEC.sub.x, provided to the select input "S" of data selector 310. The signal provided to the output "Q" of data selector 320 is the cell availability signal, CAS.sub.x.

FIG. 4 illustrates a further embodiment 400 of a cell status circuit, CSC.sub.x, of the cell determination logic circuit 130. Referring now to FIG. 4, a first two-input NAND device 410 is connected to receive UNAV.sub.-- ADD.sub.-- DEC.sub.x at its first input "D0" and is connected to receive the cell availability signal, CAS.sub.((X-1)+N) REM N, generated by the "previous" cell availability status circuit, CSC.sub.((X-1)+N) REM N. The first two-input NAND device 410 subjects the signal provided to the first data input "D0" and the second data input "D1" to a NAND logic function, and the result of the NAND logic function is provided to the output "Q" of the NAND device 410.

A second two-input NAND device 420 is connected to receive AV.sub.-- ADD.sub.-- DEC.sub.x at its first data input "D0" and is connected to receive the signal output from the "Q" output of the first two-input NAND device 410. The second two-input NAND device 420 subjects the signal provided to the inputs "D0" and "D1" to a NAND logic function, and the result of the NAND logic function is provided to the output "Q" of the second two-input NAND device 420 as the cell availability signal, CAS.sub.x.

The FIG. 4 embodiment 400 has an advantage over the FIG. 3 embodiment 300 that there is less "ripple" delay through the two NAND devices 410, 420 of the FIG. 4 embodiment 400 than there is through the two data selectors 310, 320 of the FIG. 3 embodiment 300.

FIG. 5 illustrates a still further embodiment 500 of a cell status circuit, CSC.sub.x, of the cell determination logic circuit 130. Referring now to FIG. 5, a four-to-one data selector 510 has its first and second data inputs, "D0" and "D1" connected to receive a constant signal having a level at V.sub.cc. The four-to-one data selector 510 has its third data input, "D2" connected to receive a constant signal having a level at ground. Finally, the four-to-one data selector 510 has its fourth data input, "D3" connected to receive the cell availability signal, CAS.sub.((X-1)+N) REM N. generated by the "previous" cell availability status circuit, CSC.sub.((X-1)+N) REM N.

One of the signals provided to first through fourth data inputs, "D0" through "D3" , respectively, of the four-to-one data selector 510 is selected to be provided to the output "Q" of data selector 510 under the control of UNAV.sub.-- ADD.sub.-- DEC.sub.x, provided to the select input "S0" of data selector 510 and AV.sub.-- ADD.sub.-- DEC.sub.x, provided to the select input "S1" of data selector 510.

The FIG. 5 embodiment 500 has an even further advantage over the FIG. 3 embodiment 300 than the FIG. 4 embodiment 400. In particular, there is even less "ripple" delay through the four-to-one data selector 510 of the FIG. 5 embodiment than there is through the two NAND devices 410, 420 of the FIG. 4 embodiment 400.

The invention embodiments described herein have been implemented in an integrated circuit which includes a number of additional functions and features which are described in the following co-pending, commonly assigned patent applications, the disclosure of each of which is incorporated herein by reference: U.S. patent application Ser. No. 08/45319, entitled "DISPLAY CONTROLLER CAPABLE OF ACCESSING AN EXTERNAL MEMORY FOR GRAY SCALE MODULATION DATA" (atty. docket no. NSC1-62700); U.S. patent application Ser. No. 08451965, entitled "SERIAL INTERFACE CAPABLE OF OPERATING IN TWO DIFFERENT SERIAL DATA TRANSFER MODES" (atty. docket no. NSC 1-62800); U.S. patent application Ser. No. 08/43076, entitled "HIGH PERFORMANCE MULTIFUNCTION DIRECT MEMORY ACCESS (DMA) CONTROLLER" (atty. docket no. NSC1-62900); U.S. patent application Ser. No. 08/452001, entitled "OPEN DRAIN MULTI-SOURCE CLOCK GENERATOR HAVING MINIMUM PULSE WIDTH" (atty. docket no. NSC1-63000); U.S. patent application Ser. No. 08/451503, entitled "INTEGRATED CIRCUIT WITH MULTIPLE FUNCTIONS SHARING MULTIPLE INTERNAL SIGNAL BUSES ACCORDING TO DISTRIBUTED BUS ACCESS AND CONTROL ARBITRATION" (atty. docket no. NSC1-63100); U.S. patent application Ser. No. 08/451924, entitled "EXECUTION UNIT ARCHITECTURE TO SUPPORT x86 INSTRUCTION SET AND x86 SEGMENTED ADDRESSING" (atty. docket no. NSC1-63300); U.S. patent application Ser. No. 08/451444, entitled "BARREL SHIFTER" (atty. docket no. NSC1-63400); U.S. patent application Ser. No. 08/451204, entitled "BIT SEARCHING THROUGH 8, 16, OR 32-BIT OPERANDS USING A 32-BIT DATA PATH" (atty. docket no. NSC1-63500); U.S. patent application Ser. No. 08/451195, entitled "DOUBLE PRECISION (64-BIT) SHIFT OPERATIONS USING A 32-BIT DATA PATH" (atty. docket no. NSC1-63600); U.S. patent application Ser. No. 08/451571, entitled "METHOD FOR PERFORMING SIGNED DIVISION" (atty. docket no. NSC1-63700); U.S. patent application Ser. No. 08/452112, entitled "METHOD FOR PERFORMING ROTATE THROUGH CARRY USING A 32-BIT BARREL SHIFTER AND COUNTER" (atty. docket no. NSC1-63800); U.S. patent application Ser. No. 08/451434, entitled "AREA AND TIME EFFICIENT FIELD EXTRACTION CIRCUIT" (atty. docket no. NSC1-63900); U.S. patent application Ser. No. 08/451535, entitled "NON-ARITHMETICAL CIRCULAR BUFFER CELL AVAILABILITY STATUS INDICATOR CIRCUIT" (atty. docket no. NSC1-64000); U.S. patent application Ser. No. 08/445563, entitled "TAGGED PREFETCH AND INSTRUCTION DECODER FOR VARIABLE LENGTH INSTRUCTION SET AND METHOD 0F OPERATION" (atty. docket no. NSC1-64100); U.S. patent application Ser. No. 08/450153, entitled "PARTITIONED DECODER CIRCUIT FOR LOW POWER OPERATION" (any. docket no. NSC1-64200); U.S. patent application Ser. No. 08/451495, entitled "CIRCUIT FOR DESIGNATING INSTRUCTION POINTERS FOR USE BY A PROCESSOR DECODER" (atty. docket no. NSC1-64300); U.S. patent application Ser. No. 08/451219, entitled "CIRCUIT FOR GENERATING A DEMAND-BASED GATED CLOCK" (atty. docket no. NSC1-64500); U.S. patent application Ser. No. 08/451214,entitled "INCREMENTOR/DECREMENTOR" (atty. docket no. NSC1-64700); U.S. patent application Ser. No. 08/451150, entitled "A PIPELINED MICROPROCESSOR THAT PIPELINES MEMORY REQUESTS TO AN EXTERNAL MEMORY" (atty. docket no. NSC1-64800); U.S. patent application Ser. No. 08/451198, entitled "CODE BREAKPOINT DECODER" (atty. docket no. NSC1-64900); U.S. patent application Ser. No. 08/445569, entitled "TWO TIER PREFETCH BUFFER STRUCTURE AND METHOD WITH BYPASS" (atty. docket no. NSC1-65000); U.S. patent application Ser. No. 08/445564, entitled "INSTRUCTION LIMIT CHECK FOR MICROPROCESSOR" (atty. docket no. NSC1-65100); U.S. patent application Ser. No. 08/452306, entitled "A PIPELINED MICROPROCESSOR THAT MAKES MEMORY REQUESTS TO A CACHE MEMORY AND AN EXTERNAL MEMORY CONTROLLER DURING THE SAME CLOCK CYCLE" (atty. docket no. NSC1-65200); U.S. patent application Ser. No. 08/452080, entitled "APPARATUS AND METHOD FOR EFFICIENT COMPUTATION OF A 486.TM. MICROPROCESSOR COMPATIBLE POP INSTRUCTION" (atty. docket no. NSC1-65700); U.S. patent application Ser. No. 08/450154, entitled "APPARATUS AND METHOD FOR EFFICIENTLY DETERMINING ADDRESSES FOR MISALIGNED DATA STORED IN MEMORY" (atty. docket no. NSC1-65800); U.S. patent application Ser. No. 08451742, entitled "METHOD OF IMPLEMENTING FAST 486.TM. MICROPROCESSOR COMPATIBLE STRING OPERATION" (atty. docket no. NSC1-65900); U.S. patent application Ser. No. 08/452659, entitled "A PIPELINED MICROPROCESSOR THAT PREVENTS THE CACHE FROM BEING READ WHEN THE CONTENTS OF THE CACHE ARE INVALID" (atty. docket no. NSC1-66000); U.S. patent application Ser. No. 08/451507, entitled "DRAM CONTROLLER THAT REDUCES THE TIME REQUIRED TO PROCESS MEMORY REQUESTS" (atty. docket no. NSC1-66300); U.S. patent application Ser. No. 08/451207, entitled "INTEGRATED PRIMARY BUS AND SECONDARY BUS CONTROLLER WITH REDUCED PIN COUNT" (atty. docket no. NSC1-66400); U.S. patent application Ser. No. 08/452365, entitled "SUPPLY AND INTERFACE CONFIGURABLE INPUT/OUTPUT BUFFER" (atty. docket no. NSC1-66500); U.S. patent application Ser. No. 08/451744, entitled "CLOCK GENERATION CIRCUIT FOR A DISPLAY CONTROLLER HAVING A FINE TUNEABLE FRAME RATE" (atty. docket no. NSC1-66600); U.S. patent application Ser. No. 08/451206, entitled "CONFIGURABLE POWER MANAGEMENT SCHEME" (atty. docket no. NSC1-66700); U.S. patent application Ser. No. 08/452350, entitled "BIDIRECTIONAL PARALLEL SIGNAL INTERFACE" (atty. docket no. NSC1-67000); U.S. patent application Ser. No. 08/452094, entitled "LIQUID CRYSTAL DISPLAY (LCD) PROTECTION CIRCUIT" (atty. docket no. NSC1-67100); U.S. patent application Ser. No. 08/45156, entitled "DISPLAY CONTROLLER CAPABLE 0F ACCESSING GRAPHICS DATA FROM A SHARED SYSTEM MEMORY" (atty. docket no. NSC1-67500); U.S. patent application Ser. No. 08/450726, entitled "INTEGRATED CIRCUIT WITH TEST SIGNAL BUSES AND TEST CONTROL CIRCUITS" (atty. docket no. NSC1-67600); U.S. patent application Ser. no. 08/445568, entitled "DECODE BLOCK TEST METHOD AND APPARATUS" (atty. docket no. NSC1-68000).

It should be understood that various alternatives to the embodiments of the invention described herein may be employed in practicing the invention. It is intended that the following claims define the scope of the invention and that methods and apparatus within the scope of these claims and their equivalents be covered thereby.