Dual Purpose Security Architecture With Protected Internal Operating System

The present invention concerns chip architecture and particularly a dual purpose secure chip architecture with a protected internal operating system.

For some processing applications, it is essential to operate in a secure environment so that operations cannot be probed or altered. In the prior art, various methods have been used to pro, de for a secure processing environment.

For example, a mechanical chassis can be used to house processing equipment. This mechanical chassis can include tamper switches and other elements to detect and protect against tampering and alterations. Unfortunately, such a mechanical chassis can add a significant amount of expense to a product.

Alternately, in order to restrict access to particular integrated circuits, the integrated circuits can be covered with epoxy or other chemical materials to hinder access. Unfortunately, often this can be easily defeated and so provides only a nominal amount of protection.

Another method to pro,de for a secure processing environment is to implement the system on a single integrated circuit. However, if a secure operating system is not implemented, these systems also, generally, can be defeated. However, implementation of a completely secure operating system for all functions significantly limits the functionality of the system.

In accordance with the preferred embodiment of the present invention, a secure mode within a dual mode processor is implemented. In a general/external mode, the dual mode processor executes instructions provided from an external source. The instructions are supplied to the processor via input/output to the processor. Upon receiving a special software or hardware interrupt, the dual mode processor enters a secure/internal mode. The interrupt specifies a secure function stored in a read-only memory within the dual mode processor. Upon receiving such an interrupt, input/output to the dual mode processor is disabled. An internal pointer identified by the interrupt is used to identify the location of the secure function stored in the read-only memory within the processor. The identified secure function is executed by the processor. During execution of the secure function, any attempt to insert instructions not originating from the read-only memory is ignored. However, the processor is allowed to access data specifically identified by secure function being executed.

Upon completion of performance of the secure function, an exit routine is executed to enable input/output to the processor and to resume execution of instructions provided via input/output from the source external to the processor. The instructions for the exit routine are also stored within the read-only memory.

In the preferred embodiment, the exit routine utilizes a special hardware control circuit to enable input/output to the processor. Also in the preferred embodiment, upon reset, the processor performs self-testing in secure mode, with input/output disabled. Upon successful completion of performance of the self test function, the exit routine is executed to enable input/output to the processor and to begin execution of instructions provided via input/output from the source external to the processor. Assurance hardware is used to provide protection against physical and electrical tampering

The dual mode processing system is used, for example, to perform cryptographic functions such as encryption or public key exchange. For example, in one such application, data blocks or packets are intercepted and sent to the dual mode processor. Primitives which encrypt/decrypt the data are stored in the read-only memory within the processor. These primitives are executed when the dual mode processor is in secure mode. Other system functions are performed in general mode.

The present invention allows for an inexpensive, efficient means to provide for dual mode processing. When operating in a general mode, all external instructions may be executed without any overhead associated with a secure operating system. During operation in secure mode operation, secure functions are executed in a manner protected from alteration and probing.

FIG. 1 shows a block diagram of a system in which a dual mode processor is used in a secure mode for encryption and decryption in accordance with a preferred embodiment of the present invention.

FIG. 2 shows a simplified block diagram of the dual mode processor shown in FIG. 1 in accordance with a preferred embodiment of the present invention.

FIG. 3 shows a flowchart which illustrates initialization of the dual mode processor shown in FIG. 2 in accordance with a preferred embodiment of the present invention.

FIG. 4 shows a flowchart which illustrates operation of the dual mode processor in the secure operating mode in accordance with the preferred embodiment of the present invention.

FIG. 5 is a block diagram which indicates contents of a ROM within the dual mode processor shown in FIG. 2 in accordance with the preferred embodiment of the present invention.

FIG. 1 shows a block diagram of a system in which a dual mode processor 12 is used in a secure (internal) mode for encryption and decryption in accordance with a preferred embodiment of the present invention. Dual mode processor 12 communicates with a control channel processor 11 through a data channel 18 and a data channel 19. Data channels 18 and 19, for example, are implemented as an input/output (I/O) bus which operates in accordance with a input/output bus standard, such as, for example, the Industry Standard Architecture (ISA). Control channel processor 11 provides data to dual mode processor 12. In addition, when dual mode processor 12 is in general (external) mode, control channel processor provides instructions to be executed by dual mode processor 12.

Dual mode processor 12 is used to perform a cryptographic function such as encryption or public key exchange. For example, FIG. 1 shows a demultiplexor 13 which receives an encrypted data stream 14 and produces a de-multiplexed decrypted data stream 15. Encrypted data stream 14 and decrypted data streams 15 are, for example composed of data blocks or data packets being transferred to and from demultiplexor 13. Demultiplexor 13 Forwards encrypted data to dual mode processor 12 through a data path 16. Dual mode processor 12 decrypts the data and returns the decrypted data to demultiplexor 13 through a data path 17.

In order to protect the integrity of the particular cryptographic scheme utilized, it is necessary to protect the cryptographic functions within dual mode processor 12 from access or alteration. For this purpose, dual mode processor 12 includes two operating modes. In a general mode, dual mode processor 12 performs instructions received from control channel processor 11. In a secure mode, dual mode processor performs cryptographic functions in a secure environment, as discussed more fully below.

FIG. 2 shows a simplified block diagram of dual mode processor 12 in accordance with a preferred embodiment of the present invention. Processing functions are performed by processing functions circuitry 21. For example, processing functions circuitry 21 is a reduced instruction set computer (RISC) processor. Processing functions circuitry 21 interfaces with data channels 18 and 19 through bus input/output (I/O) interface circuitry 23. Processing functions circuitry 21 interfaces with data paths 16 and 17 through crypto input/output (I/O) interface circuitry 25.

A random access memory (RAM) 22 is utilized by processing functions circuitry 21, for example, for data storage and for high speed execution of small blocks of code. A read-only memory (ROM) 24 is used to contain secure primitives which are executed by processing functions circuitry 21 when dual mode processor 12 is in secure mode. An I/O hardware control circuit 26 is addressed by a secure mode exit routine in order to release I/O controls when dual mode processor 12 is transitioning from secure mode to general mode. Hardware control circuit 26 contains exit logic which insures that dual mode processor 12 will execute a set sequence of commands that might not otherwise execute if dual mode processor 12 lost its step. The use of hardware control circuit 26 to transition between secure mode and general mode insures that if dual mode processor 12 loses step, for example due to a power glitch or tampering, the dual mode processor 12 will not prematurely or incompletely exit the secure mode. When a tampering or a glitch affects operation of dual mode processor 12 during the secure mode, hardware control circuit 26 will lock up dual mode processor 12 and require a reset before operation of dual mode processor 12 resumes.

Upon entry of the secure mode, hardware control circuit 26 disables input/output to dual mode processor 12. Upon exit of secure mode, hardware control circuit 26 enables input/output to dual mode processor 12.

In secure mode, all external access to processing functions 21 is disabled. While in secure mode, processing functions 21 executes only the secure primitives in ROM 24. In secure mode, processing functions 21 still has the ability to access external memory for data, but only as allowed by the secure primitives within ROM 24. Further, in the secure mode, dual mode processor 12 ignores all attempts to insert an illegal instruction.

Assurance logic 27 provides protection against physical and electrical tampering. Assurance logic is activated upon entering the secure mode.

FIG. 3 shows a flowchart which illustrates initialization of dual mode processor 12. In a step 31, the system is reset. Upon reset, all input/output paths of dual mode processor 12 are disabled. In a step 32, dual mode processor 12 performs a self-test function to assure proper operation. The self-test routine executed is stored by ROM 24 as a secure routine. During execution of the self-test routine, assurance logic 27 is activated to prevent physical and electrical tampering with dual mode processor 12. If dual mode processor 12 passes the self-test function, in a step 33, the secure mode exit routine is executed. The secure mode exit routine cleans up or clears all registers. The secure mode exit routine then addresses hardware control circuit 26 in order to release I/O controls. In a step 34, the exit routine is exited and the program manager is called. In a step 35, the program manager manages execution of external programming code executed by dual mode processor 12 when dual mode processor 12 is in general mode.

FIG. 4 shows a flowchart which illustrates operation of the dual mode processor in the secure operating mode in accordance with the preferred embodiment of the present invention. Before step 41, dual mode processor is in the general mode and the program manager manages execution of external programming code executed by dual mode processor 12. In a step 41, a special software or hardware interrupt (SWI) is asserted. The special software/hardware interrupt directs dual mode processor 12 in order to cause dual mode processor 12 to enter the internal secure operating system. The special software/hardware interrupt includes an address which indicates a function stored within ROM 24 to be executed.

In a step 42, the secure operating system is entered. All input/output is disabled by I/O hardware control circuit 26. Assurance logic 27 is activated to protect dual mode processor 12 from physical or electrical tampering. In a step 43, the address function within ROM 24 specified by the address within the special software/hardware interrupt is located by an internal pointer. In a step 44, the addressed function is executed. In a step 45, the secure mode exit routine is executed. The secure mode exit routine cleans up or clears all registers. The secure mode exit routine then instructs hardware control circuit 26 to release I/O controls. In a step 46, the exit routine is exited and the program manager is called. In a step 47, the program manager manages execution of external programming code executed by dual mode processor 12 when dual mode processor 12 is in general mode.

FIG. 5 shows an example of contents within ROM 24. ROM 24 contains a secure mode entry routine 51. Secure mode entry routine 51 is the first routine executed when secure mode is entered or when dual mode processor 12 is reset. Secure mode entry routine 51 disables all I/O to dual mode processor 12 and uses internal pointers 52 to jump to secure functions 53. Each secure function in secure functions 53 is made up of one or more secure primitives. The particular secure functions stored within ROM 24 vary with the particular application to be implemented. For example, in the preferred embodiment, secure functions 53 include primitives used for cryptographic operations. After a secure function has been executed, the secure mode is exited using secure mode exit routine 54.

The foregoing discussion discloses and describes merely exemplary methods and embodiments of the present invention. As will be understood by those familiar with the art, the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.