Cache Testing Using a Modified Snoop Cycle Command

The present invention relates to cache stores and more particularly to testing such stores.

Some data processing systems, such as those based on the Intel Pentium microprocessor chip, have portions that are not accessible to testing using normal commands of the system. Such a cache can be logically divided into three separate entities: a data random access memory (data RAM) for storing system data and instructions; a tag RAM for storing status data about the information stored in the data RAM; and control circuitry for overall operation of the cache. A test fixture for this cache must be able to fully test all circuit elements in all three of these entities in order to be sure of their quality and operability. The present invention is concerned with testing of the tag RAM independently of the other entities of the cache. The behavior of the cache is completely dependent of the status data stored in the tag RAM. If the bit locations in the tag RAM containing those status bits are defective, the cache will react in ways that are difficult to debug. In addition to testing the tag RAM for its independent operability, it is desirable to be able to enter data into it to test the cache and the system for their overall operability. However, while the storage locations in the data RAM are accessible and easy to test, the storage locations in the tag RAM, including those storing status data, are not readily accessible. All bits in a tag RAM word go to the cache controller and not onto the microprocessor system bus. Therefore, it is difficult to determine when an error occurs if an error is in the tag RAM or in the cache controller. Furthermore, certain data bit patterns do not occur in the tag RAM during normal system operation. For these reasons it is difficult to test the bit positions of the tag RAM themselves and to enter test patterns to test overall cache operation.

In accordance with the present invention a standard system instruction is modified and control circuits in the cache are provided which respond to this modified command to provide accessibility to the tag RAM through a data path which is independent of the cache controller. In the preferred embodiment of this invention, the cache controller of a second level cache in an Intel Pentium processor based computer system contains test circuitry that allows the system or a test fixture to read and write directly into all tag RAM databit locations. This circuitry responds to a modified External Address Strobe (EADS#) command to invoke the tag test cycle. The EADS# command is normally used in a SNOOP read cycle by the system. In a SNOOP cycle, the main memory controller invokes the EADS# command to request the first level (L.sub.1) and second level (L.sub.2) caches for modified information stored in those caches. In the tag test cycle the EADS# command line is held down twice as long as it would in a normal SNOOP read Cycle. Because of its added length, the SNOOP cycle circuitry in the L.sub.2 cache ignores the command on the EADS# command line. However, the tag RAM test circuitry in the L.sub.2 cache recognizes the extended EADS# strobe providing a path to access all bit locations in a tag RAM for both read and write cycles to test the tag RAM or to load those bit positions to selected states in testing other portions of the cache.

Therefore, it is an object of the present invention to test normally inaccessible portions of a cache.

It is another object of the invention to use a modified system command to invoke an altered cache instruction that provides an operating state for use in testing.

The foregoing and other objects, features and advantages of the present invention will be apparent from the following description of a preferred embodiment of the invention as illustrated in the accompanying drawings of which:

FIG. 1 is a block diagram of main memory and the L.sub.1 and L.sub.2 caches linked together by data and address buses;

FIG. 2 is a schematic diagram of the L.sub.2 cache in FIG. 1;

FIG. 3 is a schematic representation of the L.sub.2 cache addressing circuitry;

FIGS. 4a, 4b and 4c are signal diagrams of showing the command signals used in a SNOOP cycle, a tag test write cycle and a tag test read cycle respectively;

FIG. 5 is a flow diagram indicating the effect the difference of length of the EADS# cycle has on L.sub.2 cache response; and

FIG. 6 is a block diagram of the test circuitry in the L.sub.2 cache.

Referring now to FIG. 1, a data bus 110 and an address and control line buss 112 are shown linking the L.sub.2 cache 116, to the L.sub.1 cache 114, and the RAM controller 122 of the random access main memory (RAM) 118. The various memory units 114 to 118 respond to instructions of the central processing unit(CPU) 120. The L.sub.1 cache 114 is the fastest in its response and the most costly per bit. The response of the L.sub.2 cache 116 is not quite as fast as that of the L.sub.1 cache and its cost per bit is less. The main RAM 118 is the slowest of the three units and cost the least per bit.

The sizes of the L.sub.1, L.sub.2 caches and RAM memory are in inverse proportion to their speed. The L.sub.2 cache 116 stores a portion of the content of the main RAM 118 while the L.sub.1 cache 114 contains a portion of the entries of the L.sub.2 cache 116. The disclosed arrangement is part of a personal computer system using an Intel Pentium microprocessor. The microprocessor configuration and attendant requirements for a system using that microprocessor can be found in a manual entitled "Pentium Family Users Manual Volume 1: Data Book" published by the Intel Corporation in 1994. This manual is hereby incorporated by reference.

As shown in FIG. 2, the motherboard 200 for the computer system contains two connectors 210 and 212 for receipt of one or two L.sub.2 cache memory cards 214 and 216. The cards 214 and 216 are identical. They each contain three basic components, a controller 218, a tag RAM 220 and a data RAM 222. The data RAM 222 stores system data and instructions. The tag RAM 220 stores address bits and status bits of the information in the storage elements of the data RAM 222. The controller 218 uses information in the tag RAM to determine whether the data requested by the CPU 120 is in the data RAM 222 and if it can be transmitted to the CPU 120.

Referring to FIG. 3, of the 32-bit CPU address word 310 received on the address bus 112 of FIG. 2, bits 3 to 29 are pertinent to the normal operation of the L.sub.2 cache. Bits 0 to 2 are for a byte address in a word. The L.sub.2 cache is addressable only down to the word level so bits 0 to 2 are ignored. Bits 30 and 31 are for addresses above the gigabyte range which do not occur in the present system. Therefore bit 29 is the highest order bit in the normal operation of the system.

Referring to both FIGS. 2 and 3, for an L.sub.2 cache with a 2 megabyte data RAM 222, the tag RAM 220 is directly addressed from the buss 112 with bits 5 to 20 of the address 310. This reads a 12 bit word 312 from the tag RAM 220. Each word 312 in the tag RAM 220 includes, in bit positions 3 to 11 of the word, the high order address bits 21 to 29 of data stored in RAM 222 and also includes three status bits in bit positions 0 to 2 of the word 312. A compare circuit 314 in the controller 218 determines if there is a match between the bits 21 to 29 of the stored and requested data by comparing those bits stored in words 312 and 310 respectively. If there is a match, a gate 316 transmits status bits 0 to 2 of the tag RAM word 312 to other circuitry in the controller 218 to determine if the data stored in data RAM 222 is valid. If the requested data resident in the RAM 222 is valid, bits 3 to 20 of the CPU address word 310 are used to access the data RAM 222. Bits 5 to 20 read a 32 byte word out of the data RAM 222 and bits 3 to 4 select the requested 8 bytes out of that 32 byte word.

The address bits and tag bits in a tag RAM word are loaded into the tag RAM 220 from the controller 218 and the address and tag bits stored with the tag RAM are fed back to the controller when they are read out. During normal operation, the contents of the tag RAM 220 are never directly loaded onto the data and address busses 110 and 112 of the system making accurate testing of the controller and Tag RAM very difficult. The proper testing of each is dependent on the proper operation of the other. This interdependency makes fault analysis difficult.

Testing of the tag RAM is also exacerbated by the fact that desired test patterns cannot be used because certain status bit combinations cannot be loaded into the tag RAM through the controller. The reason for this is based on the function of the status bits. They are to determine the accessibility to the data RAM location covered by those bits to a read or write operation by the CPU 120. When status bit 0 is a binary "0" the data RAM address location is read only. When status bit 0 is a binary "1" the data RAM address is writable. When status bits 1 and 2 are "1, 1" the data is modified (M) from the copy of the data in the RAM. When bits 1 and 2 are "0, 1" the data is exclusive (E) and can be modified. When bits 1 and 2 are "1, 0" the data is shared and cannot be modified and when they are "0, 0" the data is invalid. Therefore, certain combinations of the status bits 0 to 2 cannot logically occur during normal operation of the system. For instance, the combination "0, 1, 1" cannot occur because the data cannot be both read only and at the same time changed. As a result, the controller 218 is not designed to accommodate those combinations.

In accordance with the present invention, a control signal combination that would never occur during normal operation of the system is used to modify the caches configuration to permit it to load and unload the cache tag RAM directly. This allows full testing of the tag RAM and loading of any desired test pattern into the tag RAM to test other components of the L.sub.2 cache.

FIG. 4a shows a SNOOP cycle. In a Pentium based processor system, a SNOOP cycle is a request by the memory controller 122 of the main RAM 118 for a modified copy of data that may be resident in either the L.sub.1 or L.sub.2 cache. First, the controller 122 issues a BOFF# command. In response to the BOFF# command the processor 120 cancels all pending commands and lets the buses 110 and 112 float. The controller 122 waits two clock cycles for the buses 110 and 112 to quiet down and then issues an EADS# command with the placing of an address on the bus 112. The L.sub.2 cache recognizes the initiation of a SNOOP cycle when EADS# command appears. The L.sub.2 cache ignores the SNOOP cycle if the address requested by the controller 122 is not in the L.sub.2 cache or status bits in the tag RAM 220 are not 1,1,1 indicating the data at that address is modified. If the requested address is in the L.sub.2 cache and status bits in the tag memory indicate the data is modified, the L.sub.2 cache samples the HitM# line to determine if the L.sub.1 cache also has the modified data. If the HitM# line is low indicating the L.sub.1 cache has the data, the L.sub.2 cache treats the Snoop request as a write through cycle and ignores the request. However, if the HitM# line is high, indicating that the L.sub.2 cache alone has a copy of the modified data, the L.sub.2 cache will assert a BOFF# command on the 4th clock cycle and provide the requested data on bus 10.

To distinguish a tag RAM test from a SNOOP cycle, the length of the EADS# command is modified. As shown in FIGS. 4b and 4c, the EADS# command is twice the length in FIG. 4a for a SNOOP cycle. As shown in FIG. 5, circuitry in the L.sub.2 controller recognizes the differences in the length of the EADS# commands in the tag RAM test cycle and the SNOOP cycle. When the EADS# goes low 510 the RAM controller 122 or a tester can be requesting either a SNOOP or a tag RAM test cycle. If the EADS# line rises after one clock cycle, a SNOOP cycle 520 is to be performed. If it remains low for another clock cycle a tag RAM test cycle in the L.sub.2 cache has been requested. When information is to be read 550 from the L.sub.2 cache the read/write (W/R#) line is down and when information is to be written 560 into the cache, the W/R# line is high.

As shown in FIG. 6, detector 610 receives the EADS#, the system clock (CLK) and the R/W control signals from the cache input latches 600 for the control lines of the system address buss 112. Depending on whether the signal in the R/W input latch is up or down, the detector generates either a positive tag test read (TT/read) or tag test write (TT/write) pulse when the detector determines the EADS# command is two system clock cycles long. At the same time, the SNOOP circuits the L.sub.2 cache recognizing the additional length of the EADS# pulse remain disabled. When the EADS# command is only 1 cycle both the TT/read and TT/write pulses remain down and the SNOOP circuits perform a SNOOP cycle.

As shown in FIG. 3, address bit lines 5 to 20 are used to address a word line 312 of the tag RAM. Address bit lines 3 and 21 to 31 of the address buss are not used in tag RAM addressing during normal system operation. However, as shown in FIG. 6 they are used during tag RAM testing to load and unload data from the tag RAM array 660. Address bit lines 21 to 29 are used to carry data to and from the tag bit positions 3 to 11 of the addressed tag RAM line and address bit lines 3, 30 and 31 are used to load and unload data in the status bit positions 0 to 2 of the addressed tag RAM line.

The TT/write and TT/read signals access the address drivers of the tag RAM and also enable gate 640 to allow system address bit lines 3 and 21 to 31 in the address buss 112 to receive from or send information to the data drivers and sense amplifiers 650 of the tag RAM.

Referring to FIGS. 1, 4b and 6, during a tag test write cycle the tester asserts a BOFF# command to initiate the cycle. The tester then waits two cycles and issues an extended EADS# command. The tag test detector 610 recognizes this as a request to perform a tag test while SNOOP circuits 620 in the L.sub.2 cache do not recognize this as a valid EADS# command because of the additional length of the command. At the same time the tester provides an address to the tag RAM decoder 630 on bit lines 5 to 20 of the address bus 112. The tag test detector generates a TT/write pulse which gates data bits on bit lines 3 and 21 to 31 of the address buss to the sense amplifier/driver circuits 650 of the tag array. The TT/write signal activates logic circuit 670 to provide chip select output enable and a write signal to the tag array driver circuits 650 to load the data bits into the accessed word line of the tag array 660.

The tag test read cycle differs from the write cycle as shown in FIG. 4c. The BOFF# and EADS# commands are the same as in the write cycle. However, the W/R line is lowered resulting in a TT/read pulse which activates the sense amplifiers of the tag array and gate 640 to transmit the sensed data stored in the word line of the tag array accessed by address bits 5 to 20 onto bits 3 and 21 to 31 of the address buss 112. The data on the address lines is split. The first segment is the address provided on address lines 5 to 20 and the second is the data read from the array that is placed on address lines 3 and 21 to 31. The time between the segments is the logic response time of the circuitry.

While the invention has been described in detail herein in accordance with one embodiment thereof, many modifications and changes may be made by those skilled in the art. Accordingly, it is intended by the appended claims cover all such modifications and changes that fall within the true spirit and scope of the invention.