Zero Crossing Detector Circuit

This invention relates generally to a zero crossing detector circuit and, more particularly, to a circuit that includes a comparator being configured in a difference amp configuration that has balanced inputs.

Shown in FIG. 1 is a prior art zero crossing detector circuit. The illustrated circuit consists of an open-collector comparator circuit which is configured in a difference amp configuration. The zero crossing detector circuit generates an output square wave from an input sinusoidal wave. For example, the input sinusoidal wave is delivered to V.sub.1, which imposes a voltage on the non-inverting input V.sub.+ via R.sub.1, and to V.sub.2, which imposes a voltage on the inverting input V.sub.- via voltage divider R.sub.2 /R.sub.5. When V.sub.+ is greater than V.sub.- the circuit output is HIGH (V.sub.cc), and when V.sub.+ is greater than V.sub.- the circuit output is LOW (the saturation voltage of the comparator). Most importantly, however, the circuit detects the point in time when the input voltage makes a transition from a higher value to a lower value--referenced to zero volts. However, because the inputs V.sub.+ and V.sub.- are imbalanced, the circuit does not satisfactorily detect when the input signal crosses zero.

The present invention is directed to overcoming one or more of the problems as set forth above.

In one aspect of the present invention, a zero crossing detecting circuit is disclosed. The circuit includes a first comparator having an inverting and non-inverting input connected to an input signal. The non-inverting input of the first comparator is further connected to the first comparator output to provide a feed forward path. A second comparator is additionally included having an output connected to the first comparator inverting input. This provides the inverting input of the first comparator with a reference voltage that is substantially equal to that of the first comparator non-inverting input; thereby, providing the first comparator with balanced inputs.

For a better understanding of the present invention, reference may be made to the accompanying drawings in which:

FIG. 1 shows a prior art zero crossing detector circuit; and

FIG. 2 show a zero crossing detector circuit associated with the present invention.

As explained above, the zero crossing detector circuit 100 of FIG. 1 includes a first comparator 105 being configured in a difference amp configuration. Preferably, R.sub.1 =R.sub.2 and R.sub.3 =R.sub.5 so that when V.sub.1 is greater than V.sub.2, V.sub.out will go HIGH (V.sub.cc). Alternately, when V.sub.1 is less than V.sub.2, V.sub.out will go LOW (V.sub.sat). However, because the inputs V.sub.+ and V.sub.- are not equally balanced, the accuracy of the circuit 100 is unsatisfactory. The voltage values for the inputs are shown below:

As shown by the above equations, the imbalance is due to the non-inverting input V.sub.+ being referenced to the saturation voltage, while the inverting input V.sub.- is referenced to ground; thereby, resulting in an imbalance of approximately 0.2 volts.

Thus, a novel way to compensate for the imbalanced inputs is to equivalently offset the R.sub.2 /R.sub.5 voltage divider with the saturation voltage of a similarly biased comparator. Referring now to FIG. 2, the preferred embodiment 200 of the present invention is illustrated. As shown, a second comparator 205 having an output is connected to the V.sub.- input of the first comparator 105 to provide the V.sub.- input with a voltage reference of V.sub.sat of the second comparator 205. The inverting input V.sub.- of the second comparator 205 is connected to source voltage V.sub.cc via resistor R.sub.7, while the non-inverting input V.sub.+ is connected to ground via resistor R.sub.8. Note, R.sub.7 should have the same value as R.sub.8. Thus, now the inverting and non-inverting input of the first comparator 105 are referenced to approximately the same voltage; thereby, providing for greater accuracy.

To insure that the saturation voltage of the second comparator 205 is substantially the same as the first comparator 105, the first and second comparators should be biased similarly. Thus, R.sub.4 should have the same value as R.sub.6 to similarly bias the output transistors of both comparators. However, because environmental changes in temperature effect the situation voltage of the comparators, it is advantageous to have the second comparator 205 be from the same integrated circuit package as the first comparator 105 to insure that the saturation voltages of the comparators are equally affected by temperature. Thus, because the input voltage of the inverting input V.sub.- of the first comparator 105 is now referenced to substantially the same voltage as the non-inverting input V.sub.+, the accuracy of detecting when the input voltage crosses zero is greatly increased.

Thus, while the present invention has been particularly shown and described with reference to the preferred embodiment above, it will be understood by those skilled in the art that various additional embodiments may be contemplated without departing from the spirit and scope of the present invention.

Many mechanisms, such as diesel engines for example, have parts which cooperate in time relation to produce optimum performance. Conventional timing methods include attaching transducers to the engine crank or camshaft to generate a timing signal and measuring the period of the timing signal. The preferred embodiment of the present invention is adapted to receive the timing signal, which is produced in sinusoidal form, and convert the sinusoidal signal to a series of reference pulses. For example, as the input signal makes a transition from a high level to a low level, the circuit of the present invention will produce a LOW signal shortly after the input signal crossing zero volts, i.e., when the input signal goes from a positive voltage value to a negative voltage value. Similarly, as the input signal makes a transition from a low level to a high level, the circuit of the present invention will produce a HIGH signal when the input signal crosses zero, i.e., when the input signal goes from a negative voltage value to a positive voltage value.

Other aspects, objects and advantages of the present invention can be obtained from a study of the drawings, the disclosure and the appended claims.