Smart Battery Algorithm for Reporting Battery Parameters to an External Device

The present invention relates to generally to the art of rechargeable batteries and more specifically to a smart battery for use in an intelligent device having power management capabilities. The invention also includes an apparatus and method for controlling the operation of smart rechargeable Nickel Metal Hydride (NiMH) or Nickel Cadmium (NiCad) batteries, and the like, which enables the smart battery to report out accurate information to the intelligent device for power management and charge control specific to the battery's state of charge and chemistry.

The advent of intelligent portable electronic devices such as notebook computers, video cameras, cellular phones has enabled the development of smart rechargeable batteries that can communicate with the intelligent device to provide accurate information on the battery's present state of charge, and how best to recharge the battery to maintain maximum battery life, thus enabling the highest number of charge-discharge cycles. A user of such intelligent portable devices utilizing such smart batteries will not only know how much charge is left in the battery, but battery run time at various rates of power consumption. This enables the user to select a mode of operation that will enable maximum service life on the remaining state of charge and, how long the device will continue to operate.

Prior art rechargeable battery units have been provided with means for generating some desired information to their users, including for instance, a charge monitor and fuel gauge such as that disclosed in U.S. Pat. No. 5,315,228 which discloses a method for calculating state of charge and reporting run time to empty to the host computer system.

However, there is a need for a rechargeable power unit that will accurately maintain its own state of charge information even when nominally fully discharged such that a user will have instantaneous access thereof. Moreover, there is also a need for an intelligent rechargeable battery that can provide the user with an accurate prediction of its remaining operating time at various levels of power consumption. The user of such an intelligent device, such as a portable computer, can thus elect to power down a hard disk drive to extend the operation of the portable computer for a longer period of time than would had been possible at the higher rate of power consumption.

Accordingly, it is an object of the present invention to provide a smart battery for use in a host computer that will optimize the performance of the smart rechargeable battery throughout its life cycle.

It is another object of the instant invention to provide a control method for a microprocessor controlled rechargeable battery that performs battery capacity calculations for communication to a host computer device or a smart battery charge device.

It is still another object of the instant invention to provide a control method for a microprocessor controlled rechargeable battery that provides intelligence in the form of present state of charge and battery charge parameters to a host device for communication to a smart charger.

Still another object of the instant invention is to provide a control method for a microprocessor controlled rechargeable battery that calculates predictive data such as the battery's remaining life at the current rate of drain and at alternate rates of drain.

Yet still another object of the instant invention to provide a control method for a microprocessor controlled rechargeable battery that communicates factual data such as battery identification data, temperature, voltage, charge/discharge current and existing state of charge to a host computer device or smart battery charge device.

Furthermore, another object of the present invention is to provide a control method for a microprocessor controlled rechargeable battery that will communicate potential problems and potentially dangerous conditions in the form of warnings and alarms to a host device, or a battery charge device, and subsequently, to the users thereof.

It is a further object of the instant invention to provide a control method for a microprocessor controlled rechargeable battery that monitors battery operating parameters such as voltage, current, and temperature to thereby enable either a rapid charging rate or an optimal charging rate from any charged state.

These and other objects of the present invention are attained with a smart battery which provides electrical power and which reports predefined battery parameters to an external device having a power management system, wherein the battery includes:

(a) at least one rechargeable cell connected to a pair of terminals to provide electrical power to an external device during a discharge mode and to receive electrical power during a charge mode, as provided or determined by said remote device,

(b) a data bus for reporting predefined battery identification and charge parameters to the external device,

(c) an analog means for generating analog signals representative of battery voltage and current at said terminals, and an analog signal representative of battery temperature at said cell,

(d) a hybrid integrated circuit (IC) having a microprocessor for receiving the analog signals and converting them to digital signals representative of battery voltage, current and temperature, and calculating actual charge parameters over time from said digital signals, said calculations including one calculation according to the following algorithm;

wherein .epsilon..sub.c is a function of battery current and temperature; and I.sub.s is a function of battery temperature and CAP.sub.FC,

(e) a data memory defined within said hybrid IC for storing said predefined battery identification and actual charge parameters, even when nominally fully discharged, said charge parameters including at least full charge capacity and remaining capacity,

(f) a bus controller defined within said hybrid IC for sending battery messages to said remote device over said data bus, said messages including said predefined battery identification and said actual charge parameters.

Superimposed on this equation is reset logic, to be explained below, that self corrects the value of CAP.sub.FC with a capacity calculation at each full charge (EOC) and each end of full discharge.

Further benefits and advantages of the invention will become apparent from a consideration of the following detailed description given with reference to the accompanying drawings, which specify and illustrate preferred embodiments of the invention.

FIG. 1 is a diagrammatic block diagram of a smart battery system connected to a host computer and battery charging device.

FIG. 2(a) is a simplified block diagram of the smart battery and connector, including a pinout diagram of an Application Specific Integrated Circuit (ASIC) used in the present invention.

FIG. 2(b) illustrates a simplified block diagram of the ASIC 28 of the smart battery system of the instant invention.

FIG. 3 is a general flow diagram illustrating the primary functional features of an algorithm and method for controlling a microprocessor embedded in the ASIC used in the instant invention.

FIG. 4 illustrates an initialization routine 10 for initializing the microprocessor and bus controller embedded in the ASIC.

FIGS. 5(a) and 5(b) are flow diagrams illustrating the IUT (current, voltage, and temperature) calculation program 200.

FIGS. 6(a) and 6(b) are flow diagrams illustrating the sequential processes 150 programmed in the microprocessor for calculating the current capacity of the rechargeable battery of the instant invention.

FIG. 6(c) illustrates the self-discharge program 300 for calculating the amount of battery self discharge.

FIGS. 6(d) and 6(e) illustrates the integration program 400 for calculating the amount of battery charge or discharge flowing into or out of its terminals.

FIGS. 7(a) through 7(c) are flow diagrams illustrating the sequential processes 500 programmed in the microprocessor for determining battery end conditions when the battery is in a capacity increasing state.

FIG. 7(d) illustrates a flow diagram of the learn number of cells program 700.

FIGS. 8(a) and 8(b) are logic flow diagrams illustrating the sequential processes 600 programmed in the microprocessor for determining battery end conditions when the battery is in a capacity decreasing state.

FIG. 9 illustrates a logic flow diagram of the handle request routine that is invoked when there is communication between the smart battery and the host computer or battery charger.

FIG. 10 illustrates a detailed logic flow diagram of the write block routine for writing data to the smart battery.

FIG. 11 illustrates a detailed logic flow diagram of the read block routine for reading data from the smart battery.

FIGS. 12(a) and 12(b) illustrate a flow diagram describing the logic steps invoked by the smart battery system when broadcasting an alarm condition to an external device.

FIG. 13 illustrates a logic flow diagram describing the steps invoked by the smart battery system when broadcasting a charge condition to a battery charger.

FIGS. 14(a) and 14(b) illustrates a logic flow diagram describing the steps invoked by the smart battery system when broadcasting a message.

FIG. 15 illustrates a logic flow diagram describing the steps invoked by the smart battery system to generate on LED display which indicates battery relative state of charge.

FIG. 16 illustrates a general schematic diagram of the A/D converter 60.

FIG. 17(a) illustrates the timing of the operating cycles under normal and sample mode operating conditions.

FIG. 17(b) illustrates the approximate time durations for the various measurements per operating cycle.

FIG. 18 illustrates a detailed schematic diagram of the comparator wake-up circuit 80.

FIG. 19(a) is a three-dimensional graphic representation of look up tables that depict predicted residual capacity values as a function of discharging current and temperature.

FIG. 19(b) is a three-dimensional graphic representation of look up tables that depict the amount of self-discharge current (vertical axis) as a function of relative battery state of charge and temperature.

FIG. 19(c) is a three-dimensional graphic representation of charge efficiency look-up tables showing charge efficiency factors as a function of relative state of charge, charging current, and temperature.

FIG. 20 illustrates two voltage versus time graphs, a and b, comparing calculated battery capacity characteristics at various discharging current rates for a six (6) cell battery pack.

The smart battery of the present invention is intended for use with an intelligent host device such as a portable computer, portable video camera or cellular telephone having a system management bus and a smart charger, or an intelligent host device having a system power manager that can receive and send data over a system management bus.

A representative example of such a system is illustrated in FIG. 1, wherein the smart battery 10 is connected to a power plane 12 to supply and receive electrical energy over the power plane, and a system management bus 14, which is a bi-directional modified I2C data bus (communication interface) that communicates with a host device 16 which may be a portable computer. The host device 16 may be powered by the smart battery 10, or by the system power supply 18 and a conventional AC source 20. A system power supply or power management system also communicates with a smart charger 22 which may be used to determine the rate and duration of charge sent to the smart battery by the power supply. Smart charger 22 also communicates with the system management bus 14, and may receive a temperature signal representative of battery cell temperature on a separate line feed 24. A detailed functional description of the system management bus 14 (bi-directional modified I2C data bus) can be found in the Intel.backslash.Duracell System Management Bus Specification, Rev 0.95, (April 1994).

The system power management system 18 may supply or draw power to/from the smart battery 10 over power plane 12, depending upon the state of charge in smart battery 10, and depending upon the presence or absence of power at AC source 20.

The smart charger 22 may periodically poll the smart battery 10 for charge characteristics, and adjust output to match a smart battery charge request. Optionally, and if selected by the user of the host device, the smart charger 22 can override the smart battery's charge rate request and charge the smart battery at a higher or quick charge rate. The user of the host device does not necessarily need to override the smart battery's request. As will be explained in greater detail below, the smart battery may periodically broadcast the desired charging current, or the smart charger 22 polls the smart battery for a charging current. The host or the charger need not comply with the smart battery's request and can provide a greater or lesser amount of power than requested.

The host device 16 may communicate with the smart battery over the system management bus 14 and request information from the battery for use in the system power management scheme, thereby providing the user of the host device with information about the battery's present state and capabilities. The host device 16 will also receive notice of critical events, including alarm conditions, remaining capacity below a user set threshold value, a remaining run time below a user set threshold value, or an end of discharge signal. The alarm conditions include but are not limited to overcharging, overtemperature, a remaining charge capacity below a predetermined or user set capacity, or, a run time below a predetermined or user set run time remaining.

As will be hereinafter explained in greater detail, the smart battery can report out an instaneous current value being drawn from the battery, current values averaged over predetermined time intervals, present temperature and present voltage.

The smart battery may also report out a number of battery status indicators, indicating whether or not the battery is charging or discharging, that charging is complete, or, that the battery is fully discharged.

In addition, it can provide calculated values including run time remaining at a present current usage, a run time remaining at an average current use, a run time remaining at optimal current use, and a predicted run time remaining at a host device selected current level (discharge rate).

The smart battery 10 also provides a set of predefined battery identification parameters which may include manufacturer data, cell chemistry, design capacity, design voltage, and a unique device identification number. The predefined battery identification parameters are available, for either the host device or the smart charger, to assist them in the selection of optimal usage and charge parameters for the smart battery.

The smart battery is also capable of recommending a desired charge current, reporting a time remaining to full charge, a battery capacity available at full charge, and the number of times the battery has been charged or discharged.

The smart battery at the present invention utilizes a hybrid integrated chip (IC) containing an embedded microprocessor and a novel analog to digital connector which receives analog signals from the battery and converts them to digital signals representative of battery voltage, current and temperature. The smart battery microprocessor then calculates actual charge parameters over time from these digital signals according to a predetermined algorithm in which CAP.sub.rem is the remaining capacity of the battery which is continuously assigned a new value to reflect adjustments for effective charge, discharge, and self discharge.

The charge delivered to the battery is measured, and adjusted by an efficiency factor which is a function of current, temperature, and relative state of charge. It should be mentioned that the remaining capacity, CAP.sub.rem, and the relative state of charge, SOC, represent the same thing (remaining battery capacity) and differ in that relative state of charge is indicated as a percentage of the last full charge capacity. The charge efficiency is a value determined as a function of the above variables and may be derived from a look up table, hereinafter described with respect to FIG. 19(c), or calculated from a formula which provides a stepwise approximation of charge efficiency behavior, depending upon current, temperature and state of charge. It is understood that the charge efficiency factor can be obtained from a response equation or interpolation between several different values stored in memory.

Likewise, the remaining battery capacity CAP.sub.rem is decremented by the measured discharge rate over time. A predictive model of residual capacities determines expected CAP.sub.rem for a present current and temperature. This predictive model may also estimate when the battery voltage will drop to a predetermined cut-off voltage of the present rate at discharge. This residual capacity model may be calculated from a formula or obtained from a look up table, which includes values of residual capacities as a function of discharge current and temperature.

Finally, CAP.sub.rem is also adjusted by subtracting self discharge. Self discharge is calculated as a function of temperature and state of charge, and is always subtracted from CAP.sub.rem, regardless of whether the battery is discharging or being charged. Self discharge may be derived from a look up table of empirical models of identical cell chemistry that predict self discharge as a function of temperature and state of charge, or may be calculated by the microprocessor.

As will be hereinafter explained in greater detail, CAP.sub.FC is a learned value which is self correcting because of reset logic incorporated in the capacity algorithm. The capacity algorithm takes actions on four types of end of charge (EOC) signals, including a negative voltage slope at a full charge voltage, a temperature rise that exceeds a predetermined rate, or a calculated state of charge that is equivalent to a value of 100% to 150% of the previous CAP.sub.FC value, if an optimal charging current has been used, or a high temperature limit value. When one of the first three of the above four types of conditions is encountered, the reset logic resets CAP.sub.rem to the previous CAP.sub.FC value, sets a fully charged status flag, and, signals the host device and charger to terminate charge. If the high temperature limit is reached, only a signal to terminate charge is invoked.

The charge algorithm terminates its integration of the present dischage state when it reacts to an end of discharge (EOD) signal between 0.9 volts/cell and 1.1 volts/cell and preferably 1.02 volts per cell. At that point it resets CAP.sub.rem to a new learned value of residual capacity, as determined from the integration of the discharge current, as a function of discharge current and temperature.

As will be hereinafter explained in greater detail, the reset logic will reset CAP.sub.FC as a function of which EOD signal was acted on. Thus a new CAP.sub.FC value for the smart battery's actual capacity is learned after each full discharge cycle, as a function of the last fully integrated battery discharge cycle. The smart battery 10 of the present invention is thus able to self correct CAP.sub.FC within one full cycle to readjust its capacity at each EOC and EOD, and effectively relearn full battery capacity within a single cycle, even if all prior battery history has been extinguished by virtue of a catastrophic memory failure. The smart battery of the present invention is therefore able to accurately predict actual capacity, and typically is able to correctly predict the remaining run time to empty within a few minutes for a 2400 maH battery.

Smart battery 10 of the present invention is more fully illustrated in FIG. 2(a) which is a simplified block diagram of the smart battery, an advanced design multi-pin connector, and a battery module 28 which includes a pinout diagram of the hybrid ASIC 32 used in the present invention. As illustrated in FIG. 2(a), the smart battery 10 includes a plurality of rechargeable cells generally indicated at 26 which may be Nickel Metal Hydride (NiMH) or Nickel Cadmium (NiCad) cells.

For the purposes of an illustrative but not limiting example, in the following specification, 6 NiMH cells having a nominal 2400 maH capacity, will be assumed. Such an arrangement of cells is particularly appropriate for powering a portable computer.

A suitable advanced design multi-pin battery connector 30 is used to connect the smart battery to a host device 16 or power supply 18, as previously described with respect to FIG. 1. The multi-pin connector 30 includes a positive power supply terminal 31 which is connected to the positive terminal of the first cell, and a negative power supply terminal 33 which is connected to the negative terminal of the last cell. A plurality of rechargeable cells may be connected in series therebetween as illustrated in FIG. 2(a).

The smart battery module 28 includes a hybrid IC 32 containing a microprocessor and a plurality of sensor means for generating analog signals representative of battery voltage, current and temperature. The module also includes a series of four (4) LEDS 34 driven by an LED drive circuit 53 and a switch 35 which may be manually actuated by an end user to determine the state of charge in the battery even when the battery module has been removed from the host device 16. The LEDS 34 may be used to represent a relative state of charge (SOC) in a logic scheme as follows. If the state of charge is greater than 75% (or less than 100%) then all 4 LEDS are illuminated. If the SOC is from 50% to 75%, then 3 LEDS are illuminated; if SOC is from 25% to 50%, then 2 LEDS are illuminated; if SOC is from 10% to 25%, then 1 LED is illuminated, and if SOC is less than 10%, a single LED is flashing. As mentioned above, relative SOC is remaining capacity relative to last full capacity.

As shown in FIGS. 2(a) and 2(b), the hybrid ASIC 32 also includes an external crystal 36 operating at a fixed frequency which is used as a time base for integration of battery current over time, and to ensure stable start up after a prolonged standby period when power is reapplied to the smart battery 10. The smart battery of the present invention utilizes two separate oscillators, a low power RC oscillator formed within the hybrid IC 32 and used as an operating clock for the hybrid IC and the A/D converter 60 therein, and, the external crystal 36. As will be hereinafter described in greater detail, the external crystal 36 is used to restart the measurement period after each predetermined interval to provide for accurate measurements and integration of battery conditions, regardless of battery temperature, which can adversely affect the accuracy of the internal oscillator. The frequency value of external crystal 36 may range from 10 kHz to 66 kHz, preferably at 32 kHz, and the frequency value of oscillator 48 may range from 450 kHz to 460 kHz.

The hybrid IC 32 includes a MIKRON low cost, high performance, CMOS 8 bit microcontroller (.mu.P) 50 with an advanced RISC architecture. A reduced set of 32 instructions and a Harvard architecture scheme achieves a high level of performance with minimal power drain.

The hybrid IC 32 also includes a plurality of analog circuits which are used, in combination with external analog sensors, to generate digital signals representive of battery voltage, current and temperature as will be hereinafter explained.

For example, as shown in FIG. 2(a), battery voltage is obtained from a voltage divider circuit which includes R1 and R2 which are internally switched by a NMOS transistor within the hybrid IC 32 to provide voltage measurement during a small portion of each measurement interval, thereby minimizing current drain on the battery cells 26.

The measurement of battery temperature is accomplished with an NTC-thermistor illustrated as R.sub.NTC1 in FIG. 2(a) which is a thermistor, which varies resistance as its temperature varies. A resistor R3 is connected in series to form a voltage divider circuit between V.sub.ASS, (negative analog power supply voltage) V.sub.TEMP, (the temperature voltage input) and V.sub.REFT, which is a reference voltage applied to the thermistor/resistor string by the hybrid ASIC 32 at pin V.sub.REFT. The temperature voltage input is measured at V.sub.TEMP according to the following formula: ##EQU1## wherein the NTC1 value may be 10 kohms at 25.degree. C. and varies with temperature. If desired, a look-up table with a plurality of temperature values and a plurality of V.sub.TEMP values may be defined to calculate the battery temperature, and between these values, the temperature is linearly interpolated by the microprocessor within IC 32.

The measurement of battery current is measured through a shunt resistor, illustrated in FIG. 2(a) as R.sub.shunt, that is connected in series with the battery cells and negative terminal 33 of cell pack 26. The shunt resistor is of small value, but may range anywhere from 1 mohm to 200 mohms depending on the number of cells and expected usage of the battery. The voltage drop across the shunt is sensed between V.sub.SHUNT+, the shunt resistor positive input pin of ASIC 32, and V.sub.ASS, the negative analog power supply voltage.

As shown in FIG. 2(b), whenever the analog signals representing battery voltage, current, and temperature are obtained, they are input into an ASIC multiplexor or switching network 55 which enables only one analog signal at a time to be input to the A/D converter 60 for digital conversion.

A general schematic diagram of the A/D converter 60 is shown in FIG. 16. In the preferred embodiment, the A/D converter 60 is a bipolar, high resolution, incremental delta sigma converter and consists of three parts: a bandgap reference circuit 62 which provides a preset analog voltage which is used as an analog ground for the A/D; a voltage divider network 64 which divides the present voltage to the analog voltages which are used as the full-scale voltage for the A/D; and, a delta sigma circuit 66 for converting the analog signal to a digital word output at line 69. A/D control circuit 68 having a clock input from the IC oscillator, provides the control for the delta sigma converter which has a different degree of resolution depending on the type of measurement. For instance, in one embodiment of the invention, the A/D converter was configured as having a resolution of 13 bits and a conversion time ranging from 300 to 400 msec for current measurements, and, was configured as having a resolution of 10 bits and a conversion time ranging from 30 to 60 msec for voltage and temperature measurements. The timing diagram for the voltage, current, and temperature measurements in each operating cycle is illustrated as 58a in the timing of operating cycles diagram of FIG. 17(a), as explained below.

In one embodiment of the invention, the voltage divider circuit 64 of the A/D converter divides the preset bandgap reference voltage into the following full scale voltages: a 150 mV signal used as the full scale voltage for the battery current measurement; 150 mV, 250 mV, or 350 mV signals used as the full-scale voltage for the battery pack voltage measurement and dependent upon the number of battery cells; and 150 mV used as the full-scale voltage for the battery temperature measurement. These values are illustrative and may vary as battery design varies.

The multi-pin connector 30 includes two pins for the system management bus interface 75, which include a serial clock I/O line 38 and a bidirectional serial data I/O line 40. These lines are connected to the SMBCLK and SMBD data pins, respectively, of the hybrid IC 32. As explained generally above, and, in greater detail below, the smart battery module 28 communicates with the host device 16 and the smart charger 22 over the system management bus and data line 40 to communicate both stored battery parameters and calculated battery parameters.

The smart battery 10 also includes a separate thermistor R.sub.NTC2 which is connected across the negative terminal of multi-pin connector 30 and a temperature or thermistor line 42. Thermistor R.sub.NTC2 may be used independently by the smart charger 22 to determine battery temperature, in a manner similar to that previously described with respect to R.sub.NTC1.

A positive digital power supply voltage is obtained from the plurality of rechargeable battery cells 44, and supplied to the hybrid IC through pin V.sub.DD as the positive power supply voltage for the chip. It should be understood that the supply voltage for the hybrid IC does not necessarily have to be obtained at the battery midpoint 46, but should be obtained at a point from the battery cells in order to receive a voltage of approximately 3 to 4.8 volts, i.e., the equivalent voltage of three (3) cells. As will be hereinafter explained in greater detail, the use of a battery midpoint for the positive voltage supply enables the hybrid IC to remain powered even when the battery is accidently shorted and removed from terminals 31-33, and enables the A/D converter 60 to determine whether the battery is discharging or being charged as will hereinafter be explained in greater detail. Although not shown in FIG. 2(a), suitable fuse elements (not shown) and positive temperature coefficient (PTC) elements (not shown) are provided in series with the battery pack cells to protect the battery from very high current and excessive temperatures caused by a temporary short circuit across the battery terminals or other thermal event.

As shown in FIG. 2(b), the hybrid IC 32 further includes RAM memory 65 which can store up to 128 8-bit words for communication of calculated battery parameters, and a ROM memory 67 for storing look-up table values utilized in the battery capacity calculation algorithm (explained in detail below). The exact amount of RAM, ROM, and program ROM memory is a design choice, and these values change as the ratio between calculated and preset parameters vary.

As shown in FIG. 2(a), the addition of capacitor C4 acts as a buffer to maintain the integrity of the RAM memory contents in the case of a battery short-circuit or temporary power loss. Preferably, the capacitor C4 is connected to the negative analog voltage supply terminal, and its value is chosen to ensure that a source of supply voltage is supplied to the embedded memory (RAM) for a time dependent upon the RAM leakage current. In the preferred embodiment, the power to RAM memory is unlatched if a short circuit conditioned is sensed, and the value of capacitor C4 is 330 nF which provides a source voltage to the RAM for a period of time necessary for the PTC element (not shown) to ramp to a high resistance value. The PTC element will create a high impedance between battery terminals when a short circuit across the battery pack terminals creates a high circuit drain.

The hybrid IC 32 further includes up to 4 kbytes of additional ROM memory 70 for storing the various algorithms, subroutines, manufacturer data, and data constants utilized by the smart battery module for calculating the battery capacity, sending messages such as alarms and battery charger control commands etc., and handling message requests from external devices. Each of the algorithms for accomplishing these functions will be explained in further detail below.

As shown in FIG. 3, the battery operating system 10' will first perform an initialization routine 100 that is initiated upon system power up, enabled by a power ON signal/reset impulse signal 11, or, enabled by a wakeup from STANDBY signal 13 which is generated after the microprocessor has determined that it should exit the standby mode. As shown in FIG. 2(b), the ASIC 32 is provided with a power-on reset circuit 85 which generates a reset impulse signal 11 every time the power supply voltage is applied to the ASIC. The threshold of this circuit is between 1.2 V and 1.6 V depending upon the type of transistors used in the circuit (not shown).

After a power on/reset signal 11 is received, or, after the standby mode is exited, the system is placed in a sleep mode 23 (FIG. 3) until it is triggered by trigger signal 17 generated by the external oscillator 36 which provides the trigger for the system operations (capacity calculation) every 500 msec, or, is awakened by a bus request signal 15 as will be explained in further detail below. In the battery "sleep" mode, the microprocessor is in an idle state until the operating cycle trigger 17 or external bus request signal 15 is received.

Initialization of algorithm variables

To prevent exceptions in the capacity calculations to be described hereinbelow, it is imperative that variables do not have undefined values. This enables the algorithm to work in a catastrophic emergency mode in the event that all RAM memory has been lost. The default values of critical variables may then be substituted by correct values when the battery system is reformatted, as for example, at a battery service station using the original manufacturer's data.

In the initialization routine 100, shown in FIG. 4, all values to be stored in the system RAM are cleared and all system default values are assigned. Preferably, many of the default values are constant values and are necessary in case of an emergency situation wherein all RAM memory has been lost.

As shown in FIG. 4, step 104 of initialization routine looks for a value that has been burned into the system at manufacture. The variable "checksum" is the byte sum from the calibration parameters, cf.sub.-- curr, cf.sub.-- temp, co.sub.-- curr, co.sub.-- temp, (explained below) and the kind of display (kod). It is written into battery memory at the time of manufacture and calculated when the calibration data is sent to the battery. This "checksum" value is first-compared to a value of zero, as indicated at step 102 in FIG. 4. If it is equal to zero, then the default values of the critical parameters stored in RAM are cleared, and new ones are assigned as indicated at step 108.

On power-on-reset as well as on a wakeup from the STANDBY mode of the chip (explained below), the program is started at an initial memory address. The variable "checks" which adds all three current calibration factors and the number of cells is calculated at step 104 and compared to the initial register "checksum" value at step 106. If "checksum" has not been cleared, i.e., is not zero (step 102), and, is determined as equal to the calculated "checks" value, it is assumed that the RAM memory is valid and the emergency mode (which uses ROM defaults) will not be activated and the capacity calculation will be continued without resetting the RelativeStateOfCharge "SOC" value (explained below) or the FullChargeCapacity "full.sub.-- cap" value (explained below). A normal example of such an instance is when the chip switches into the STANDBY mode at low battery voltage and then back into the ON mode when the battery is to be recharged.

At step 106, if the checksum test is negative, i.e., the "checksum" value does not equal to the calculated "checks" value, the .mu.P will first clear all RAM banks completely, as indicated at step 108. A consequence of this is that an internally generated CALIBRATED flag will be cleared and the number of cells of the battery pack has to be learned, a process to be explained in greater detail below. Next, the default values as described below are transferred from ROM to RAM as indicated at step 110 in FIG. 4. Included at step 110 will be an initialization of FullChargeCapacity "full.sub.-- cap", RelativeStateOfCharge "SOC" and the RemainingCapacity "Itf" values, as well as state and other variables to ensure a proper start of the capacity calculation. Then, the program resets all system timers such as the calculation of voltage, temperature and selfdischarge timers. The program then passes out of the initialization routine at step 116, and the capacity calculation is initiated at each trigger signal 17 which is delivered every 500 msec by the external 32 kHz crystal 36. Thus, in the initialization routine, all the above-described steps are executed at the virginal start of the system, or after a power-on-reset, in which memory was lost during the STANDBY mode.

As explained above, the default values are necessary to ensure that upon a power-on/reset, the rechargeable battery capacity calculation (explained below) may be executed. The preferable nominal default values for the critical parameters used for the capacity calculation algorithm 151 are set forth as follows:

The DesignCapacity (theoretical or nominal capacity, hereinafter "nom.sub.-- cap") should be in the range of 500 to 10,000 mAh. For this range the capacity calculation is guaranteed to be valid. Nom.sub.-- cap may range between 1700 maH to 2400 mAH, but, after a memory loss, the capacity calculation algorithm defaults to a preferred value of 2000 mAh and the new capacity is relearned from that level; the default value of the number of battery cells in the rechargeable battery pack is 6 cells, however, this value may be changed depending upon the actual configuration of the battery pack; N.sub.-- DT.sub.-- T and N.sub.-- DT.sub.-- U values represent the number of program operating cycles that are counted between temperature and voltage changes that are used in the capacity calculation algorithm. N.sub.-- DT.sub.-- T, the time interval for the dT/dt (temperature slope) detection, to be explained below, is defaulted as 20 sec., but this value may range from 10 to 50 sec. N.sub.-- DT.sub.-- U, the time interval for the dU/dt (voltage slope) detection, to be explained below, is defaulted as 120 sec., but this value may range from 100 to 400 sec. The cf.sub.-- curr, and cf.sub.-- temp are also defaulted and these values specify calibration factors for current and for the temperature look-up tables, respectively. The co.sub.-- curr is a default offset value for current calibration and co.sub.-- temp is a default offset value used for the temperature measurement. These values may change depending upon the specific battery design. The AL.sub.-- REM.sub.-- CAP value represents the remaining capacity alarm triggering value and may range from 50 mAh to 500 mAh. Preferably, AL.sub.-- REM.sub.-- CAP has a default value (AL.sub.-- REM.sub.-- CAP.sub.-- DEF) of 200 mAh. An alarm condition exists when the remaining capacity is below this value (without taking into account the remaining capacity after EDV due to current and temperature (i.e., the residual capacity correction)). The AL.sub.-- REM.sub.-- TIME value represents the estimated remaining time at the present discharge rate and may range from 1.0 min. to 20 min. Preferably, AL.sub.-- REM.sub.-- TIME has a default value (AL.sub.-- REM.sub.-- TIME.sub.-- DEF) of 10 minutes. This alarm condition exists while the calculated remaining time to voltage breakdown (EDV), based on the minute average current (discussed below), is below the value of AL.sub.-- REM.sub.-- TIME and will automatically be disabled when the battery is in the charging mode. The AL.sub.-- DTEMP value represents the dT/dt alarm trigger condition and may range from 1.degree. K./min. to 5.degree. K./min. Preferably, AL.sub.-- DTEMP has a default value (AL.sub.-- DTEMP.sub.-- DEF) of 2.degree. K./minute. This alarm condition will exist when the battery detects that the rate of its internal thermal rise (dT/dt) is greater than the AL.sub.-- DTEMP value. The AL.sub.-- HI.sub.-- TEMP value represents the high temperature alarm trigger and may range from 310.degree. K. to 345.degree. K. Preferably, AL.sub.-- HI.sub.-- TEMP has a default value (AL.sub.-- HI.sub.-- TEMP.sub.-- DEF) of 328.degree. K. Additionally, when the capacity calculation is started by power-on-reset, the FullChargeCapacity, ("full.sub.-- cap" represents the learned full charge capacity of the battery), will be initialized to the DesignCapacity (nom.sub.-- cap); the RemainingCapacity ("Itf") to 1/8 of the full.sub.-- cap; and, the RelativeStateOfCharge ("soc") to 12.5% and the battery state to capacity decreasing, and, specifically, to selfdischarging mode. The alarm timer N.sub.-- ALARM is set at 10 seconds and this is the amount of time that an alarm condition will be broadcast between a host device and/or a battery charger as will be explained in further detail below. It should be understood that these values are typical values for a NiMH battery intended for use in a portable computer. Other types of battery chemistry, or portable devices, may call for a different set of default values.

After the system is initialized at step 100, the battery will enter into a sleep mode 23 where it will either awake upon a bus-request signal 15 or awake upon the external crystal trigger signal 17 every 500 msec. If the battery is awaked by a bus request signal 15 as determined at step 21, then the battery will handle the request by the handle request routine indicated at step 25 where it will thereafter exit into the sleep mode. The routine for handling the requests 25 will be explained in further detail below.

If the system is triggered by the normal external crystal trigger signal 17, and there are no bus requests, then the program disables the bus requests (37 msec before the trigger signal) and enables the A/D converter to begin the current, voltage, and temperature measurements for the current operating cycle as shown at step 130 in FIG. 3. A "getvalues" status flag is then checked at step 139 to determine whether A/D conversions of the raw current, voltage, and temperature measurement values are to be performed. When this flag is set high (logic level=1), then the raw current, voltage, and temperature values of the rechargeable battery are obtained for the current trigger cycle as shown at step 140. These raw A/D current, voltage and temperature values are built into register 61, as shown in FIG. 2(b), for subsequent storage in RAM as I, U, or T. If the "getvalues" flag is low (logic level=0), then no raw current, voltage, and temperature measurements will be obtained for the present cycle, and the getvalues flag will toggle high (logic 1) at step 148 and the process will continue as shown in FIG. 3.

After new current, voltage, and temperature values are obtained (step 140), the A/D measurements ready flag is set high (logic level=1) at step 141, and a check is made at step 142 to determine whether the system is in a sample mode. Thus, at step 142, if the absolute value of the raw current, .vertline.I.vertline., is determined to be below a threshold value of 10 mA, then the battery system will operate at half power or half the sample rate depending upon the status of the sample mode flag. Thus, at step 143 in FIG. 3, a determination is made as to whether the sample mode flag is low (i.e., logic 0) or high (logic 1). If the sample mode flag is low, then the sample mode flag will toggle to a high level at step 144, and the system is placed in a sample mode and the process proceeds at step 149 to initiate the A/D conversion. If the sample mode flag is already high (from the previous cycle), then the "getvalues" flag is set equal to zero at step 146, and the A/D converter is disabled at step 147. The A/D conversion will not occur (to save power) and the algorithm proceeds to the capacity calculation (step 151). The "getvalues" flag is always set low in the sample mode. The status of this flag ensures that an A/D conversion will be skipped, and, as a consequence, no valid data will be available and the capacity calculations at step 151.

If the raw current, .vertline.I.vertline., is determined at step 142 to be above the 10 mA threshold, then the battery system will exit the sample mode (and the sample mode flag is set at logic 0) at step 145, and the A/D conversion of the raw current, voltage, and temperature values will be performed at step 149. At step 150, a determination is made as to whether the A/D measurement ready flag is high (logic 1) indicating that valid raw battery parameter data has been received. If it is set high, then the capacity calculation and attendant battery characteristic conversions (voltage, current, and temperature) will be performed. If the A/D measurement ready flag is low (logic 0), then the capacity calculation is not performed in the current cycle, and the process proceeds to step 158 where the bus request line for message transfer is enabled and the hybrid IC is placed in the sleep mode at step 23. The oscillator trigger 17 continues to wake up the algorithm every 500 msec, however, when the current is less than 10 mA, the A/D conversions and the capacity calculations are only made every other cycle.

FIG. 17(a) illustrates the timing of the operating cycles under normal mode operating conditions 57a as compared when the system operates under sample mode conditions 57b explained below. As shown in FIG. 17(a) and, as mentioned above, the 32 kHz external crystal delivers the trigger signal 17 every 500 msec to initiate the raw voltage, current, and temperature measurements, indicated as 58a. Also initiated is the capacity calculation 160 which utilizes the current, voltage, and temperature measurements of the previous operating cycle. As mentioned above, when the raw current value obtained is determined to be below a threshold value of 10 mA, the battery system will operate at half power, and no measurements will be taken during the next 500 msec operating cycle as indicated as 58b in FIG. 17(a). However, measurements are taken one second later at the next operating cycle as indicated as 58c. When the raw current value obtained is determined to be above a threshold value of 10 mA, the battery system will resume normal mode operation and during the next and subsequent operating cycles, the capacity calculation and attendant battery characteristic measurements (voltage current, and temperature) will be taken. FIG. 17(b) illustrates the approximate time durations for the various measurements. As a matter of design choice, the capacity calculation 160 is performed in approximately 71 msec for each operating cycle. Thereafter, the alarm control subroutine 152 will be performed for a duration of approximately 29 msec and the charger control subroutine 154 will be performed for a duration of approximately 2 msec if the battery determines these operations are to be performed (see FIG. 3). The LED display routine 156 may be performed if it is requested by a user and the LED display control functions will take place for approximately 23 msec as shown in FIG. 17(b). It should be understood that the aforementioned performance times for the various routines may vary due to the accuracy of the internal 455 kHz oscillator, which may vary with temperature. Each of the alarm control subroutine 152, charger control subroutine 154 and LED display subroutine 156 will be explained in further detail below. Since the system management bus request line is inactive during the capacity calculation, alarm control, charger control, and LED display routines, the microprocessor will be unable to receive requests from a host device or battery charger as indicated for the time duration 158 for each operating cycle shown in FIG. 17(a). Therefore, in each operating cycle, after the capacity calculation has been performed, the System management bus request line is enabled for the remaining time of the 500 ms cycle, as indicated in FIG. 17(b), so that it may respond to a request from a host device or charger. Concurrently, the battery places itself in the sleep mode 20 whereupon it will be awakened for the next cycle upon receipt of the system trigger signal 17, or, be awoke by a bus request signal 15 as shown in FIG. 3. For a remaining 37 msec of each operating cycle, the bus request is again disabled as shown for the time duration 158 prior to the next trigger signal 17. It should be mentioned that each system trigger signal 17 initiates the start of the internal clock 48 generating the 455 kHz signal for controlling the hybrid IC, microprocessor, A/D converter, etc.

Algorithm for calculating battery capacity

The purpose of the capacity calculation is to continuously monitor the capacity of the rechargeable battery in accordance to the formula indicated by equation (1) as follows:

where CAP.sub.rem, is referred to hereinbelow as "Itf" and indicates the remaining capacity in the battery at any given time expressed as mAh (milliamperehours); the .SIGMA..epsilon..sub.c I.sub.c .DELTA.t.sub.c term represents the sum of the incremental increases in capacity as the battery is being charged and takes into account a charge efficiency factor .epsilon..sub.c accessed preferably from look-up table values to be explained in further detail below with respect to FIG. 19(c), or, alternatively, may be obtained from a response equation or by interpolating between several points stored in memory; a .SIGMA.I.sub.d .DELTA.t.sub.d term which represents the sum of the continuous decrease in battery capacity due to discharge associated with the battery's usage; and a .SIGMA.I.sub.s .DELTA.t.sub.s term which represents the predicted and measurable amount of self-discharge based upon self-discharging effects associated with the battery's chemistry and is a function of the battery state of charge and temperature. By knowing the RemainingCapacity, Itf, at all times, it is possible to provide battery parameter information useable by a host computer (PC) or smart battery charger to ensure safe and reliable battery use and to ensure prolonged battery life.

FIGS. 6(a) through 6(b) illustrate the capacity calculation routine performed for the rechargeable battery pack at each trigger cycle. As mentioned briefly above, the period of the operating cycles is 500 ms and in each cycle the capacity calculation is started. As shown in FIG. 17(a), it takes approximately 58 ms to perform the calculation each cycle. In parallel, the current, voltage and temperature measurements are running except when in the "sample" mode where the measurements are taken once every second. The sample mode is designed to save power consumption (i.e., the battery operates at half-power) and switches on and off controlled by the amount of detected current. For example, when the current falls below 10 mA, the "sample" mode is enabled and less frequent measurements are made.

Normally the temperature, voltage and current are measured and updated once per cycle. The current is measured with an integrating method (explained in detail below), which recognizes its changes during the conversion time. All output values taken from SMBus requests and capacity calculation are one period delayed. The A/D measurements are controlled by an on-chip oscillator at nominal 455 kHz and the operating cycles--responsible for the integration time--by the precise 32 kHz oscillator. The lower accuracy of the absolute frequency value of the on-chip oscillator has no influence on the accuracy of the measurement.

As shown in FIG. 6(a), step 200, the first step of the capacity calculation, the IUT Calculation routine 200 is performed to first convert the raw analog/digital converter output data from register 61 (FIG. 2(b)) into values having appropriate units useful for the capacity calculation algorithm. In FIG. 5(a), at step 205, the raw A/D Current measurement, I.sub.-- raw, is scaled and converted to the actual current value "I" in units of milliamps. At step 210, the raw A/D pack voltage measurement, U.sub.-- raw, is scaled and converted to the actual battery pack voltage value "U" in units of millivolts. Next, as indicated at step 212, the .mu.P checks the battery pack voltage to determine whether or not any individual cell of the battery pack has an output voltage less than 0.9 V. If a cell is detected as outputting a voltage less than 0.9 volts, then the battery pack is placed in a Standby mode, as indicated at step 214. The following actions take place when the battery state changes between an ON and STANDBY mode: The .mu.P proceeds to switch off the A/D converter and 455 kHz oscillator and sets a bit flag to tell the hardware to start a special voltage control logic and set itself for sleep mode. When the control logic wake-up comparator circuit 80 as shown in FIG. 2(b), detects that the V.sub.DD of the ASIC has increased above 3.33 V (1.11 V/cell for a three cell battery pack), the .mu.P will awake, enabling the A/D converter again to take measurements, and continues with the capacity calculation with an initialization which depends from the checksum test as described above.

As shown in FIG. 2(b), the wake-up comparator circuit 80 is activated when the battery has entered the standby mode. As mentioned previously, when in the standby mode, the .mu.P 50, A/D converter 60, and the 455 kHz on-chip oscillator 48 are turned off to save current. Only the 32 kHz oscillator is running to give a sampling period of 500 msec to a comparator 76, which compares the positive supply voltage V.sub.DD with the A/D bandgap reference voltage of 1.25 V. When the V.sub.DD of ASIC 32 has increased beyond the 3.33 V (1.11 V/cell for a three cell battery pack), then the comparator 76 will switch on the .mu.P 50, A/D converter 60, and the 455 kHz on-chip oscillator 48. A detailed schematic of the comparator circuit 80 is shown in FIG. 18. As shown in FIG. 18, the wake-up comparator circuit 80 comprises a voltage divider comprising resistors R4 and R5 which are tied to the V.sub.DD ASIC power supply and ground to provide a pack voltage signal 82 to a first input of a comparator. The pack voltage signal 82 is compared with the predetermined bandgap reference voltage signal 83 and this value may be changed depending upon the battery pack design. For a three cell battery pack, the bandgap reference voltage 83 is 1.25 volts. When V.sub.DD ASIC power is low, the comparator output signal is high. When VDD rises above the reference voltage 83, the wake-up signal 13 goes low, thus enabling normal system operation. During the sleep mode, the comparator is enabled by enable line 15a. Additionally, the power input to the comparator 76 is tied to a low current drain NMOS transistor 90 to enable continued comparator circuit sensing without appreciable current loss.

As long as the cell is detected as outputting a voltage greater than 0.9 volts, the capacity calculation continues and, at step 215, the raw A/D pack temperature measurement, T.sub.-- raw, is converted to the actual battery pack temperature in units of degrees Kelvin. This temperature value is further scaled with the help of manufacturer provided look-up tables (not shown), at step 220, to take into account thermistor scaling values, and a final current temperature value of "T" is obtained. At step 222, the condition of the battery is checked to determine if an over temperature condition exists, i.e., if T.gtoreq.AL.sub.-- HI.sub.-- TEMP. An over temperature condition exists at a temperature 328.degree. K. or greater and, when detected, a temperature alarm condition flag, HI.sub.-- TEMP.sub.-- ALARM, is set as indicated at step 224. Next, at step 227, the state of the battery pack is checked to determine if capacity is increasing. If capacity is increasing, and the over temperature condition exists (HI.sub.-- TEMP.sub.-- ALARM set), then the TERMINATE.sub.-- CHARGE.sub.-- ALARM flag is set at step 228. This flag indicates that one or more of the battery's charging parameters are out of range and will be reset when the particular parameter falls back into its allowable range. If it is determined at step 222 that an over temperature condition does not exist, then the temperature alarm condition flag, HI.sub.-- TEMP.sub.-- ALARM, is cleared at step 226, as shown in FIG. 5(a) and the process continues at step 230. Whether an over temperature alarm condition exists or not, a determination is made at step 230 to determine if the current scaled temperature value T is greater than a maximum temperature value "Tmax", indicating the highest temperature reached for that particular battery. If the current temperature value is the highest value reached in the life of the battery, then, at step 235, the variable Tmax is assigned the current scaled temperature value and this data is stored in RAM and may subsequently be used by the manufacturer upon the battery's return for quality control purposes after the battery has reached the end of its useful life.

At this point, it should be mentioned that when the rate change in voltage or temperature taken between successive measurements is at a certain gradient, an end of charge condition may exist (if the capacity is increasing). Thus, as shown in FIG. 5(b), steps 240 through 249, the change in temperature calculation is performed, and at steps 250 through 255, a change in voltage calculation is performed.

As indicated at step 240 the timer (loop counter) for the change in temperature dT/dt calculation is decremented. Preferably, the timer for the change in temperature calculation times out every 20 seconds, and this is the frequency at which the change in temperature (dT) calculation is made. This value is chosen by design, and may range anywhere from 10 sec to 120 sec. Thus, as indicated at step 242 a determination is made as to whether the dT timer has timed out, i.e., if 20 sec. has passed. If not, the program proceeds to the voltage change dV calculation at step 250. If the timer has timed out, then, as indicated at step 245, the change in temperature dT calculation is made, which is the difference between the current temperature value T and the previous temperature value determined 20 seconds previously. Included in this step is to reassign the next old value of T as the current T value. Finally, the 20 second dT timer is reset. After the dT calculation is performed, a determination is made as to whether the amount of internal temperature change exceeds the allowable rate, i.e., whether the AL.sub.-- DTEMP alarm condition exists, as shown at step 247 in FIG. 5(b). A temperature change of approximately 2.degree. K./min or greater indicates an AL.sub.-- DTEMP alarm condition and, when detected, an alarm condition flag, DTEMP.sub.-- ALARM, is set as indicated at step 249. If the amount of internal temperature change does not exceed the allowable rate, then the temperature change alarm condition flag, DTEMP.sub.-- ALARM, is cleared, as indicated at step 248. Regardless, the process continues at step 250 in FIG. 5(b).

As indicated at step 250 the timer (loop counter) for the change in voltage dU/dt calculation is decremented. Preferably, the timer for the change in voltage calculation times out every 255 seconds, and this is the frequency at which the change in voltage (dU) calculation is made. Thus, as indicated at step 252 a determination is made as to whether the dU timer has timed out, i.e., if 255 sec. has passed. If not, the program proceeds to step 260 to determine whether an End of Discharge voltage condition has been reached. If the timer has timed out, then, as indicated at step 255, the change in voltage dU calculation is made, which is the difference between the current voltage value U and the previous voltage value determined 255 seconds previously. Included in step 255 is to reassign the next old value of U as the current U value. Finally, the 255 second dU timer is reset. After the dU calculation is performed, a determination is made at step 260 as to whether the capacity is decreasing, and, as to whether the present voltage U is less than the end of discharge voltage (EDV) limit (typically 0.9 V/cell), indicating that an end of discharge condition EOD.sub.-- U exists. Thus, the present voltage value U is compared to the preset end of discharge voltage (Uempty) to determine if it is less than this voltage. If an End of Discharge condition for voltage exists, then an EOD.sub.-- U flag is set at step 262 and a Terminate.sub.-- Discharge.sub.-- Alarm flag is set indicating that the battery has supplied all the charge it could without being damaged. If an End of Discharge condition does not exist, then the EOD.sub.-- U flag and the Terminate.sub.-- Discharge.sub.-- Alarm flag is cleared at step 264. Additionally, at step 264, the capacity reset flag is disabled. The IUT.sub.-- Calculation procedure 200 is then exited and the capacity calculation continues at step 165 in FIG. 6(a).

At step 165 of the capacity calculation routine 151, a calculation of the rolling minute average current is performed utilizing the recent previous current (I) measurements. Then, at step 170 of FIG. 6(a), a determination is made as to whether the present current (I) value is less than or equal to the selfdischarge current I.sub.-- SELFD, which, in the preferred embodiment, is 3.0 milliamps but may range anywhere from 2.0 ma to 10.0 ma and represents the limit for a mode and battery state recognition. If the present current (I) value is less than or equal to the selfdischarge current then the state of the battery is determined to be capacity decreasing without any external drain. Consequently, a selfdischarge flag bit is set at step 175. If the present current (I) value is greater than the selfdischarge current (3.0 mA), then the battery selfdischarge flag bit is cleared at step 172. The battery however, may still be in a capacity increasing or capacity decreasing state even though the battery self-discharge current is always calculated, and the direction of current is established at step 178 in FIG. 6(a) to determine the present state of the battery. If the current (I) is determined to be a positive value, then the state of the battery is capacity increasing (hereinafter CI) and a capacity increasing flag is set at step 180. If the current is determined to be a negative value, then the state of the battery is capacity decreasing (hereinafter CD) and a capacity decreasing flag is set at step 182. If it is determined that the capacity is decreasing, then a determination is made at step 184 as to whether the end of discharge voltage (plus hysteresis) EOD.sub.-- UH flag has been set. If, at step 184, the EOD.sub.-- UH flag has been set indicating that the battery pack end of discharge voltage has been reached, or, if the battery self discharge flag has been set (as determined at step 175), or, if capacity is increasing, then a determination is made at step 189 as to whether the capacity reset flag has been set. If it has been set, then, at step 190, the remaining capacity (Itf) at the EOD voltage condition is reset to a predicted Residual Capacity "pd" value obtained from look up table depicted in Figure 19(a). Additionally, at step 190, the error register is reset to zero and the capacity reset flag is cleared. The program then proceeds to the selfdischarge calculation and current integration procedures. If, at step 184, the EOD.sub.-- UH flag has been determined not to have been set, or, if the capacity reset flag had not been set as determined at step 189, then the process proceeds at step 192 in FIG. 6(b).

At step 192 of FIG. 6(b), a determination is made as to whether the state of the battery has changed, i.e., whether the battery has changed from a capacity increasing (CI) state to a capacity decreasing (CD) state, or vice versa. To avoid the instance of false battery cycle counting (to be explained in detail below) or the inaccurate learning of the full charge capacity due to current pulse sign changes or breaks of the current flow, a time constant is built in for the state changes between CI and CD. In this way current spikes with the duration below a time constant, MC.sub.-- CONST, (on the order of one second), will not toggle the battery state. To avoid this situation, a timing filter is implemented at step 194 to allow measurements to take place in a timely manner. If a state change is not detected the timing filter timer is reset at step 194a. As indicated at step 195 of FIG. 6(b), the timer for the selfdischarge calculation is decremented. Preferably, the timer for the selfdischarge calculation times out every 128 seconds, and this is the frequency in which a selfdischarge calculation is made. Thus, as indicated at step 196 a determination is made as to whether the selfdischarge timer has timed out, i.e., if 128 sec. has passed. If not, the program proceeds to step 401 to perform the current integration procedure 400, as shown in detail in FIGS. 6(d) through 6(g) and explained in further detail below. If the timer has timed out, then, as indicated at step 300, the selfdischarge calculation procedure is performed as will be explained in detail hereinbelow. After the self discharge calculation procedure is performed, the self-discharge calculation timer is reset to 128 seconds as indicated at step 197 in FIG. 6(b).

Selfdischarge calculation routine

Due to the electrochemical nature of batteries the selfdischarging correction of the remaining capacity has to be calculated all the time, independent from the existence of any charging or discharging currents. This is because there will always be a self-discharge current drain regardless of whether the battery is being charged or discharged and the amount current drain is a function of the battery charge and temperature. Thus, as indicated as step 305 in FIG. 6(c), the selfdischarge rate "s" as a function of the relative state of charge "soc" and current temperature T is accessed via a look-up table, shown in FIG. 19(b) which shows a three-dimensional graphic representation of self-discharge current (vertical axis) as a function of relative battery state of charge and temperature. These look up factors "s" for selfdischarge give the predicted selfdischarge rate scaled by the design (nominal) capacity, and, as is shown in FIG. 19(b), the amount of selfdischarge current increases with increasing temperature and increased battery state of charge levels. For instance, at approximately 65.degree. C. and a 95% relative state of charge, battery selfdischarge current might total an amount of up to 30% of the full battery capacity per day. The amount of selfdischarge values are empirically derived and will vary, depending upon the battery chemistry and battery architecture.

At step 310, a determination is made as to whether the state of the battery is capacity increasing or capacity decreasing. If the battery is in a discharging state, as shown at step 315, the total amount of capacity decrease (current drained) since the last state change is calculated and stored in a separate register. If the capacity is increasing, then the program is directed to step 320, where the effects of the selfdischarge rate is taken into account for the error calculation. Step 320 is also performed after the total amount of capacity decrease (current drained) since the last state change is calculated at step 315. Then, at step 325, the actual capacity integral "Itf" is decremented by the selfdischarge rate "s", thus, providing the .SIGMA.I.sub.s .DELTA.t.sub.s in equation (1) described above. Afterwards, the self-discharge procedure ends and the current integration routine 400 is performed (FIG. 6(b)).

Battery charge integration routine

When the battery is being charged, it is said to be in the Capacity Increasing state (CI), else it is in the Capacity Decreasing state (CD). CD includes the standby mode of the battery, when no current flows through the battery poles. In the standby mode only the selfdischarging rate reduces the capacity.

The battery current will be precisely integrated during both charge and discharging states. The capacity integration itself is independent from the battery state. As will be explained, look up tables (LUT) provide adjustment factors to enable more precise capacity adjustment. The first LUT (described above) comprises current efficiency factors dependent upon the battery relative state of charge, the C.sub.-- rate (current), and the temperature; a second LUT comprising selfdischarging rates dependent upon relative state of charge and temperature; and, a third LUT with residual capacity corrections dependent upon the discharging current rate and temperature which give the fraction of the full capacity which can be extracted from the battery under relaxed conditions after the battery has reached an end of discharge voltage condition.

The flow diagram for the current integration process is shown in FIGS. 6(d) and 6(e). As shown in FIG. 6(d) the first step of the current integration process is to determine the magnitude of the relative state of charge (soc). The soc is defined as the actual capacity expressed as a percentage of the full charge capacity (i.e., the capacity of the battery when fully charged) and is used to estimate the amount of charge remaining in the battery. Thus, as indicated at step 405, a determination is made as to whether the remaining capacity is greater than zero (0). If the remaining capacity Itf is a negative number, the full capacity is incorrect and must be learned and the soc value is clamped to zero (as indicated at step 412 in FIG. 6(d). Otherwise, the soc calculation will take place at step 410. The actual logic that is implemented at step 410 is indicated as follows: ##EQU2## where "x" is a scale factor and is preferably equal to 128 in the preferred embodiment. As previously described, until the full charge capacity of the battery is learned, the full charge capacity is initialized as the design (nominal) capacity.

Next, as indicated at step 415 in FIG. 6(d), the C.sub.-- rate is calculated. The C.sub.-- rate is defined as the rate in which it would take the energy source to drain in one hour and is measured in units of reciprocal hours. The C.sub.-- rate calculation in step 415 is based on the actual current value (I) and the present full charge capacity value and is additionally scaled. A determination is then made at step 418 as to whether the battery is in a capacity increasing or capacity decreasing (discharging) state. If the capacity is increasing, then the battery is being charged and the charge calculation must take into account a charge efficiency factor, made available in the charge efficiency factor accessible by the microprocessor, as shown in FIG. 19(c). Thus, at step 420 the charge efficiency factor that is dependent upon the current relative state of charge (soc), the C.sub.-- rate, and the temperature, is accessed. For instance, as shown in FIG. 19(c), when the battery is charged to approximately 95% of full capacity, and the current is being charged at a 0.1 C.sub.-- rate at a temperature of 45.degree. C., the charge efficiency factor .epsilon..sub.c is found to be about 0.8. The charge efficiency factors are emperically derived and will vary depending upon the battery chemistry and battery architecture. The representations shown in FIG. 19(c) are for a battery state of charge 95% and it is understood that charge efficiency values will vary considerably depending upon (remaining capacity) state of charge.

Finally, the increase in charge for the current time interval taking into account the actual current and the charge efficiency factor is calculated at step 435 to form the term .epsilon..sub.c I.sub.c .DELTA.t.sub.c in equation (1). This value will be used to increment the integration at step 445 as will be explained below.

If at step 418 it is determined that the capacity is decreasing, the amount of discharge will be integrated for the current discharge cycle as indicated at step 422 in FIG. 6(d). It is next determined at step 425 whether the self-discharge flag had been previously set (step 175, FIG. 6(a)) indicating that the battery discharge current is less than 3 mA, and that only the self-discharging processes need to be considered. If the self-discharge flag bit has not set, a charge calculation is made at step 440 to increment the integration. The final integration is accomplished at step 445 wherein the charge increment calculated at either step 435 or 440 is added to the remaining capacity Itf, and, as indicated in equation (1). Additionally, at step 445, the charge is integrated for the error calculation and the running total of the error is also calculated.

If it is determined at step 425 that the self-discharge flag is set (step 175), then the battery is in the selfdischarging mode (step 175, FIG. 6(a)) without any external current drain and the residual capacity is calculated as indicated at step 451. The detailed residual capacity calculation subroutine 450 is shown in FIG. 6(e), and the first step of this routine is to determine the residual battery capacity value. This value, which is dependent upon the current C.sub.-- rate and the temperature, is accessed at step 453 by the microprocessor from the look-up table depicted in FIG. 19(a). For instance, as shown in FIG. 19(a), at a temperature of -20.degree. C. and a current drain of twice the C.sub.-- rate, (2C), it has been empirically derived that approximately 95% of the full battery capacity will remain when the end of discharge voltage is reached. When applying a light load (e.g., C/10 discharge rate) at a temperature of about 23.degree. C., virtually no residual capacity will remain when end of discharge voltage is reached.

At step 455, a determination is made as to whether the C.sub.-- rate is greater than a high discharge threshold rate (preferably of.sub.-- mAh) and whether the End of Discharge flag (see step 262, FIG. 5(b)) had been set. If not, then the capacity calculation at steps 440 and 445 (FIG. 6(d)) is performed as described above. If the current discharge rate is higher than the high discharge threshold rate, then all of the capacity resets are disabled, as indicated at step 456 in FIG. 6(e), and the integration procedure continues at step 440, FIG. 6(d).

During the operational state of the battery, whether the battery capacity is increasing (CI) or decreasing (CD), the end of charge conditions (EOC) and end of discharge (EOD) conditions, respectively, have to be observed. Therefor, the capacity calculation routine illustrated in FIGS. 6(a) and (b) continues by making a determination as to whether the battery is in a capacity increasing or capacity decreasing (resting or discharging) state, as indicated at step 198 in FIG. 6(b). If the capacity is increasing, then the routine for determining whether an End.sub.-- Condition CI has been met as indicated at step 500. If the capacity is decreasing, then the routine for determining whether an End.sub.-- Condition CD has been met as indicated at step 600.

Observation routine for capacity increasing end conditions

The microprocessor of the hybrid IC calculates a charge termination by one of three methods: a negative voltage slope greater than 10 mV/cell/min .+-.5 m V/cell/min at a full charge voltage; a.sup..DELTA.T /.sub..DELTA.t that exceeds 0.9.degree./min.+-.0.2.degree./min, or a preferred calculated charge of 120% of full charge capacity (but may range from 100% to 150% of CAP.sub.FC. The routine for determining if one of the EOC trigger conditions has been met is illustrated in the flow diagrams of FIGS. 7(a)-7(d).

If it is determined that the capacity is increasing, then the first step 505 of the EOC (CI state) observation process 500 illustrated in FIG. 7(a), is a determination of whether the battery's relative state of charge (soc) value is greater than 20% of the battery's full charge capacity value. If the battery has attained that level of capacity, then the fully discharged status flag is cleared at step 507. As will be explained below, the fully discharged status flag is set when it is determined that the battery has supplied all the charge it can without being damaged. Until the battery reaches that capacity level, the FULLY.sub.-- DISCHARGED status flag will remain set. Next, as indicated at step 510, the first EOC trigger detection method is performed. This first method is a determination as to whether the dT/dt trigger enable condition has been met, and, whether the slope of the temperature increase dT is greater than or equal to a threshold limit indicating an EOC condition. In the preferred embodiment, the dT/dt trigger enable condition is satisfied whenever the relative state of charge (soc) is above a 50% threshold limit, and, an end of charge condition is detected when the slope of the temperature increase becomes greater than a threshold of about 0.9.degree.C./min. It should be mentioned that the slope of the temperature may trigger EOC when it is detected within the range from 0.5.degree.C./min to 12.degree.C./min. If either of these conditions are not satisfied, then a second method of detecting an EOC condition, namely, a detection of whether the slope of the voltage change, dU/dt, becomes negative wherein the value of dU/dt must have a minimum amount and the charging current rate (C.sub.-- rate) must be greater than a certain value, is performed at step 540 as will be explained in further detail below. If the dT/dt trigger enable condition has been met and the slope of the temperature increase dT is greater than or equal to the EOC threshold limit, then a determination as to whether the EOC flag has been set is made at step 512. When the EOC flag has not been set, then the number of cells in the battery pack will have to be learned--a process indicated as element 700 in FIG. 7(b) to be described below. Whether or not the number of cells in the battery pack is learned (as will be explained below), at step 700, then step 570 is performed wherein: a) the EOC status flag is set; b) the remaining capacity is set equal to 95% of the full charge capacity; c) the error registers are cleared; d) the overflow flag for the uncertainty calculation is cleared; and, e) the fully charged status flag is set indicating that the battery has reached a charge termination point. Finally, the algorithm proceeds to step 575, shown in FIG. 7(c), where the terminate charge alarm flag is set.

If the dT/dt trigger enable condition has been met, the slope of the temperature increase dT is greater than or equal to the EOC threshold limit, and the EOC flag has been set (step 512), then a determination is made at step 514 as to whether the remaining capacity (Itf) is greater than or equal to the full charge capacity. If this condition is satisfied, then the remaining capacity is set to the full charge capacity as indicated at step 520. Additionally, at step 520, the error registers are cleared and the overflow flag for the uncertainty calculation is cleared. If the remaining capacity (Itf) is not greater than or equal to the full charge capacity (step 514) then the algorithm proceeds to step 575, shown in FIG. 7(c), where the terminate charge alarm flag is set. In the preferred embodiment, the terminate charge alarm flag must be set when the battery detects EOC on any of the EOC trigger conditions or when an over temperature condition exists, i.e., if T.gtoreq.AL.sub.-- HI.sub.-- TEMP (step 228, FIG. 5(a)). As explained above, the terminate charge alarm flag may already be set by the 95% full-trigger, which is initiated when the first temperature slope trigger condition is satisfied at step 510.

After the remaining capacity is set to the full charge capacity at step 520, the algorithm proceeds at step 530 to determine whether the battery charger is still on. This is accomplished by checking for a positive charge increase obtained during the charge integration process (see step 435, FIG. 6(d)). If the charger is still on, then it is known that the charger is continuing to overcharge the battery, and the algorithm must keep track of the amount of battery overcharge. Thus, at step 532 in FIG. 7(a), the total amount of overcharge is calculated by adding the charge increase to the overcharge registers (not shown). It should be mentioned that the overcharge register is never reset, so that the total amount of overcharging since the system start-up is retained. Whether or not the battery charger is still on, the algorithm proceeds to step 535 where the overcharging alarm status flag is set indicating that the battery is being charged beyond an EOC indication. Finally, the algorithm proceeds to step 575, shown in FIG. 7(c), where the terminate charge alarm flag is set.

As mentioned above with respect to step 510, if either the dT/dt trigger enable condition has not been met, or, the slope of the temperature increase dT is not greater than or equal to the EOC threshold limit, then a second method of detecting an EOC condition is performed at step 540 shown in FIG. 7(c). At step 540, a determination is made as to whether: a) the charge is constant current, i.e., whether the difference between the current value and the average current value for one (1) minute is preferably less than 50 milliamps; b) whether the dU/dt voltage change is negative and is greater than a threshold amount of preferably 12 mV/m; and, c) whether the charge current is greater than a predetermined rate, preferably, a rate of C/10. If either of the second method EOC trigger conditions are not satisfied, then a third method of detecting an EOC condition, namely, a detection of whether the relative state of charge (soc) is above 120% and the current rate is between C/50 and C/5 is performed at step 545. It should be mentioned that the EOC condition may be triggered when the relative state of charge (soc) is detected within the range of 100% to 160%. If all of the second method EOC trigger conditions are satisfied, or, if all of the third method EOC trigger conditions are satisfied, then a determination as to whether the EOC flag has been set, is made at step 550 in FIG. 7(c). If either the second method EOC trigger conditions or third method EOC trigger conditions are satisfied, and the EOC flag has been set (step 550), then the fully charged status flag is set at step 555 indicating that the battery has reached a charge termination point. Afterwards, the process proceeds at step 520, FIG. 7(a), by clamping the remaining capacity value to the full charge capacity value as described above. If the EOC flag has not been set, then the number of cells might have to be learned--a process indicated as element 700 to be described below. When the process of learning the amount of cells in the battery is complete, then the EOC status flag will be set at step 551, and the fully charged status flag is set at step 555 indicating that the battery has reached a charge termination point and the algorithm continues at step 520 described above. If all three EOC trigger conditions are not satisfied, then the EOC detection procedure 500 is exited and the capacity calculation (FIG. 6(b)) continues.

Alternately, a -dU trigger condition will be reached when it is determined that the battery capacity is increasing, dU>DU.sub.-- MIN, where DU.sub.-- MIN is a predetermined value equal to the number of battery pack cells multiplied by 10 mV, and the current is determined to be constant and the charge rate is higher than 0.3 C. The charge current is considered constant if .vertline.I-I.sub.-- avg.vertline.<50 mA and .vertline.I-I.sup.-1 .vertline.<50 mA where I.sup.-1 was the previous value of the current measurement. The constancy of the battery charging may be calculated in addition to, or, in place steps 250 et seq. of the IUT calculation routine FIG. 5(b), where the method of calculating -dU may be accomplished without time dependency.

Learn number of cells routine

As described above, an emergency power-down condition may occur wherein all RAM contents are lost. In such a situation, it may be necessary to relearn the number of cells in the battery pack. Rather than burning in the number of cells for a particular battery module in the ASIC ROM, the number of cells may be learned to enable the ASIC to be configured with other battery packs having a different number of cells. The relearning of the number of cells is indicated by a bit (CALIBRATED bit) in the AL.sub.-- STATUS register, which will indicate whether the number of battery cells has to be relearned. In the preferred embodiment, it is easily accomplished by utilizing the voltage measured at the battery pack terminals after an EOC condition, described above, is met.

The first step 705 in the learn number of cells procedure 700 shown in FIG. 7(d), is to determine whether the battery pack is uncalibrated, i.e., whether the CALIBRATED bit in the AL.sub.-- STATUS register indicates that the number of cells should be learned. If so, it is determined at step 710 whether the converted voltage value, U (mV), measured at step 210, FIG. 5(a) during the IUT calculation procedure, is greater than 11 volts. If so, then it is concluded that the battery pack has nine (9) cells and the number of cells is set at nine in step 720. If the measured voltage value, U, is not greater than 11 volts, then a determination is made at step 715 as to whether the voltage is greater than 7.5 volts. If so, then it is concluded that the battery pack has six (6) cells and the number of cells is set at six in step 725. If the measured voltage value, U, is not greater than 7.5 volts, then it is concluded that the battery pack has four (4) cells and the number of cells is set at four in step 730. After the number of cells is determined, the EOD cutoff voltage, Uempty, is set equal to the number of cells multiplied by the operating battery voltage of 1.02 Volts in the preferred embodiment as indicated at step 740 in FIG. 7(d).

Observation routine for capacity decreasing end conditions

As previously mentioned, the capacity calculation routine 151 at step 198 makes a determination as to whether the battery is in a capacity increasing or capacity decreasing (resting or discharging) state. If it is determined that the capacity is decreasing, then the first step 605 of the EOD (CD state) observation process 600 illustrated in FIGS. 8(a) and 8(b), is a determination of whether the present voltage measurement (U) is greater than the end of discharge voltage (EDV) and any hysteresis. When the EDV voltage is reached, it is an indication that discharging should be stopped to save the battery from damage. Typically, the EDV is 1.02 V/cell. If the voltage obtained is greater than the EDV voltage, then a flag indicating that the voltage is greater than the EDV voltage plus hysteresis is set at step 610. If the voltage is not greater than the EDV voltage plus hysteresis, then the flag is cleared at step 612. Additionally, as indicated at step 613, since the capacity is decreasing, the Terminate Charge Alarm and Over Charging Alarm flags are cleared.

A determination as to the value of the remaining capacity (Itf) is made at step 615, where it is determined whether the remaining capacity is less than the calculated error (i.e., the uncertainty capacity). If the remaining capacity is less than the calculated error, then this is an indication that the battery pack has no more capacity and is fully discharged. Consequently, the FULLY.sub.-- DISCHARGED status flag is set at step 618 and the process continues at step 619. If there is remaining capacity, then the FULLY.sub.-- DISCHARGED flag is not set, and the process continues at step 619 where a determination of the relative state of charge is made. If the relative state of charge (soc) has dropped below some hysteresis value, preferably, about 80% of the full charge capacity, then the FULLY.sub.-- CHARGED status flag is cleared, as indicated at step 620. Whether the FULLY.sub.-- CHARGED status flag is cleared or not, the process continues at steps 625 and 630, where the cycle count number is updated. At step 625, a determination is made as to whether a cycle count flag is cleared, and, whether the capacity has decreased by 15% of nominal capacity. If these two events of step 625 have occurred, then the cycle count register, containing a value of the number of times the battery has been charged or discharged (not shown), will be incremented at step 630 and the cycle count flag will be set. It should be understood that in the preferred embodiment, the cycle count will be incremented whether or not the battery has been fully or partially charged. Whether the cycle count flag is incremented or not, the process continues at step 640, where a check is made as to whether the EOD flag is set, and, whether the reset flag is clear. If either the EOD flag is not set, or, the reset flag is not clear, then the end condition observation routine 600 is exited. If the EOD flag is set, and, the reset flag is clear, then a determination is made at step 645 as to whether the EOC (end of charge) flag has been set and whether the error value (uncertainty capacity) is less than 8% of nominal capacity. If these conditions are satisfied then the full charge capacity value is learned at step 650. Specifically, whenever the battery has performed a full cycle reaching an EOC trigger point and the EOD point and the uncertainty capacity is below 8% of the nominal capacity, the full charge capacity is reset at step 650 with the formula:

where "pd" is the predicted residual capacity correction value accessed from the look-up table of FIG. 19(a) and dependent upon the discharging current rate and temperature. The divisor 256 provides for an integer scaling of pd. The meaning of the formula is to exchange the remaining capacity (Itf) by the residual capacity from the LUT table, which contains fractions of the full charge capacity (Note: the residual capacity obtained is calculated from step 451 of the charge integration process of FIG. 6(d)). If the EOD point is reached with less capacity output as in the former cycle, the amount of Itf (remaining capacity) will be higher at EDV (less discharged capacity compared with the accumulated charged capacity). The full charge capacity will be reduced by the difference of Itf compared with the former cycle so that the ageing of the battery is taken into account by this learning step. If the battery is used in several partial charge/discharge cycles without reaching an EOC or EOD point, the error of the calculation can accumulate to a heavy difference between the real capacity and the calculated remaining capacity (Itf). The algorithm (MaxError()), to be explained in detail below, calculates the maximum possible error (uncertainty) during its operation as precise as the capacity integration itself on the base of a percentile error for each operating mode. The uncertainty is reset to zero at each EOC and EOD point. An uncertainty of above 8% disables the full capacity reset. Additionally, when the conditions at step 650 are satisfied, the EOC flag is cleared indicating that the full charge capacity has been reset. After the full charge capacity is reset (step 650), or, if it is determined that the uncertainty error is greater than the prespecified value of 8%, or, the EOC flag is not set, then the algorithm continues at step 655.

At step 655, a determination is made as to whether the C.sub.-- rate at the EDV (end of discharge voltage) trigger is equal to zero, or, whether the present C.sub.-- rate is less than the C.sub.-- rate at the EDV trigger, and, whether the capacity reset is not disabled. If either of these conditions are satisfied, the present current at the EOD trigger is set equal to the present C.sub.-- rate, the delayed capacity reset value is set equal to the present residual capacity value, and, the flags to delay capacity reset after EOD are set at step 660. Else, if both of the conditions of step 655 are not met, then the end conditions observation routine 600 is exited. As indicated in FIG. 6(a) of the capacity calculation routine 151, if the EOC and EOD triggering has not occurred, then the capacity calculation is exited.

System management bus and bus interface

As described above, and as shown in FIGS. 2(a) and 2(b), a modified Phillips I.sup.2 C bus interface is used by the battery module 28 to communicate within a configuration comprising the ASIC 32 and the battery 10, a host computer 16, and a smart charger 22. As mentioned previously, requests are either from the host computer to the battery, from the charger to the battery, or, from the battery to either the host or charger. An example of a typical communication between the battery and the charger may be to switch the charger on and off, or, to demand a certain charging rate. The host computer may request information of the battery such as the battery state, or, the battery alarm conditions such as minimal capacity, or, overtemperature. The bus interface control circuit 75 controls all requests and alarm conditions via two serial ports SMBCLK and SMBDATA over the system management bus.

When the battery 10 needs to inform the host of an alarm condition or to inform the battery charger about its desired charging voltage or current, the battery acts as a bus master with write function capabilities. The battery will function to: evaluate the request from the .mu.P 50; check if the system management bus is free; generates a start bit and sends the address of the battery charger or host; checks whether the ACK-bit has been sent from the charger or host and gives a message to the .mu.P; sends the data supplied from the .mu.P on the bus and checks for ACK bit; generates a stop-bit at the end of the transfer.

When the battery 10 is requested by the host to provide it with information to be explained below, the battery acts as a bus slave with read and write capabilities. For instance, during the steady-state operation, the host might request some information from the battery and will formulate a request. FIG. 9 illustrates the software algorithm compatible with the system management bus interface protocol for providing communication between an external device (host PC or battery charger), and the battery, which acts as a slave thereto.

Specifically, the first step 750 in FIG. 9, is to decode the command code that has been sent by the external device. Illustrative command codes are discussed hereinbelow, and each typically requires two bytes of data to be transmitted which is indicated as the variable "count". The next step, indicated as step 752, is to determine whether the command code sent is a valid, recognizable command word. If not, a unsupported command bit is set at step 755 and the transmission will be terminated as indicated at step 758a in FIG. 9. If the command is supported, the battery will perform an internal check to determine if an error has occurred at step 759. If an internal error is found, then the algorithm will enter a timer loop which will keep checking the internal flag until an error is confirmed or the timer (not shown) times out. This is indicated at step 761. If a correct value is found at step 759, then the algorithm will continue at step 764 to determine if the decoded command code calls for a read or write function. If the timer has timed out, or, an error is confirmed at step 761, then an unknown error flag is set at step 763 and the software transmission is terminated at step 758b.

When functioning as a slave, the battery will perform either read or write functions. At step 764, a determination is made as to whether the command code input (step 750) is a read or write command. If it is a read command, a determination is made at step 765 as to whether the battery is to perform a calculation as requested by the external device and return a value to be read by the external device. Examples of calculations made by the battery in response to a query (for e.g., AvgTimeToEmpty()) from a host device are described in greater detail below. The battery .mu.P will proceed to perform the calculations at step 768 and will return a data value to a specified address location as indicated by the read block routine at step 800 and explained in detail below. If it is determined at step 765 that a calculation is not to be performed, (for e.g., only a voltage value is requested) then the algorithm will proceed directly to the read block routine 800 as shown in FIG. 9.

If, at step 764, it is determined that a write function is to be performed wherein a data value is to be written to the battery address location from an external device, (for e.g., the AL.sub.-- REM.sub.-- TIME threshold value), then a write block authorization check must be performed to determine if the external device may perform the write function. This is indicated at step 771 where a password is checked for validity. If the password checked is not an authorized password, then access will be denied as indicated at step 774, and the external device will not be able to perform the write function and will terminate the software transmission at step 758b. If the external device is authorized to write data to a battery address, then the device will write a data value to pre-specified address locations, as indicated by the write block routine at step 775 to be explained in detail below.

Host to Smart Battery Communication

This type of communication transfers data from the battery to either a user (of a host PC, for e.g.), or, the power management system of an external device. A user can get either factual data, such as battery characteristic data, (Voltage(), Temperature(), charge/discharge Current(), AverageCurrent() etc.), or, predictive (calculated) data such as the battery's remaining life at the present rate of drain, or, how long it will take to charge the battery.

The following control commands are representative of battery supplied information when queried by a host device or host PC:

The RemainingCapacity() function returns the battery's remaining capacity and is a numeric indication of remaining charge. Depending upon the capacity mode bit, the RemainingCapacity() function will return a value in mAh or 10 mWh. The value returned is calculated as follows:

where the uncertainty error Itf.sub.-- err is the subtracted value and the output value is cut at 0 if (.vertline.Itf.vertline.<.vertline.Itf.sub.-- err.vertline.).

The RemainingCapacityAlarm() function sets or retrieves the low capacity threshold value AL.sub.-- REM.sub.-- CAP (described above) for the low capacity alarm in RAM. When the RemainingCapacity() falls below the AL.sub.-- REM.sub.-- CAP value, the battery sends Alarm Warning() messages to the host with the REMAINING.sub.-- CAPACITY.sub.-- ALARM bit set. At manufacture, the AL REM CAP value is set to 10% of design capacity and will remain unchanged until altered by the RemainingCapacityAlarm() function. This function is used by any host system that desires to know how much power it will require to save its operating state. It enables the host system to more finely control the point at which it will transfer to a standby or sleep mode.

The RemainingTimeAlarm() function sets or retrieves the AL.sub.-- REM.sub.-- TIME alarm value. When the estimated remaining time at the present discharge rate as calculated by the AverageTimeToEmpty() function falls below the AL.sub.-- REM.sub.-- TIME value, the battery sends Alarm Warning() messages to the host with the REMAINING.sub.-- TIME.sub.-- ALARM bit set. An AL.sub.-- REM.sub.-- TIME value of zero (0) effectively disables this alarm and the value is initialized to 10 minutes at time of manufacture. The FullChargeCapacity() function returns the predicted battery pack capacity when it is fully charged and is expressed either in current (maH or 10 mwH) depending upon the setting of the CAPACITY.sub.-- MODE bit (discussed below). This information, along with information about the original capacity (DesignCapacity()) of the battery, can be presented to the user as an indication of battery wear. The DesignCapacity() returns the theoretical capacity of a new battery pack which when compared with the value returned by the FullChargeCapacity(), will provide an indication of the battery wear. This information is useful by a host device or host PC to adjust its power management policy.

The AtRate() function is the first half of a two-function call-set used to set the AtRate value used in calculations based on capacity made by the AtRateTimeToFull(), AtRateTimeToEmpty(), and, AtRateOK() functions.

When the AtRate value is positive, the AtRateTimeToFull() function returns the predicted time, preferably in minutes, to fully charge the battery at the AtRate value of charge (value is in ma). The calculation formula is governed by equation (.sub.--): ##EQU3## where "time" is the returned value in minutes.

The AverageTimeToFull() function returns the predicted remaining time in minutes until the battery is full if a current like the last minute rolling average, I.sub.-- avg, value is continued. The calculation formula is governed by equation (.sub.--): ##EQU4## where "time" is the returned value in minutes.

When the AtRate value is negative, the AtRateTimeToEmpty() function returns the predicted operating time, preferably in minutes, at the AtRate value of battery discharge, until the battery will be exhausted (EDV condition). The calculation formula is governed by equation (.sub.--): ##EQU5## where "time" is the returned value in minutes, .vertline.AT.sub.-- RATE.vertline. and pd.sub.-- at.sub.-- rate values are calculated by the AtRate() function where pd.sub.-- at.sub.-- rate represents the remaining capacity (fraction of full.sub.-- capacity) and is divided by the value of 256 to scale that value to a fraction. Itf.sub.-- err is the uncertainty error as explained below.

When the AtRate value is negative, the AtRateOK() function returns a Boolean value that predicts the battery's ability to supply the AtRatevalue of additional discharge energy for 10 seconds, i.e., if the battery can safely supply enough energy for an additional load after the host PC sets the AtRate value.

The RunTimeToEmpty() function returns the predicted remaining battery life at the present rate of discharge (minutes) and is calculated based on either current or power depending upon the setting of the CAPACITY.sub.-- MODE bit (discussed below). The value returned by this function can used by the host PC or device power management system to get information about the relative gain or loss in remaining battery life in response to a change in power policy. The calculation formula is governed by equation (.sub.--): ##EQU6## where "time" is the returned value in minutes and takes into account the remaining capacity in the battery after EDV which can be get out only by reduction of the load; .vertline.I.vertline. is the current, pd:=pd(C.sub.-- rate(.vertline.I.vertline., T) and is calculated in the capacity calculation algorithm pd represents the remaining capacity (fraction of full.sub.-- capacity). This value is divided by 256 to obtain a fraction. Itf.sub.-- err is the uncertainty error as explained below.

The AverageTimeToEmpty() function returns a one-minute rolling average of the predicted remaining battery life (in minutes) and is calculated based on either current or power. This function provides an averaging of the instantaneous estimations, thereby ensuring a more stable display of state-of-charge information. The calculation formula is governed by equation (.sub.--): ##EQU7## where "time" is the returned value in minutes, I.sub.-- avg is updated every 0.5 sec, pd.sub.-- avg:=pd(C.sub.-- rate(I.sub.-- avg), T) and is calculated in the alarm control routine one cycle before and represents the predicted residual capacity (fraction of full.sub.-- capacity). This value is divided by 256 to obtain a scale fraction. Itf.sub.-- err is the uncertainty error as explained below.

FIG. 20 illustrates two voltage versus time graphs, a and b, comparing calculated battery capacity characteristics at various discharging current rates for a six (6) cell battery pack. As shown in FIG. 20, graph a, the voltage will rapidly decrease to an end of discharge condition in a short amount of time when a load amounting to a discharge rate of 2 C and yielding approximately 1.554 Ah (amperehours) is applied to the battery. When the load is significantly decreased to a C/5 discharge rate, the battery pack voltage will generously rise to extend the life of the battery for an amount of time to yield another 0.816 Ah. Graph b, which is of a different time scale than graph a, shows that discharge at the C.sub.-- rate will yield approximately 2.307 Ah. When that load is lightened to one half the C.sub.-- rate, the battery voltage will increase slightly and the battery life can be predicted to extend for an amount of time to yield another 0.078 Ah until end of discharge voltage is reached.

As discussed above, certain calculations are dependent upon the value of the uncertainty capacity, i.e., the maximum possible error obtained during the capacity calculations. The MaxError() function returns the actual uncertainty in the capacity calculation in percentage. A MaxError() output of 20% means that the real value may be between 10% below and 10% above the internally calculated capacity. Most of the calculations in the system management bus interface already subtracts the uncertainty error, so that the error will be -0/+MaxError()%. The uncertainty is set to zero on EOC and EOD conditions by the capacity algorithm as explained above. The calculations performed are as follows: ##EQU8## where Itf.sub.-- err.sub.-- C.sub.-- D is the always positive accumulated charge during the charging and discharging mode; Itf.sub.-- err.sub.-- S is the accumulated charge of the self.sub.-- discharging process. Because of the permanent presence of selfdischarging, even while charging, this accumulation is done all the time using the LUT dependency from relative state of charge (soc) and temperature. Both accumulators are reset to zero at EOC and EOD condition. EPS is the error fraction of the capacity calculation--especially from the LUT and from A/D measurement--while charging or discharging, with the scaling factor 256 applied. EPS.sub.-- S is the error for selfdischarge-charge integration as fraction. The uncertainty will grow undesirable if the battery will not be fully or discharged over several cycles and the learn mode of the full capacity will be disabled.

The CycleCount() function returns the number of charge/discharge cycles the battery has experienced. The cycles count on each charge decrease with the amount of 15% of the design capacity after the last recharging, which needs not to be a full charging.

Other registers contained in the DBOS memory scheme is the BatteryMode() register which is used to select the battery's various operational modes. For instance, the BatteryMode() register is defined as containing a CAPACITY.sub.-- MODE bit which is set to specify whether capacity information is to be broadcast in units of mAh or mwH (milliwatthours). This bit allows power management systems to best match their electrical characteristics with those reported by the battery. For example, a switching power supply represents a constant power load, whereas a linear supply is better represented by a constant current model. Additionally, the BatteryMode() register contains a CHARGER.sub.-- MODE bit which is set to specify whether charging voltage and charging current values are to be broadcast to the smart battery charger 22 (FIG. 1) when the smart battery requires charging. This bit allows a host PC or battery charger to override the smart battery's desired charging parameters by disabling the smart battery's broadcast of the charging current and charging voltage.

Another function calculated on the basis of capacity is the BatteryStatus() function which is used by the power management system of a host device or PC to get alarm and status bits, as well as error codes from the battery. This function returns the battery's status word flags including alarm warning bits such as OVER.sub.-- CHARGED.sub.-- ALARM, TERMINATE.sub.-- CHARGE.sub.-- ALARM, DTEMP.sub.-- ALARM, OVER.sub.-- TEMP.sub.-- ALARM, TERMINATE.sub.-- DISCHARGE.sub.-- ALARM, REMAINING.sub.-- CAPACITY.sub.-- ALARM, and REMAINING.sub.-- TIME.sub.-- ALARM and status bits including INITIALIZED, DISCHARGING, FULLY.sub.-- CHARGED, and, FULLY.sub.-- DISCHARGED.

Ancillary functions that the battery 10 is capable of performing include: the SpecificationInfo() for providing the version number of the smart battery specification the battery pack supports; the ManufactureDate() for providing a system with information that can be used to uniquely identify a particular battery; the Serial Number(), which provides information for identifying a particular battery; the ManufacturerName() function returns the name of the smart battery's manufacturer; the DeviceName() function returns a character string that contains the battery's name; the DeviceChemistry() returns a character string that contains the battery's chemistry; the ManufacturerData() function which allows access to the manufacturer data (e.g., lot codes, number of deep cycles, discharge patterns, deepest discharge, etc., contained in the battery.

Write Block Routine

As mentioned above, the battery may receive data from an external device to be used in a control command calculation, or, as an alarm threshold value. The write block 775 illustrated in FIG. 10, controls this transfer of data to the battery. First, at step 776, a determination is made as to whether the data value to be read from the external host device is greater than two bytes long. In the preferred embodiment, most control commands will write a data value to the battery that is two bytes long. If the data is longer than two bytes, i.e., if count>2, then the variable "w" is set equal to the number of address locations allocated for and corresponding to length of data in number of bytes at step 778. Then, at step 780, a determination is made as to whether the previously determined count value has been set equal to the address locations allocated. If this is not the case, then an error flag is set at step 790 indicating that an inordinate amount of data is to be sent, or, that there is not enough locations allocated for receiving the data. If the previously determined count value "count" has been set equal to the number of address locations allocated, then the program enters a loop indicated as steps 781, 783 and 785 wherein each byte of data is sequentially written to the I.sup.2 C bus to the battery address location [Adr] (step 783). After each byte is sent, the count of the number of bytes is decremented and the address location for the next sequential data byte to be written is incremented. Until count=0, indicating that the last byte of data has been transmitted to the battery as shown at step 785, the loop will continue and enter at step 781 to determine if the battery has read each data byte (RDVAL=1) sent by the external device and indicating that the data byte has been successfully transmitted. If the read acknowledge flag has been received after each byte transfer, the loop continues at step 783 until the last data byte is sent. If the read acknowledge flag has not been received, then an error may have occurred and the program proceeds to step 782 where a determination is made as to whether a bus error or timeout has occurred. If none of these instances has occurred, then the program will proceed to step 787 to determine if the bus master has terminated the transmission. If the bus master has terminated the transmission, then an error flag is set at step 790 indicating that an inordinate amount of data is being transmitted and the transmission will be terminated at step 795. If the bus master has not terminated the transmission, then the system will continue to look for the RDVAL flag until an internal handshake timer (not shown) times out (step 782) and an unknown error flag is set and the transmission will be terminated, as shown at steps 792 and 795. In view of FIG. 10, it is understood that in some cases, a fixed two-byte data word is to be read, as indicated at step 776, and the algorithm will proceed directly to step 783 where the first data byte is read by the battery at the first battery address location.

After the last data byte has been received, as indicated at step 786, a determination is made as to whether the stop bit flag has been received from the modified I2C bus master indicating the end of bus control due to the fact that the external device will not be sending any more data. If the stop bit is received the write block is exited. If the stop bit has not been received, then an error may have occurred and the program proceeds to step 788 where a determination is made as to whether a bus error or timeout has occurred. If an error or timeout has occurred, then the program will proceed to set an unknown error flag and the transmission will be terminated, as shown at steps 792 and 795. If none of these instances has occurred, then the program will proceed to step 789 to determine if the RDVAL flag has been set to indicate if the last data byte has been successfully read. If it has been successfully read, then this is an indication that the external device has not finished sending data or that not enough address locations have been allocated and an error flag will be set as shown at step 790 and the transmission will be terminated at step 795. If the last data value has been successfully read at step 789, then the process will continue to look for the modified I.sup.2 C bus master stop bit at step 786 until either an internal handshake timer (not shown) times out or an error occurs (step 788).

Read Block Routine

As mentioned above, the battery will return a calculated or measurement data value to a specified address location as indicated by the read block routine 800 as illustrated in FIG. 11. At step 802, a determination is first made as to whether the data value to be written to the host device is greater than two bytes long. If the data is longer than two bytes, i.e., if count>2, then the address is pointed to at step 805 and the program enters a loop indicated as steps 808, 812, and 815 wherein each byte of data is sequentially written to the SMBus bus to an address location of the requesting host device as indicated at step 812. After each byte is sent, the count of the number of bytes is decremented and the address location for the next byte to be written is incremented. Until count=0, indicating that the last byte of data has been transmitted to the external device as shown at step 815, the loop will continue and enter at step 808 to determine if the acknowledge bit has been sent by the external device indicating that the current data byte has been successfully transmitted. If the acknowledge bit has been received after each byte transfer, the loop continues at step 812 until the last data byte is sent. If the acknowledge bit has not been received, then an error may have occurred and the program proceeds to step 821 where a determination is made as to whether a bus error, termination, or timeout has occurred. If none of these instances has occurred, then the program will proceed to step 808 to again determine if the data byte acknowledge bit has been received. This process will continue until an internal handshake timer (not shown) times out wherein the process will continue at step 825 where an unknown error flag is set and the transmission will be terminated. After it is determined that the last data byte has been sent (step 818) then a flag indicating that the last byte has been sent is set at step 818 of FIG. 11. In view of FIG. 11, it is understood that in some cases, no data is to be returned as shown at step 802, and the algorithm will proceed directly to step 812 and bypass the receipt acknowledgment bit step 808.

Next, as indicated at step 822, a determination is made as to whether the stop bit flag has been received from the I.sup.2 C bus master indicating the end of bus control due to the fact that the external device will not be receiving any more data. If the stop bit is received the read block is exited. If the stop bit has not been received, then an error may have occurred and the program proceeds to step 824 where a determination is made as to whether a bus error or timeout has occurred. If none of these instances has occurred, then the program will proceed to step 822 to again determine if the stop bit has been received. This process will continue until an internal handshake timer (not shown) times out wherein the process will continue at step 825 where an unknown error flag is set and the transmission will be terminated.

Alarm Control

All of the alarm status flags heretofore mentioned indicate that the battery has reached a certain state of charge (fully charged, empty discharged) or a critical state (maximal temperature, being overcharged). These events are encoded in the A1.sub.-- Status battery register and the warning message AlarmWarning() is sent by the by the battery to an external device when the battery detects an alarm condition. In this event, the battery becomes the bus master and alternately notifies the host computer or battery charger of any critical and/or alarm conditions at a rate of preferably once every five seconds, until the critical state is corrected. The alarm condition may be broadcast to the host computer for 10 seconds if the alarm condition is such that the battery charger does not need to be notified of an alarm condition, for e.g., the REMAINING.sub.-- CAP.sub.-- ALARM warning message is not the broadcast to the charger device. If alarm conditions such as OVER.sub.-- CHARGED.sub.-- ALARM, TERMINATE.sub.-- CHARGE.sub.-- ALARM, DTEMP.sub.-- ALARM, OVER.sub.-- TEMP.sub.-- ALARM, and TERMINATE.sub.-- DISCHARGE.sub.-- ALARM exist, then the alarm has to be broadcast alternating between the charger device and the host device in five (5) second intervals.

The modified SMBus protocol for communicating alarm or warning messages are illustrated in the alarm control routine 152 as shown in detail in FIGS. 12(a) and 12(b). This routine runs through all possible alarm conditions for possible broadcast to a host device after a capacity calculation is performed as shown in FIG. 3.

The first step, indicated as step 901 in FIG. 12(a) is to verify the status of the remaining capacity. Specifically, a determination is made as to whether the AL.sub.-- REM.sub.-- CAP run value is greater than 0 and that the remaining capacity (less the uncertainty error) is less than the AL.sub.-- REM.sub.-- CAP value. If these conditions hold true, the REMAINING.sub.-- CAPACITY.sub.-- ALARM bit is set at step 904. If none of these conditions holds true, the REMAINING.sub.-- CAPACITY.sub.-- ALARM bit is cleared at step 906. Next, the C.sub.-- rate based on the one minute rolling average current is calculated and the residual capacity based on the C.sub.-- rate [pd.sub.-- avg:=pd(C.sub.-- rate(I.sub.-- avg), T)] is accessed from the look-up table of FIG. 19(a). Then, at step 910, a determination is made as to whether the battery state is capacity decreasing. If the battery capacity is decreasing, then a determination is made at step 913 as to whether the AL.sub.-- REM.sub.-- TIME alarm threshold value is greater than zero (0). If so, then the estimated remaining time at the present discharge rate is calculated at step 915 by the AverageTimeToEmpty() command code. When the calculated remaining time falls 4below the AL.sub.-- REM.sub.-- TIME threshold value, as determined at step 917, the program sets the REMAINING.sub.-- TIME.sub.-- ALARM bit as indicated at step 919 and the program proceed at step 925 shown in FIG. 12(b). If, it is determined either that the battery state is not capacity decreasing (step 910), or, that the AL.sub.-- REM.sub.-- TIME is equal to zero (step 913), or, that the calculated remaining time falls below the AL.sub.-- REM.sub.-- TIME threshold value (step 917), then the program clears the REMAINING.sub.-- TIME.sub.-- ALARM bit as indicated at step 921 and the program proceed at step 925 shown in FIG. 12(b).

As shown at step 925, the upper byte of the Alarm status register is checked to determine if any alarm bits, e.g., alarm bits such as OVER.sub.-- CHARGED.sub.-- ALARM, TERMINATE.sub.-- CHARGE.sub.-- ALARM, DTEMP.sub.-- ALARM, OVER.sub.-- TEMP.sub.-- ALARM, TERMINATE.sub.-- .sub.-- DISCHARGE.sub.-- ALARM, REMAINING.sub.-- .sub.-- CAPACITY.sub.-- .sub.-- ALARM, and, REMAINING.sub.-- TIME.sub.-- ALARM have been set. If so, then a check of the alarm broadcast flag "alarming" is made at step 927. If the upper byte of the Alarm status register indicates no alarm condition, i.e., no bits set, then the process will continue at step 926 and the alarming broadcast flag is cleared. Note, that upon initialization, the alarming broadcast flag is not set. However, as long as an alarm condition exists, this flag will be set. Therefore, as shown at step 927, if the alarming flag is cleared, the process continues and the alarming flag is set at step 930. Additionally, at step 930, the alarm broadcast timer is set to zero, and, the "alarm to host" flag is set indicating that the alarm will be sent to a host external device and not a battery charger. The process continues at step 933, where a determination is made as to whether the alarm broadcast timer has timed out (=0). Since the broadcast timer has been set to zero at step 930 for this first operating cycle of the alarm condition, or, if the alarm broadcast timer has timed out, then the process will continue at step 935. If the timer has not timed out, then the alarm control process is exited. At step 935, the address location for the alarm broadcast is set to the host device, and the command code is set equal to the battery status [BatteryStatus()] function described above. This will initiate the transfer of the particular alarm to the host device. A determination is then made at step 937 as to whether the alarm to host flag is cleared (=0). During the first operating cycle of the alarm condition (step 930), the alarm to host flag had been set (=1) so the algorithm skips over steps 940 and 943 (discussed below) and performs the send message routine 945 which changes the function of the battery as having bus master control so that the alarm message can be sent. Details of the send message routine 945 will be explained in detail below. Afterwards, at step 947, the broadcast alarm timer is reset to its 10 second time (N.sub.-- ALARM) and the alarm sent to host flag is toggled to the alarm sent to charger flag.

After the message is initiated to broadcast an alarm warning message to the host device at step 945 (by the send message routine), and, the alarm broadcast timer has been reset, then the process continues. After the next capacity calculation (FIG. 3), if the alarm condition still exists (i.e., the alarm bits are set) at step 925, the process is continued. However, for the next and subsequent operating cycles of the alarm condition, the alarming flag has already been set as determined (at step 927), so the alarm broadcast timer (initialized as 10 seconds) is decremented at step 931 until the timer has timed out or the alarm status has been changed. Thus, after the broadcast timer has decremented, the process continues at step 933, where a determination is made as to whether the alarm broadcast timer has timed out (=0). If the broadcast timer has not timed out, then the alarm control routine is exited and these set of steps will continue until the alarm broadcast timer has timed out (step 933). Until the alarm message has been broadcast to the host device for preferably five (5) seconds, then steps 935 and 937 will not be performed. When the broadcast timer has timed out, and, since the alarm to host flag has toggled (during the first operating cycle of the alarm condition), the condition at step 937 will be true. Therefor, the address location for the alarm broadcast is changed and set to the battery charger at step 940, and the program will proceed to step 943 where a determination is made as to whether the particular alarm warning message is meant to be sent to the battery charger for the next 10 seconds. If, the alarm condition is not meant to be transmitted to the battery charger, then the send message routine (step 945) will be bypassed, and the broadcast timer will be reset at step 947 and the alarm to host bit toggled so that the message will be retransmitted to the host device.

Charger Control

Whenever the BatteryMode() CHARGER MODE bit is set to zero, and the battery detects the presence of a smart battery charger, the battery is able to communicate with the smart battery charger and will send ChargingCurrent() and ChargingVoltage() values to the smart battery charger. The ChargingCurrent() function sets the maximum current that a smart battery charger may deliver to the battery and will return the desired charging rate in mA. This allows the battery charger to dynamically adjust its output current to match optimal recharging requirements. A maximum value of 0.times.FFFF means constant voltage charging with the output value of ChargingVoltage(). Results are broadcast with the battery as active bus master under the conditions set forth in the charger control routine 154 of FIGS. 3 and 13.

The first step 850 in FIG. 13 is to determine whether the battery is in the system. If not, CAPACITY.sub.-- MODE and CHARGER.sub.-- MODE variables are cleared at step 853 and the routine is exited. If the battery is installed in the system, a determination is made at step 855 as to whether the battery was just inserted in the system. If the battery was just inserted, then the message timer is set to one (1), and the CAPACITY.sub.-- MODE and CHARGER.sub.-- MODE variables are cleared at step 857 and the algorithm continues at step 859. If the battery has not just been inserted (step 855), then the algorithm skips to step 859 where a determination is made as to the state of the charger mode bit. If the bit is not cleared at step 859, then the routine is exited. If the CHARGER.sub.-- MODE bit is set at step 859 then the timer is decremented at step 861. The next step at 863 is to determine whether the message timer has timed out. If it has, then the message timer is reset at step 865 and the charging current calculation is additionally made. If the message timer has not timed out at step 863, then the routine is exited. The next step 866 is to determine whether the returned value of the calculated charging current is zero. If the charging current value returned is zero, then the process proceeds at step 868. If the charging current is not zero, then the determination is made at step 867 as to whether the state is capacity increasing (CI). If the battery is in a CI state, then the process proceeds at step 868. If the capacity is decreasing, then the routine is exited.

At step 868, the address location for the charger broadcast is set to the battery charger, and the command code is set equal to the command code ChargingCurrent(). Next, at step 870, the charging current command message is sent to the battery charger by the send message routine (discussed below). Then, at step 872, the maximum value (hex FFFF) fed into the ConstantVoltage() function which indicates that the charger will be a constant current charging device. This instruction is broadcast to the charger via the send message routine at step 874. After the charging current is broadcast, the routine is finally exited.

Send Message Routine

As indicated at step 945 in FIG. 12(b) and step 870 in FIG. 13, the send message routine changes the function of the battery to have bus master control so that the alarm messages can be sent. FIGS. 14(a) through 14(b) illustrate the send message routine.

The first step 950 is to determine the data bus availability. If it is determined that the data bus is available, then the first piece of data to be sent is the slave address, i.e., the address of the external host device or battery charger, as indicated at step 952. As soon as the data bus is acquired, then two flags are set; the first flag is an internally generated flag that is set to indicate that the battery now has bus master control (step 953), and, the second flag is the transmission termination flag that is cleared at step 954. The next step, as indicated at step 955, is a check as to whether the acknowledge bit has been sent, i.e., whether the first byte of data (slave address) has been received by the slave device. If the acknowledge bit has not been sent, then a check is made at step 958 to determine if the bus is busy. If the bus is now busy, then the program continues at step 960 of FIG. 14(b). If the bus is not busy at step 958, then a determination is made as to whether a bus error or timeout flag has been generated at step 959. If an error or timeout has occurred, then the program will proceed to step 973 where the transmission will be terminated and the routine exited. If an error or timeout condition does not exist, the routine will continue at step 955 until an acknowledge bit has been sent by the slave indicating that the data has been received. If the acknowledge bit has been received, then the current command code is transmitted at step 957. It should be understood that when the send message routine is invoked during a critical alarm condition, then the command code word is set to the battery address (see step 935, FIG. 12(b)) and the slave will recognize that only two bytes of data are to be sent. The next step, as indicated at step 960, is a check as to whether the acknowledge bit has been sent, i.e., whether the command code (or battery address) has been received by the slave device. If the acknowledge bit has not been received, then a check is made at step 962 to determine whether a bus error or timeout flag has been generated. If an error or timeout has occurred, then the program will proceed to step 973 where the transmission will be terminated and the routine exited. If an error or timeout condition does not exist, the routine will continue at step 960 until it is acknowledged that the command code (or battery address) has been received. If the acknowledge bit has been received, then the first byte of data is transmitted to the specified address location (see step 935, FIG. 12(b) at step 965. The next step, as indicated at step 966, is a check as to whether the acknowledge bit has been sent, i.e., whether the first byte of command code data has been received by the slave device. If the acknowledge bit has not been received, then a check is made at step 967 to determine whether a bus error or timeout flag has been generated. If an error or timeout has occurred, then the program will proceed to step 973 where the transmission will be terminated and the routine exited. If an error or timeout condition does not exist, the routine will continue at step 966 until it is acknowledged that the first data byte has been received. If the acknowledge bit has been received, then the second byte of data is transmitted to the next address location at step 968. The next step, as indicated at step 969, is a check as to whether the acknowledge bit has been sent, i.e., whether the second byte of command code data has been received by the slave device. If the acknowledge bit has not been received, then a check is made at step 971 to determine whether a bus error or timeout flag has been generated. If an error or timeout has occurred, then the program will proceed to step 973 where the transmission will be terminated and the routine exited. If an error or timeout condition does not exist, the routine will continue at step 969 until it is acknowledged that the second data byte has been received. After the full message has been transmitted by the battery to the slave device, the send message routine is exited.

LED display

As shown in FIG. 2, the battery 10 of the instant invention provides manually controlled four (4) segment light emitting diode (LED) display indicating the relative state of charge 6f the battery (similar to a fuel gauge) with respect to the full.sub.-- cap value. After the capacity calculation, alarm control 152, and charger control 154 routines are performed during each 500 msec period (operating cycle), the system will look for a hardware trigger of the LED display. At any time, a user can initiate the LED display by a switch 35 on the battery 10 as shown in FIG. 2(a). FIG. 15 illustrates the control logic for the LED display.

Pushing the switch 35 will trigger a hardware switch as indicated at step 975 of FIG. 15. If the hardware trigger is set, then the process proceeds to step 977. If the hardware trigger for the LED display is not set, then the current LED display is cleared and the LED display timer is reset at step 992. Afterwards, the LED display routine is exited.

At step 977, a determination is made as to whether the working mode of the LED display will relate to the default value of the adjusted full capacity (full.sub.-- cap), the return of RelativeStateOfCharge(), or, will relate to the design capacity (nom.sub.-- cap) value, as explained above. If the working LED display mode is determined to relate to a full.sub.-- cap basis, then the relative soc is calculated at step 978 normalized with respect to full.sub.-- cap. Otherwise, at step 979, the relative soc is calculated at step 979 normalized with respect to nom.sub.-- cap. Next, at step 980, a counter is set to the relative soc value, and all four LED's are cleared and their bit values initialized. Then, a determination as to whether the counter is above 75% is made at step 981. If the counter is above 75 percent, then all four LED's will be turned on for display indicating>75% charge. If the counter is less than 75%, then the counter is incremented with a 25% increase at step 983 and the LED bits in the LED display register are shifted which will give a corresponding indication of the relative soc when the LED's are turned on. Steps 981 and 983 are repeated up to three (3) times until the condition that the counter is greater than 75 is achieved. After the condition is satisfied, then at step 985, the LED's are turned on (displayed) in accordance with the bit formation in the LED register (not shown). A determination is then made at step 987 if the relative capacity is greater than ten (10) percent. If so, then the program proceeds to step 994. If the relative capacity is determined to be less than 10% then a determination is made at step 989 as to whether the LED display is to flash. Therefore, the LED flashing bit is checked at step 989, and if the bit is not set, then the LED that is displayed to indicate less than 10% relative soc will flash, as indicated at step 991. If the flashing bit is set at step 989, then the LED will flash, and the flashing bit is cleared at step 990. the system will proceed to step 994 where the LED display timer is decremented. Then, a determination is made at step 995 as to whether the LED display timer has timed out. If the LED display timer has timed out, then the hardware trigger bit is cleared at step 996, and the display timer is reset. Otherwise, the LED display routine is exited.

While the invention has been particularly shown and described with respect to the preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention, which should be limited only by the scope of the appended claims.