US 5,604,617 AGrant
Telecommunications Switching Element
Issue Date:1997-02-18
•6 Claims
•5 Drawing Sheets
Abstract
A multi-stage telecommunications switch, such as a "rotator", has 2.sup.n input ports and 2.sup.n output ports, `n` being an integer greater than 1, and is formed from a number n.times.y.sup.(n-1) of y.times.y switching elements where `y` is an integer greater than 1 and the elements are arranged in n stages wherein each switching element within a stage x, where `x` is an integer between 1 and n, changes state every y.sup.(x-1) timeslots to provide switching only in the space domain. The switching elements may be electrical or optical devices.
Metadata
Assignee
- GPT Limited
Inventor
- Nigel J. Burton
Application Information
Application Number:US 2945517
Filing Date:1994-08-23
Priority Date:1993-08-27
Art Unit:267
Classifications
IPC:
H04J 1400
Field of Search:
359385370340117;128;139;1401759;63-64;60;60.1825.79;825.8;825.03;826
Patent Drawings (5 sheets)
Description
Background of the Invention
The present invention relates to a telecommunications switching element referred to as a "rotator" and described in patent applications nos. GB2258360, GB2258366, GB2258581 and GB2258582, corresponding to U.S. application Ser. Nos. 08/030,341, 08/030,231, 08/030,402 and 08/030,166, respectively, imported herein by reference.
Summary of the Invention
According to the present invention there is provided a multi-stage telecommunications switching means having 2.sup.n input and 2.sup.n output ports, where `n` is an integer greater than 1, comprising a number n.times.y.sup.(n-1) of y.times.y switching elements where `y` is an integer greater than 1 arranged in n stages wherein each switching element within a stage x, where x is an integer between 1 and n, changes state every y.sup.(x-1) timeslots to provide switching only in the space domain.
Further there is provided a multi-stage telecommunications switching means as above, having 2.sup.n inputs and 2.sup.n outputs, and wherein y is equal to 2, whereby there are n.times.2.sup.(n-1) switching elements arranged in `n` stages and each switching element within a stage `x`, where x is an integer between 1 and n inclusive, changes state every 2.sup.(x-1) timeslots.
Brief Description of the Drawings
The present invention will now be described, by way of example, with reference to the accompanying drawings, in which:
FIG. 1 shows a rotator input channel map;
FIG. 2 shows a rotator output channel map;
FIG. 3(a) shows a basic 2.times.2 switching device;
FIG. 3(b) shows the device of FIG. 3(a) in the "cross" state;
FIG. 3(c) shows the device of FIG. 3(b) in the "bar" state;
FIG. 4 shows an interconnected array of devices of FIG. 3(a); and
FIG. 5 shows two 4.times.4 rotators interconnected to provide an inverse transformation;
Detailed Description of the Preferred Embodiments
A Rotator is part of an ATM or STM switch fabric and performs a mixing and spatial routing function between its inputs and outputs. The Rotator described as an example has 16 inputs and 16 outputs. The inputs to the Rotator each have 16 slots in a conceptual frame. The Rotator space switches the slots so that each input has a single slot to each output per frame, and consequently each output has one slot from each input.
It is important that the Rotator preferably should introduce no additional delay, and therefore no timeswitching functions are possible. The present invention provides a Rotator function that satisfies the zero-delay requirement.
The invention further allows a migration from electrical to optical technology with no change to the control or timing relationship.
The rotator functionality can be represented by the input and output channel maps shown in FIGS. 1 and 2 respectively.
The input channel map in FIG. 1 shows the 16 inputs to the rotator in the vertical dimension annotated by the numbers 1 to 16, and the 16 timeslots per cycle in the horizontal direction annotated A to P.
One internal cycle from input number 5 is highlighted for explanation. It can be seen that input number 5 is divided into 16 timeslots, A5 to P5. The rotator will take the 16 timeslots and transmit one to each central stage.
In the output channel map, FIG. 2, one cycle to central stage switch 7 is highlighted, and it can be seen that sample C from input number 5 will be transmitted to central switch 7.
Note that all samples remain in their respective columns, i.e. they are not moved in the horizontal plane, which represents the time domain, but only moved in the vertical plane which represents the space domain. Thus no time switching is performed and therefore no additional delay is incurred in the rotator.
The Rotator, as shown in FIG. 4, is implemented by means of multiple interconnected 2.times.2 switching elements (32 in total), FIG. 3(a), which may be in turn be implemented either optically or electrically. The 2.times.2 element has two states, a `cross` state and a `bar` state, shown in FIGS. 3(b) and 3(c) respectively. A simple control interface switches the element between the 2 states. The 32 elements must be interconnected in the manner shown in FIG. 4.
The timing of the control signals `cross` and `bar` with reference to the start of the frame is as shown below, where `B` represents a `bar` and `C` a `cross` signal.
The implementation described performs the required functionality of the Rotator with zero delay (except for propagation delay), and can either be implemented using electronic or optic technology using the same control and timing information. Both Lithium Niobate and Indium Phosphide are suitable materials for optic implementation of the Rotator function.
Using a pair of interconnected Rotators R1, R2, shown in FIG. 5 as 4.times.4 units for this example, such that R2=[R1].sup.-1, i.e. R2 performs the inverse function to R1 leaving the inputs unchanged for each Rotator.
Ad, Bd, Cd, Dd represent the data from inputs A, B, C, D respectively and Ah, Bh, Ch, Dh represent the header information from inputs A, B, C, D respectively.
The header information is switched by R1 to the Header Processing where SOH handling, ATM cell header translation/policing and other functions can be carried out to provide modified headers Ah', Bh', Ch', Dh'. Equivalent delays are then applied to the data by the Delay Unit. The data streams are then reconstituted by the Rotator R2.
Claims
What I claim is:
1. A multi-stage telecommunications switch having 2.sup.n input and 2.sup.n output ports, where `n` is an integer greater than 1, comprising: a number n.times.y.sup.(n-1) of y.times.y switching elements, where `y` is an integer greater than 1, arranged in n stages, wherein each switching element within a stage x, where x is an integer between 1 and n, changes state every y.sup.(x-1) timeslots to provide switching only in the space domain.
2. The switch as claimed in claim 1, having 2.sup.n inputs and 2.sup.n outputs, wherein y is equal to 2, whereby there are n.times.2.sup.(n-1) switching elements arranged in `n` stages and each switching element within a stage `x`, where x is an integer between 1 and n inclusive, changes state every 2.sup.(x-1) timeslots.
3. The switch as claimed in claim 1 wherein each switching element has two states, a first state wherein each input port is connected to a corresponding output port and a second state wherein each input port is cross-connected to an opposite output port.
4. The switch as claimed in claim 1 wherein the switching elements are optical devices.
5. A processing circuit comprising: a first and a second multi-stage telecommunications switch, each switch having 2.sup.n input and 2.sup.n output ports, where `n` is an integer greater than 1, each switch further having a number n.times.y.sup.(n-1) of y.times.y switching elements, where `y` is an integer greater than 1, arranged in n stages, wherein each switching element within a stage x, where x is an integer between 1 and n, changes state every y.sup.(x-1) timeslots to provide switching only in the space domain, wherein the second switch performs a function inverse to that performed by the first switch, and further comprising a header processing unit connected between an output of the first switch and the corresponding input of the second switch.
6. The processing circuit as claimed in claim 5, further comprising delay means between the remaining corresponding outputs of the first switch and inputs of the second switch.