Capacitance Measuring Device

This invention relates to a capacitance measuring device and a method of measuring capacitance.

Presently most practical methods of measuring capacitance require an AC input and output signal. For example, U.S. Pat. No. 5,212,454 describes an arrangement wherein a high frequency voltage signal is applied to a capacitor and the resulting current measured.

An object of the invention is to provide a method and device for measuring capacitance that avoids the need to apply an AC input.

Accordingly the invention provides a capacitance measuring device comprising a MOS transistor having a source, drain, and gate; a first capacitor C.sub.1 connected between said gate and said drain so that charge is coupled from said drain onto said gate; a second capacitor C.sub.2 for connection to a source of gate voltage V.sub.G and connected to said gate; one of said first and second capacitors having a known capacitance and the other of said first and second capacitors having an unknown capacitance; means for applying a variable known DC voltage between said source and drain to cause a saturation current to flow therebetween; and means for determining the ratio .delta.V.sub.G /.delta.V.sub.d for said saturation current, where V.sub.G is the applied gate voltage, and V.sub.d is the drain voltage; said unknown capacitance thereby being derivable from the relationship C.sub.1 /C.sub.2 =-.delta.V.sub.G /.delta.V.sub.d.

In the preferred embodiment, the MOS transistor is an n-channel MOSFET.

The invention makes use of the fact that in an arrangement where the gate is isolated from the gate voltage by a capacitor C.sub.x, and charge is coupled from the drain to the gate by another capacitor C, the amount of charge that is coupled is determined by the ratio C/C.sub.x, or in other words ##EQU1##

The invention thus allows capacitance to be measured using D.C. alone. The device can be integrated on a chip using either CMOS, BICMOS, NMOS, or any technology that can fabricate MOS devices.

The key aspect of this invention is that it can measure, the capacitance using only D.C. measurements.

The invention also provides a method of measuring capacitance, comprising isolating a gate region of a MOS device from exterior biasing with a first capacitor, coupling charge between a drain and said gate of said MOS device with a second capacitor, one of said first and second capacitors having an unknown capacitance, and measuring the rate of change of gate voltage with respect to drain voltage at saturation current to derive said unknown capacitance therefrom.

The invention will now be described in more detail, by way of example only, with reference to the accompanying drawings, in which: FIG. 1 is a circuit diagram of a first embodiment of a device in accordance with the invention; and

FIG. 2 is a circuit diagram of a second embodiment of a device in accordance with the invention.

Referring to FIG. 1, a n-channel MOSFET 1 has a source 2 and substrate 2a connected to ground (GND) and a drain 3 connected to a constant current supply 4. This current supply 4 supplies a saturation current I.sub.ds that flows between the drain 3 and source 2. The drain voltage V.sub.d is measured by a voltage meter 6 connected between the drain 3 and ground (GND).

MOSFET 1 has a gate 5 connected through a capacitor C.sub.x of unknown capacitance to an electrode 8 connected to a source 7 of variable known gate voltage V.sub.G. A capacitor C connects the drain 3 to the gate 5 so as to couple charge from the drain 3 to the gate 5.

This configuration thus allows the drain to place or couple charge on to the gate of the MOS transistor The capacitor C.sub.x attached from V.sub.G to the gate is used to isolate the coupling region (i.e. the gate region) from any exterior biasing. The amount of charge that is coupled is determined by the ratio C/Cx. As this ratio increases the amount of coupling also increases. The magnitude of coupling is monitored through the structures current-voltage characteristics. In order to measure capacitance, the ratio C.sub.x /C is determined from the rate of change of the measured drain voltage with respect to the applied variable gate voltage V.sub.G when the source drain current I.sub.ds is saturated. The unknown capacitance is derived from the relationship ##EQU2##

The measurement is thus performed with the device operating in saturation.

In an alternative embodiment, a p-channel device can be used instead of an n-channel device by switching the polarities of all the voltages.

Extra components can be added for stability, obtaining better accuracy, or for integration purposes.

In a second embodiment shown in FIG. 2, the device, which is otherwise similar to FIG. 1 has two input gate capacitors Cx.sub.2 and Cx.sub.1 in series. Switches 9 and 10 allow the coupling capacitor C no be connected in series selectively either with the series combination of Cx.sub.2 and Cx.sub.1, or Cx.sub.2 alone. In this case, the following relationship holds: ##EQU3## where now C.sub.x1 =(Cx.sub.x1.sup.-1 +Cx.sub.x2.sup.-1).sup.-1

This basic mechanism for coupling charge from C to the gate remains the same as described with reference to FIG. 1.

This above configuration allows one to measure capacitance while making no restrictions on the geometry of the transistor. In the above equation, "on" means the switch is short circuited. It is understood that when one switch is on the other is assumed off.

From the above relationship it will be apparent to the skilled reader that the roles of capacitors C and C.sub.x can be reversed. So long as one is known and the other is unknown, it makes no difference which is which.

The invention described can be used for any application in which capacitance measurements are made. Some specific applications include sensing applications based on capacitance measurons, actuator applications based on capacitance monitoring and driving, basic capacitance meters, CV (Capacitive-voltage) meters, and Charge coupling circuits.