Modulating Method and Demodulating Apparatus

This invention relates to a modulating method and a demodulating apparatus and, more particularly, to a modulating method for modulating data so as to be suited to transmission or recording of data on a recording medium and a demodulation apparatus for reproducing the data by demodulating the modulated coded data resulting from the demodulation.

When transmitting the data or recording the data on the recording medium, such as a magneto-optical disc or an optical disc, the data are modulated so as to be suited for transmission or recording. Block coding has been known as one of such modulating techniques. The block coding consists of blocking an input data string into units (data words) each consisting of m.times.1 bits and translating the data words into codewords, each consisting of n.times.1 bits, in accordance with an appropriate coding rule. The block coding becomes a fixed length code if i=1 and becomes a variable length code if i may assume multiple values, that is if i>1, with the maximum value of i being i.sub.max =r). The code produced by block coding is termed the variable length code (d, k; m, n; r), where i is termed a constraint length, with i.sub.max being equal to the maximum constraint length r, d is the minimum number of the same consecutive symbols, that is a so-called minimum run of O's, and k is the maximum number of the same consecutive symbols, that is a so-called maximum run of O's.

When recording the variable length code on, for example, an optical disc, it is modulated into so-called non-return to zero code (NRZ code) and recorded based upon the NRZ modulated variable length code, referred to hereinafter as the recording waveform data string. With the minimum length between transitions and the maximum length between transitions of the recording waveform data string being T.sub.min and T.sub.max, respectively, it is desirable from the viewpoint of the recording density that the minimum length between transitions T.sub.min be long, that is that the minimum run d be large, while it is desirable from the viewpoint of clock reproduction and jitter that the maximum length between transitions T.sub.max be short, that is that the maximum run k be small. A variety of modulation methods have been proposed with which the above conditions are met.

In the case of an optical disc having audio data recorded thereon, that is a so-called compact disc (CD), a so-called eight-to-fourteen modulation (EFM) is employed. This modulation method is a variable length code (2, 10; 8, 17; 1) in which, if the interval between bits (bit length) of the recording waveform data string is T, the minimum length, between transitions T.sub.min is (2+1)T or 3T. If the interval between bits of the data string is T1, the minimum length between transitions T.sub.1min is ((8/17).times.3)T.sub.1 or 1.41T.sub.1. In the following description, the indication of the bit length T is directly followed by the bracketed indication of the corresponding bit length T.sub.1. The maximum length between transitions T.sub.max (T.sub.1max) is 11T (5.18T.sub.1,), while the window margin T.sub.W, which stands for the allowable jitter, is represented as (m/n).times.T, and has a value equal to (8/17)T or 0.47T. With such a CD, it may be contemplated to diminish the minimum pit length corresponding to the minimum length between transitions T.sub.min (T.sub.1max) on the optical disc. However, if the minimum pit length becomes excessively shorter than the spot size of the laser beam, it becomes difficult to detect the pits so that errors tend to be produced. On the other hand, limitations are imposed on increasing the recording density by diminishing the wavelength of the laser light source for diminishing the spot size.

With the above in view, there has also been developed a modulation method whereby the minimum pit length on the optical disc, that is the minimum length between transitions T.sub.min (T.sub.1min), may be increased without diminishing the information volume.

For example, as shown in table 1, there has also been proposed a variable length code (4, 22; 2, 5; 5) in which the minimum length between transitions T.sub.min is increased to 5T (2T.sub.1) for increasing the recording density as compared to EFM. This modulation method is referred to hereinafter as variable five modulation (VFM). With the VFM, the maximum length between transitions T.sub.max (T.sub.1max) increased to 23T (9.2T.sub.1,) as compared to the maximum length between transitions T.sub.max (T.sub.1max) of EFM which is equal to 11T (5.18T.sub.1,). That is, the VFM is not advantageous from the viewpoint of clock reproduction and jitter and renders the designing of the apparatus difficult.

In other words, although it is necessary to increase the minimum length between transitions T.sub.min for increasing the recording density, it is necessary to reduce the maximum length between transitions T.sub.max simultaneously to as small a value as possible in order to assure the operating reliability of the apparatus. That is, a smaller value of the ratio of the maximum length between transitions to the minimum length between transitions is desirable. Specifically, the ratio T.sub.max /T.sub.min =11T/3T=3.67 for EFM, while the same ratio for VFM is 23T/5T=4.60.

In sum, while it is necessary to increase the minimum length between transitions T.sub.min (T.sub.1min), that is the minimum run d, of the variable length code produced on modulation in order to increase the recording density for a recording medium, such as an optical disc, the maximum length between transitions T.sub.max (T.sub.1max), that is the maximum run k, is undesirably increased with the conventional modulation methods.

In view of the above-described status of the art, it is a principal object of the present invention to provide a modulation method whereby the minimum run d may be enlarged as compared to that of EFM to assure high density recording, and the maximum run k may be diminished as compared to that of VFM, and a demodulating apparatus whereby the variable length code resulting from such modulation may be demodulated in order to reproduce the data.

According to a first modulation method of the present invention, data having a minimum run of 4 or more and a basic data length of m bits is converted into a variable length code (d, k; m, n; r) having a basic code length of n bits, which has a bit at a preset position of a codeword which has the possibility of giving an infinite number (.infin.) for the maximum run k and a bit at a preset position of a codeword which gives the maximum number of "0"s consecutive from the LSB towards upper order bit side of the codeword is set as being an unfixed bit.

According to a second modulation method of the present invention, the unfixed bit as defined in the first modulation method is set to "1" when d or more bits are consecutive to the unfixed bit.

A modulation apparatus according to the present invention inversely converts the variable length code (d, k; m, n; r) having the minimum run d equal to 4 or more and the basic codeword length of n bits, and including an unfixed codeword having an unfixed bit at a preset position the value of which is determined by the number of "0"s consecutive to such bit, and includes detecting the codeword having the unfixed bit, means for determining the constraint length of the variable code depending on the results of detection by the unfixed codeword detection means, and inverse conversion means for inverse converting the variable length code into data based on the constraint length i from the constraint length decision means with the aid of inverse conversion tables of inverse converting n.times.i bit variable length code into m.times.i bit data.

With the first modulation method of the present invention, when converting data having the minimum run d of 4 or more and the basic data length of m bits into the variable length code (d, k; m, n; r) having the basic code length of n bits, the bit at a preset position of a codeword which is likely to give an infinite number (.infin.) of the maximum run k and the bit at a preset position of a codeword which gives the maximum number of "0"s consecutive from its least significant bit towards the upper order bit side is an unfixed bit the value of which is fixed depending on the number of "0"s consecutive thereto.

With the second modulation method according to the present invention, the unfixed bit is set to "1" when d or more bits are consecutive to the unfixed bit.

In this manner, the minimum length between transitions T.sub.min may be increased to 5T from 3T for EFM, thereby improving the recording density. In addition, the distributions of the minimum length between transitions T.sub.min may be concentrated in the vicinity of 5T. On the other hand, the maximum length between transitions T.sub.max may be diminished to, for example, 19T, from 23T for VFM having the same value of the minimum length between transitions T.sub.min, thereby simplifying the designing of the apparatus from the aspects of clock reproduction and jitter. In addition, the ratio of the maximum length between transitions to the minimum length between transitions may be reduced to 3.8 from 4.6 for VFM.

With the demodulation apparatus according to the present invention, in which the variable length code (d, k: m, n; r) having a minimum run d of 0.4 or more and the basic code length of n bits, and including a codeword having an unfixed bit the value of which is determined by the number of "0"s consecutive to the unfixed bit, is inverse converted into data having a basic data length of m bits, the codeword braving the unfixed bit is detected, and the constraint length i of the variable length code is determined based upon the results of detection. The variable length code is then inverse-converted into data, on the basis of the constraint length i, with the aid of inverse conversion tables for inverse conversion of the n.times.i bit variable length code into m.times.i bit data. In this manner, the variable length code including variable length codeword may be demodulated into data. In addition, the inverse conversion tables for inverse conversion of the variable length code into data and hence the circuit scale may be reduced in size as compared to those of VFM, thereby decreasing the cost.

FIG. 1 is a block circuit diagram showing a circuit arrangement for a modulating apparatus according to the present invention.

FIG. 2 is a graph showing the distribution of the transition lengths with the modulating method according to the present invention as compared to that with the conventional VFM.

FIG. 3 is a block diagram showing a concrete circuit arrangement of a demodulating apparatus according to the represent invention.

Referring to the drawings, preferred embodiments of the modulating method and the demodulating apparatus according to the present invention are explained in detail. In these embodiments, the present invention is applied to a modulating apparatus for translating data into variable length code (d, k; m, n; r) and a demodulating apparatus for performing an inverse operation of the above-mentioned translating operation. FIGS.1 and 3 illustrate circuit arrangements for the modulating apparatus and the demodulating apparatus, respectively.

Referring to FIG. 1, the modulating apparatus includes a shift register 11 for shifting data based on m bits as a unit, and an encoding circuit 12 for discriminating the constraint length i (i=1 to r) of data supplied from the shift register 11, based upon m bits as a unit, and for detecting data which is to be transformed into a codeword including an unfixed bit, referred to hereinafter as an unfixed codeword. The apparatus also includes conversion tables aweigh, i being 1 to r, for translating data having a minimum run d of not less than four and a basic data length of m bits into a variable length code (d, k; m, n; r) having a basic codeword length of i bits, and a selector 13 for selecting one of the conversion tables 14.sub.1 based upon the constraint length i from the encoding circuit 12 for supplying m.times.i bit data to the conversion tables 14.sub.1. The apparatus also includes an unfixed bit processing circuit 16.sub.1 for setting a bit of a pre-set position of a codeword from the conversion table 14.sub.1 which gives an infinite number (.infin.) of the maximum run k and a bit of a pre-set position of a codeword from the conversion table 14.sub.1 having the maximum number of consecutive 0's from the least significant bit towards the upper order bit side and for setting the value of the unfixed bit to 1 when d or more bits are consecutive to the unfixed bit, and a selector 15 for selecting one of the unfixed bit processing circuits 16.sub.1 based upon the results of detection from the encoding circuit 12 and supplying the unfixed bit to the selected one of the unfixed bit processing circuit 16.sub.i. The apparatus also includes a multiplexor 17 for commutatively selecting the codeword from the selector 15 or the codeword from the unfixed bit processing circuit 16.sub.1 for outputting the selected codeword as serial data, and a buffer memory 18 for temporarily storing the variable length codeword from the multiplexor 17 and outputting the stored codeword as the modulated codeword at a pre-set transfer rate. Finally, the apparatus includes a clock generator 19 for supplying clocks to the buffer memory 18.

Now, assuming that the variable length code (d, k; m, n; r) is the code (4, 18; 2, 5; 6), with a minimum d run of not less than 4, a maximum run k of 0's equal to 18 bits, a basic data length m of 2 bits, a basic codeword length n of 5 bits and with a maximum constraint length r of 6 bits. Then, as shown in Table 2, the conversion table 14.sub.1 is a conversion table for converting 2.times.1 bits or 2 bits, with the constraint length i equal to 1, into the codeword having the length of 5.times.1 bits or 5 bits, referred to hereinafter as a 2-5 conversion table. The conversion table 14.sub.2 is a conversion table for converting 4 bits, with the constraint length i equal to 2, into a 10-bit codeword, referred to hereinafter as a 4-10-conversion table. In a similar manner, the conversion tables 14.sub.3 to 14.sub.6 are a 6-15 conversion table, a 8-20 conversion table, 10-25 conversion table and a 12-30 conversion table, respectively.

In these conversion tables, some of the conversion tables have a codeword the maximum run k of which becomes equal to .infin. if the unfixed bit is set to 0. An example is the conversion table 14.sub.1 (2-5 conversion table) that has a coding rule for converting data "01" in binary representation into a codeword "00*00" in which a bit as from the least significant bit (LSB) up to the m'th bit which, if set to 1, will give the least value of the maximum length of transition T.sub.max, becomes an unfixed bit, where * is fixed to 1 or 0 depending on the number of 0's consecutive thereto. The conversion table 14.sub.2 (4-10 conversion table) has a coding rule of converting data "1011" into a codeword "00000 00*00". The conversion table including a codeword in which the number of 0's consecutive from the LSB towards the upper order side becomes maximum, such as the conversion table 14.sub.4 (8-20 conversion table), has a coding rule of converting data "00000100" into a codeword "00000 00000 00100 00*00". These conversion tables are implemented by, for example, a ROM in which the values of the codewords are previously stored with the data as addresses.

The shift register 11 is supplied with data obtained by processing video signals with data compression operations, such as predictive coding, discrete cosine transform, Huffman coding or the like. The shift register 11 shifts the input data, based upon m bits as a unit, and outputs the data to the encoding circuit 12.

The encoding circuit 12 discriminates the constraint length i of the input data supplied thereto based upon m bits as a unit. Specifically, the encoding circuit 12 checks if data supplied thereto on the 2-bit basis is presenting the data portion of the 2-5 conversion table shown in Table 2. That is, the encoding circuit determines the constraint length i to be 1 when the data is "11", "10" and "01" and, if the data is "00", it adds the next two bits to produce 4 bits, that is it shifts the input data to the next rank. If data "10" and data "11" are consecutive to each other in this order, the constraint length i is determined to be 2 in order to prevent the maximum run of the variable length code produced on conversion from becoming infinite (.infin.).

The encoding circuit 12 checks if 4-bit data supplied thereto is present in a data portion of the 4-10 conversion table shown in Table 2. That is, the encoding circuit determines the constraint length i to be 2 when the data is "0011", "0010"' and "1011" and, if the data is "0001" or "0000", it shifts the input data to the next rank.

In a similar manner, the encoding circuit 12 determines the data portions of the 6-15 conversion table, 8-20 conversion table or the 10-25 conversion table in which the data supplied on the 2-bit basis from the shift register 11 is present, and accordingly determines the constraint length i=3 to 6.

The encoding circuit 12 also detects data "01", "1011" and "00000100" and detects these data as being data in which the codeword produced on conversion becomes an unfixed codeword.

The selector 13 then selects the conversion table 14i based upon the constraint length i supplied from the encoding circuit 12, and routes m.times.i bit data to the thus selected conversion table 14i.

Specifically, the selector 13 selects the conversion table 14, when i=1 and routes 2-bit data "11", "10" and "01" to the thus selected conversion table 14.sub.i.

The selector 13 selects the conversion table 1.sub.2 when i=2 and routes 4-bit data "0011", "0010" and "1011" to the thus selected conversion table 14.sub.2. If the data "10" and data "11" are consecutive in this order, the selector selects the conversion table 14.sub.2 and routes 4-bit data "1011" to the conversion table 14.sub.2.

In a similar manner, the selector 13 selects the conversion tables 14.sub.3 to 14.sub.6, associated with the value of the constraint length i, if the constraint length i is 3 to 6, and routes 6-12 bit data to the thus selected conversion tables 14.sub.3 to 14.sub.6.

The conversion tables 14.sub.1 to 14.sub.6 have the 2-5, 4-10, 6-15, 8-20, 10-25 and 12-30 conversion tables, as explained hereinabove, and reads out the codewords of the codeword portion, using the data supplied via the selector 13 as the readout addresses.

The result is that if the data is "11", "10" and "01", the conversion table 14.sub.1, outputs the codewords "10000", "01000" and an unfixed codeword "00*00", respectively

If the data is "0011", "0010" and "1011", the conversion table 14.sub.2 outputs the codewords "00010 00000", "00001 00000" and an unfixed codeword "00000 00*00", respectively.

If the data is "000111", "000110", "000011", the conversion table 14.sub.3 outputs the codewords "00010 00010 00000", "00010 00001 00000",'. - "00000 00001 00000".

If the data is "00001011", "00001010 00000100", the conversion table 14.sub.4 outputs the codewords "00010 00010 00010 00000", "00010 00010 00001 00000" and an unfixed codeword "00000 00000 00100 00*00", respectively.

If the data is "0000001111", "0000001110 0000000001" the conversion table 14.sub.5 outputs the codewords "01000 00000 00000 00010 00000", "01000 00000 00000 00001 00000", "00000 00000 00100 00001 00000", respectively.

If the data is "000000000011" "000000000010". . . "000000000000", the conversion table 14.sub.6 outputs the codewords "00010 00010 00010 00010 00010 00000", "00010 00010 00010 00010 00001 00000". . . "00010 00010 00001 00001 00001 00000", respectively.

That is, these conversion tables 14.sub.1 to 14.sub.6 output variable length codewords and route these codewords to the selector 15. The selector 15 selects the unfixed bit processing circuit 16j.sub.i, based upon the results of detection of the unfixed codeword, supplied from the encoding circuit 12, and routes the unfixed codeword to the unfixed bit processing circuit 16.sub.j, while routing the codewords other than the unfixed codeword to the multiplexor 17.

Specifically, the selector 15 selects, when supplied with an unfixed codeword "00*00" containing the unfixed bit "*", the unfixed bit processing circuit 16.sub.1 based upon the results of detection of the unfixed codeword, and routes the unfixed codeword "00*00" to the unfixed bit processing circuit 16.sub.j

When supplied with the unfixed codeword "00000 00*00", for example, the selector 15 selects the unfixed bit processing circuit 16.sub.2, and routes the unfixed codeword "00000 00*00" to the unfixed bit processing circuit 16.sub.2.

When supplied with the unfixed codeword "00000 00000 00100 00*00", for example, the selector 15 selects the unfixed bit processing circuit 16.sub.4, and routes the unfixed codeword "00000 00000 00100 00*00" to the unfixed bit processing circuit 16.sub.4.

The unfixed bit processing circuit 16, sets the unfixed bit of the unfixed codeword "00*00", that is the third bit as counted from the LSB being the first bit, to 1 when not less than d "0" bits are continuously adjacent to the unfixed bit. Specifically, if the unfixed codeword "00*00" is followed by the codeword "10000", the processing circuit 16.sub.i, sets the unfixed codeword "00*00" fixedly to a codeword "00000". On the other hand, if the codeword "00010 00000" is followed by the unfixed codeword "00*00", the unfixed codeword is set fixedly to a codeword 00100.

Also the unfixed bit processing circuit 16.sub.2 sets the unfixed codeword "00000 00*00" fixedly to a codeword "00000 00100" or to a codeword "00000 00000" depending on the number of "0"s consecutive to the unfixed bit.

Furthermore, the unfixed bit processing circuit 16.sub.4 sets the unfixed codeword "00000 00000 00100 00*00" fixedly to a codeword "00000 00000 00100 00100" or to a codeword "00000 00000 00100 00000" depending on the number of "0"s consecutive to the unfixed bit.

The multiplexor 17 multiplexes the codeword from the selector 15 and the codeword fixed by the unfixed bit processing circuit 16.sub.j to produce serial data which is supplied to the buffer memory 18.

The buffer memory 18 transiently stores the codewords supplied thereto from the multiplexor 17 and outputs the stored codewords as the codewords at a pre-set transfer rate in relation to the clocks supplied from the clock generator 19.

That is, if the bit length of the NRZI modulated variable length codeword, referred to herein as the recording waveform data string, is T, the minimum length between transitions T.sub.min with the variable length code (4, 18; 2, 5; 6) of the present embodiment is (4+1)T or 5T. The maximum length between transitions T.sub.max is (18+1)T or 19T, while the window margin T.sub.W, which gives an allowable jitter value represented by (m/n).times.T, has a value equal to 2/5T or 0.4T. The ratio of the maximum length between transitions to the minimum length between transitions, as referred to in connection with the prior art, is 3.8 (T.sub.max /T.sub.min =19T/5T).

In other words, with the present variable length code (4, 18; 2, 5; 6), the minimum length between transitions T.sub.min may be increased to 5T from the minimum length between transitions T.sub.min of the eight to fourteen modulation (EFM), that is the variable length code (2, 10; 8, 17; 1), which is 3T, thus improving the recording density. In addition, the distribution of the minimum length between transitions T.sub.min may be concentrated in the vicinity of 5T, as shown for example in Table 3 and FIG.2. Specifically, as shown in FIG. 2, the occurrences of 5T and 6T may be increased by approximately 17% and 14%, respectively, as compared to those in the case of variable five modulation (VFM). That is, for a variable length code (4, 22; 2, 5; 5) referred to in connection with the prior art, the mean length between transitions, which is the total number of bits divided by the number of times of transitions, may be decreased to 7.82 from 8.21 for VFM.

In addition, with the present variable length code (4, 18; 2, 5; 6), the maximum length between transitions T.sub.max may be diminished to 19T, as compared to the maximum length between transitions T.sub.max equal to 23T for VFM having the same value for the minimum length between transitions T.sub.min. The design of the apparatus is thereby simplified from the standpoint of clock reproduction and jitter. Further, the ratio of the maximum length between transitions to the minimum length between transitions may be diminished to 3.8 as compared to the value of the same ratio of 4.6 for VFM.

Also, as may be seen from tables 1 and 2, the conversion tables 14.sub.1 to 14.sub.6 of the variable length code (4, 18; 2, 5; 6) may be rendered smaller than those for VFM.

It is also noted that, if the bit length of the data string is T.sub.1, the minimum length between transitions T.sub.1min and the maximum length between transitions T.sub.1max, based on the bit length T.sub.1, as a reference, are 2.0T.sub.1, and 7.6T.sub.1, respectively.

The modulation method according to the present invention is not limited to the above-described embodiment. For example, the variable length code may also be a variable length code (4, 19; 2, 5; 5) which is inclusive of unfixed bits such as those in unfixed codewords "00*00", "00000 00*00", "00000 00000 00100 00*00" and "00000 00000 00010 000*0" and which is made up of a 2-5 , 4-10. 6-15, 8-20 and 10-25 conversion tables. In this case, the minimum length between transitions T.sub.min, the maximum length between transitions T.sub.max, window margin T.sub.W and the ratio of the maximum length between transitions to the minimum length between transitions are equal to 5T (2.0T.sub.i, 20T (8.0T.sub.1,), 0.4 and 4.0, respectively, such that the maximum length between transitions T.sub.max and the ratio of T.sub.max to T.sub.min may be smaller than those for VFM.

Table 4 shows another example of the conversion tables, which may be employed in the modulation method according to the present invention.

The other embodiments of the conversion tables applicable for the modulation method according to the present invention are hereinafter explained.

Table 5 also shows a conversion table of the variable length code (4, 18; 2, 5; 5), which represents an example in which the size is reduced by employing a large number of unfixed bits *.

Table 6 shows a conversion table for the variable length code (4, 19; 2, 5; 6). Although the size is enlarged as compared to those shown in tables 2 and 4, the number of unfixed bits * is diminished to avoid complexity of operation in order to achieve a more favorable hardware configuration

Table 7 shows a conversion table for the variable length code (4, 20; 2, 5; 5). Although T.sub.max becomes larger than that with the other codes, the size may be reduced.

The modulation apparatus is hereinafter explained.

The present demodulation apparatus includes an unfixed codeward detection circuit 21 for detecting a codeword including an unfixed bit from the variable length code (d, k; m, n; r) having a minimum run d of 4 and a basic codeword length of n bits, with the unfixed bit being at a pre set position as determined by the number of "0"s consecutive to the preset bit position, and constraint length determining circuits 22a, 22b, for determining the constraint length i of the variable length code based upon the results of detection by the unfixed codeword detection circuit 21. The apparatus also includes inverse conversion tables 24a.sub.i, 24b.sub.1 for inverse conversion of the n.times.i bits of the variable length code into m.times.i data, where i=1 to r, and selectors 23a, 23b for selecting the inverse conversion tables 24a.sub.i, 24b.sub.1 based upon the constraint length i from the constraint length determining circuits 22a, 22b and supplying the n.times.i bit variable length codewords to the selected inverse conversion tables 24ai, 24b.sub.i. The apparatus also includes multiplexors 25a, 25b for commutatively selecting data from the inverse conversion tables 24a.sub.i, 24b.sub.1 and outputting the selected data as serial data, and a buffer memory 26 for transiently storing data from the multiplexors 25a and 25b and outputting the stored data as playback data. Finally, the apparatus includes a phase locked loop (PLL) 27 for reproducing clocks based upon the variable length code and supplying the clocks to the buffer memory 26.

Assuming that the variable length code (d, k; m, n; r) is the variable length code (4, 19; 2, 5; 5) in which the minimum run d is 4 bits, the maximum run k is 19 bits, the basic data length m is 2 bits, the basic codeword length n is 5 bits and the maximum constraint length r is 5, the inverse conversion tables 24a.sub.1, 24b.sub.1, on the whole are inverse conversion tables corresponding to the 2-5 conversion tables shown in table 4, i.e., is inverse conversion tables each having a constraint length i equal to 1 and adapted for converting a 5-bit codeword into 2-bit data, referred to hereinafter as 5-2 conversion tables. Of these inverse conversion tables, the inverse conversion table 24a.sub.1, is for codewords liable to unfixed codewords, that is codewords in which five bits as counted from the MSB are "00000" or "00100", whereas the inverse conversion table 24b.sub.1 for other codewords, that is codewords in which five bits as counted from the MSB are "10000" or "01000".

On the other hand, the inverse conversion tables 24a.sub.2, 24b.sub.2 on the whole are inverse conversion tables corresponding to the 4-10 conversion tables shown in table 4, that is inverse conversion tables each having a constraint length i equal to 2 and adapted for converting a 10-bit codeword into 4-bit data, referred to hereinafter as 10-4 inverse conversion tables. Of these inverse conversion tables, the inverse conversion table 24a.sub.2 is for codewords liable to unfixed codewords, that is a codeword in which five bits as counted from the MSB are "00000", "00001" whereas the inverse conversion, tables 24b.sub.2 is for other codewords, that is codewords in which five bits as counted from the MSB are "00010, "00001".

In a similar manner, the inverse conversion tables 24a.sub.3 and 24b.sub.3 comprise 15-6 inverse conversion tables having a constraint length i equal to 3 and adapted for converting 15-bit codewords into 6-bit data, while the inverse conversion tables 24a.sub.4, 24b.sub.4 comprise 20-8 inverse conversion tables having a constraint length i equal to 4 and adapted for converting 20-bit codewords into 8-bit data, and the inverse conversion tables 24a.sub.5, 24b.sub.5 comprise 25-10 inverse conversion tables having a constraint length i equal to 5 and adapted for converting 25-bit codewords into 10-bit data.

Referring to FIG. 3, the unfixed-bit detection circuit 21 is made up of an unfixed pattern detection circuit 21a for detecting a 5-bit pattern including an unfixed bit, referred to hereinafter as an unfixed pattern, and an unfixed codeword decision circuit 21b for detecting the unfixed codeword based upon the results of detection from the unfixed pattern detection circuit 21a, These circuits are fed with variable length codewords corresponding to the data reproduced from the recording medium and subsequently processed with NRZI demodulation, error correction or the like.

The unfixed pattern detection circuit 21a detects the unfixed patterns based upon a group of 5 bits from the leading end as a unit of detection. Specifically, there are two patterns likely to unfixed patterns, that is patterns "00000" and "00100". The detection circuit 21a detects these patterns "00000" and "00100" and routes the results of detection to the unfixed codeword discrimination circuit 21b.

When the unfixed codeword discrimination circuit 21b detects the pattern "00100", it determines the pattern to be an unfixed codeword "00*00". When the discrimination circuit detects the pattern "00000", it combines the pattern with the next 5-bit pattern to produce a 10-bit pattern and checks if the 10-bit pattern corresponds to patterns "00000 10000", "00000 01000" or "00000 00100". If the 10-bit pattern corresponds to the patterns "00000 10000" or "00000 01000', the discrimination circuit determines the first 5-bit pattern "00000" to be an unfixed codeword "00*00". If the 10-bit pattern corresponds to the pattern "00000 00100", the discrimination circuit determines the 10-bit pattern "00000 00100" to be an unfixed codeword "00000 00*00".

In a similar manner, the discrimination circuit 21b detects unfixed codewords, such as "00000 00000 00100 00*00" or "00000 00000 00010 000*0" as it appends 5 bits each time, and routes the results of detection of the unfixed codeword to the constraint length decision circuits 22a, 22b.

Based upon the results of detection of the unfixed codewords, supplied from the unfixed codeword discrimination circuit 21b, the constraint length discrimination circuits 22a and 22b determine the constraint length i of the unfixed codeword and the constraint length i of the codewords other than the unfixed codewords, respectively.

Based upon the constraint length i from the constraint length discrimination circuits 22a, 22b, the selectors 23a, 23b select the inverse conversion tables 24a.sub.i, 24b.sub.1 and routes n.times.i bit variable length codewords to the thus selected inverse conversion tables 24a.sub.i, 24b.

Specifically, when i=1, for example, the selector 23a selects the inverse conversion table 24a.sub.1 and routes 5-bit codewords 00000" or "00100" to the thus selected inverse conversion table 24a.sub.1, while the selector 23b selector the inverse conversion table 24b.sub.1 and routes 5-bit codewords "10000" or "01000" to the thus selected inverse conversion table 24b.sub.1.

On the other hand, when i=2, for example, the selector 23a selects the inverse conversion table 24a and routes 10-bit codewords "00000 00000" or "00000 00100" to the thus selected inverse conversion table 24a.sub.2, while the selector 23b selects the inverse conversion table 24b.sub.2 and routes 10-bit codewords "00010 00000" or "'00001 00000" to the thus selected inverse conversion table 24b.sub.2.

In a similar manner, when the constraint length i is 3 to 5, the selectors 23a, 23b select the inverse conversion tables 24a.sub.3 to 24a.sub.5 and 24b.sub.3 to 24b.sub.5 and routes 15 to 25 bit codewords to the selected inverse conversion tables 24a.sub.3 to 24a.sub.5 and 24b.sub.5.

The inverse conversion tables 24a.sub.1 to 24a.sub.5 and 24b.sub.1 to 24b.sub.5 each have a 5-2, 10-4, 15-6, 20-8 and 25-10 inverse conversion, tables, and read out data of the data portions shown in table 4, using the codewords from the selectors 23a and 23b as the readout addresses.

The result is that, for the codewords "10000", "01000" and "00*00", the inverse conversion table 24b, outputs data "11" and "10" respectively, while the inverse conversion table 24a.sub.2 outputs data "1011".

For the codewords "00010 00000", "00001 00000" and "00000 00*00", the inverse conversion table 24b.sub.2 outputs data "0011" and "0010", while the inverse conversion "table 24a.sub.2 outputs data "1011".

For the codewords "00010 00010 00010 00000", "00010 00001 00000", "00000 00001 00000", the inverse conversion table 24b.sub.5 outputs data "000111", "0001010", "00011".

For the codewords "00010 00010 00010 00000", "00010 00010 00001 00000", "00000 00000 00010 00*00", the inverse conversion table 24b.sub.4 outputs data "00001011", "00001010", - "00000101", while the inverse conversion table 24b.sub.4 outputs data "00000100" and "00000011".

For the codewords "00010 00010 00010 00010 00000", "00010 00010 00010 00001 00000, "00000 00000 00010 00001 00000", the inverse conversion table 24b.sub.5 outputs data "0000001101", "0000001010", "0000000000.

That is, 2.times.i bit data, as inverse converted from 5.times.i bit variable length codewords, are outputted from these inverse conversion tables 24a.sub.1, to 24a.sub.5 and 24b.sub.1, to 24b.sub.5 and routed to the multiplexors 25a and 25b.

The multiplexors 25a and 25b multiplex the data routed from the inverse conversion tables 24a.sub.1, to 24a.sub.5 and 24b.sub.1, to 24b.sub.5 and transmit the resulting data as serial data to the buffer memory 26.

On the other hand, the PLL 27 reproduces clocks based upon the variable length codewords, and transmits the reproduced clocks to the buffer memory 26.

The buffer memory 26 temporarily stores data supplied thereto from the multiplexors 25a, 25b and outputs the stored data at a preset rate as playback data in a timed relation to the clocks supplied thereto from the PLL 27. These output data are processed, for example, with inverse DCT, predictive decoding or the like, for reproducing video signals.

With the present demodulation apparatus, the variable length code including an unfixed codeword into data may be demodulated by detecting the codeword having the unfixed bit, determining the constraint length i of the codeword of the variable length code based upon the results of detection, and inverse-converting the codeword into data based upon the constraint length i with the aid of the inverse conversion tables for inverse converting the n.times.i bit variable length code into m.times.i bit data. With the present demodulating apparatus, similarly to the modulation apparatus, the inverse conversion tables 24a.sub.1 to 24b.sub.5 and 24b.sub.1 tl 255 and hence the circuit size may be reduced as compared to that of the VFM. In addition, since the maximum length between transitions T.sub.max may be diminished as compared to that of VFM, the PLL 27 may be improved in reliability.