Apparatus and Method for a NMOS Redundancy Fuse Passgate Circuit Using a VPP Supply

1. Field of the Invention

This invention relates generally to data processing system integrated circuit components and, more particularly, to the redundancy fuse circuits typically used in dynamic random access memory (DRAM) circuits to choose between a logic signal and the complement of the logic signal.

2. Description of the Related Art

An example of a redundancy passgate circuit implemented in complementary metal oxide semiconductor (CMOS) technology, according to the related art, is shown in FIG. 1. The signal Ax.sub.-- is applied to a first conduction terminal of passgate transistor P11. The second conduction terminal of passgate transistor P11 is coupled to the OUTPUT signal terminal. The signal Ax is applied to a first conduction terminal of passgate transistor P12, while a second conduction terminal of passgate P12 is coupled to the OUTPUT signal terminal. The n-channel gate of passgate transistor P11 is coupled to the p-channel gate of passgate P12, to a drain terminal of p-channel transistor T13, and to a drain terminal of n-channel transistor T14 and to a gate terminal of n-channel transistor T15. The n-channel terminal of passgate transistor P12 is coupled to the p-channel gate of passgate P11, to a gate terminal of p-channel transistor T13, to a gate terminal of n-channel transistor T14, to a drain terminal of n-channel transistor T15, to a first terminal of fuse F11, and to a drain terminal of n-channel transistor T12. The SET signal terminal is coupled to a gate terminal of n-channel transistor T12 and to a gate terminal of p-channel transistor T11. A source terminal of n-channel transistor T12, a source terminal of transistor T15, and a source terminal of transistor T14 are coupled to ground terminal. A drain terminal of transistor T11 is coupled to a second terminal of fuse F11, while a source terminal of transistor T11 is coupled to the supply terminal. A source terminal of transistor T13 is coupled to the power supply terminal.

Previous generations of dynamic random access memory units have implemented redundancy fuse circuits using CMOS passgates, such as illustrated in FIG. 1, to chose between a binary logic signal and its complement logic signal. But as the amount of redundancy has been increased on the DRAMs, a need has been felt for passgate circuits operating at higher frequencies which have lowered gate capacitance.

The foregoing and other features are accomplished, according to the present invention, by a redundancy fuse passgate circuit which is implemented in n-channel metal oxide semiconductor (NMOS) technology and which requires an additional (pumped) voltage supply (VPP). The set terminal applies a signal to the fuse circuit. In response to the set terminal signal, the fuse circuit applies a signal to the input terminal of an inverting amplifier. The input terminal and the output terminal of the inverting amplifier apply signals to the gate terminals of the transistors which select the complementary signals for transmission therethrough to the output terminal.

These and other features of the present invention will be understood upon reading of the following description in conjunction with the Figures.

FIG. 1 is a schematic circuit diagram of a redundancy passgate circuit according to the related art.

FIG. 2 is a schematic circuit diagram of a redundancy passgate circuit according to the present invention.

FIG. 3 is a graph comparing a response time of a passgate according to the present invention to the response time of a prior art circuit for a 0.fwdarw.1 logic signal transition.

FIG. 4 is a graph comparing the response time of a passgate according to the present invention to the response time of a prior art circuit for a 1.fwdarw.0 logic signal transition.

1. Detailed Description of the Drawings

FIG. 1 has been described with reference to the related art.

Referring now to FIG. 2, a redundancy passgate circuit according to the present invention is shown. Signal Ax.sub.-- is applied to a first conduction terminal of n-channel semiconductor field effect transistor T12, while signal Ax is applied to a first conduction terminal of n-channel semiconductor field effect transistor T22. A second conduction terminal of transistor T21 and a second conduction terminal of transistor T22 are coupled to the OUTPUT signal terminal. A SET signal terminal is coupled to a gate terminal of n-channel semiconductor field effect transistor T24 and to a gate terminal of p-channel semiconductor transistor T23. A source terminal of transistor T23 is coupled to the SUPPLY terminal while the drain terminal of transistor T23 is coupled to a first terminal of fuse F21. A source terminal of transistor T24 is coupled to the ground terminal while the drain terminal of transistor T24 is coupled to a second terminal of fuse F21, to a drain terminal of n-channel semiconductor field effect transistor T25, to a gate terminal of n-channel semiconductor field effect transistor T27, and to a gate terminal of p-channel semiconductor filed effect transistor T26. The source terminal of transistor T25 is coupled to the ground terminal. The gate terminal of transistor T25 is coupled to an input terminal of inverting amplifier I21, to drain terminal of transistor T26, to a drain terminal of transistor T27, and to a gate terminal of n-channel semiconductor field effect transistor T28. A source terminal of transistor T27 is coupled to the ground terminal, while the drain terminal of transistor T26 is coupled to the supply terminal. The source terminal of transistor T28 is coupled to the ground terminal, while the drain terminal of transistor T28 is coupled to a drain terminal of p-channel semiconductor field effect transistor T29 and to a gate terminal of p-channel filed effect transistor T30. The source terminals of transistors T29 and T30 are coupled to the VPP terminal. The drain terminal of transistor T30 is coupled to the gate terminal of transistor T29, to the drain terminal of n-channel semiconductor field effect transistor T31, to the input terminal of inverting amplifier I22, and to the gate terminal of transistor T21. The output terminal of inverting amplifier I22 is coupled to the gate terminal of transistor T22.

FIGS. 3 and 4 compare the response times of the passgate of the present invention (i.e., implemented in NMOS technology) with the response times of prior art circuits (i.e., implemented in CMOS technology) for the 1.fwdarw.0 and the 0.fwdarw.1 logic signal transitions, respectively.

2. Operation of the Preferred Embodiment(s)

The redundancy fuse passgate circuit of FIG. 1 has been used in previous implementation of DRAM units. This circuit uses CMOS passgates to determine whether the Ax or the Ax.sub.-- signal will be applied to the output terminal. When the fuse is intact, the Ax signal will be applied to the output terminal by means of passgate P12. When the fuse is blown, the Ax.sub.-- signal will be transferred to the output terminal by means of passgate P11. The present invention reduces the capacitance loading placed on the Ax and the Ax.sub.-- signal. The reduction in capacitance is provided by NMOS passgates T21 and T22 while reducing the capacitance seen by the Ax and Ax.sub.-- input signals. The advantage of this circuit is a faster signal transfer of the input signals to the output terminal. As can be seen from FIG. 3 and FIG. 4, the NMOS units of the present invention are approximately 50% faster than the circuits of the related art implemented in CMOS technology. A disadvantage of the NMOS passgate circuit of the present invention is the greater layout area on the chip in comparison to the CMOS passgate circuit of FIG. 1. A further disadvantage of the present invention is the requirement for an on-chip pumped power supply, VPP. The pumped voltage supply level VPP, which is greater than the supply voltage level, provides a higher gate voltage to transistors T21 and T22. The higher gate voltage compensates for the effects of voltage drops across transistors T21 and T22 and permits the full Ax and Ax.sub.-- signal levels to be transmitted across these transistors.

While the invention has been described with particular reference to the preferred embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents substituted for elements of the preferred embodiment without departing from the invention. In addition, many modifications may be made to adapt a particular situation and material to a teaching of the present invention without departing from the essential teachings of the present invention.

As is evident from the foregoing discussion, certain aspects of the invention are not limited to the particular details of the examples illustrated, and it is therefore contemplated that other modifications and applications will occur to those skilled in the art. It is intended that the claims shall cover all modifications and applications as do not depart from the spirit and scope of the invention.