Solid State Image Sensing Device Having Facilitated Output Signal Correction

The present invention relates to a solid state image sensing device, and more specifically to a solid state image sensing device of multiline CCD (charge coupled device) register structure.

Recently, with the advance of higher resolution and higher speed of image reading devices, a multiline CCD image sensor has been known as an image sensor suitable for the image reading devices. An example of this image sensor is composed of a photoelectric transfer elements arranged in a straight line (each element of which corresponds to one pixel), a shift register, two-stage charge transfer sections (registers) composed of a plurality of CCDs, and an output section (buffer).

The signal charges generated by the photoelectric transfer elements are transferred to the charge transfer section via a shift gate at a predetermined timing and further transferred to the output section at another predetermined timing for conversion into voltage signals.

In this multiline CCD register structure, however, in case there exists defects in the charge transfer paths between the initial stage register and the succeeding stage register, charges tend to remain when being transferred between these registers. These remaining charges cause a factor of image defects. In addition, there exists such a tendency that a constant magnitude of charge remains only when the signal charge exceeds a predetermined level.

FIG. 1 shows the relationship between the signal charge generated by the photoelectric transfer section and output charge outputted after transferred between the two registers, in which 1 denotes the normal charge; 2 denotes the abnormal charge excluding the remaining charge, and 3 denotes the abnormal charge including the remaining charge. As shown in FIG. 1, when the magnitude of the signal charge is small, the relationship between both becomes non-linear characteristics, so that it has become difficult to correct the signal charges through signal processing.

With these problems in mind, therefore, it is the object of the present invention to provide a solid state image sensing device of multiline CCD structure, which can correct the signal output easily even if remaining charges exist during charge transfer between registers or can eliminate the remaining charges apparently.

To achieve the above-mentioned object, the present invention provides a solid state image sensing device, comprising: photoelectric transferring means composed of a plurality of photoelectric transfer elements arranged in a straight line, for transducing incident light into signal charges; at least first and second charge transfer paths arranged in parallel to the photoelectric transfer elements and each having a plurality of charge coupled devices, for transferring the signal charges; charge transferring means for transferring the signal charges from said photoelectric transferring means to said first charge transfer path at a first timing and for transferring the signal charges transferred to said first charge transfer path to said second charge transfer path at a second timing; and charge supplying means for applying a bias charge to the signal charges to be transferred from said first charge transfer path to said second charge transfer path.

Here, the charge supplying means comprises a charge input drain region for transducing incident light into the bias charge and a charge input electrode for applying the bias charge to the signal charges to be transferred, both the charge input drain region and electrode being formed on a semiconductor substrate. Further, the image sensing device further comprises discharging means for discharging the bias charge from said first and second charge transfer paths, respectively.

Further, the present invention provides a method of transferring charges in a solid state image sensing device having at least first and second charge transfer paths for transferring signal charges and charge transferring means for transferring the signal charges between the first and second charge transfer paths, which comprises the steps of: supplying a bias charge to the first charge transfer path; transferring the bias charge from the first charge transfer path to the second charge transfer path; supplying the signal charges to the first charge transfer path; transferring the signal charges from the first charge transfer path to the second charge transfer path; and outputting the signal charges and the bias charge both transferred to the second charge transfer path.

Further, it is preferable that the method of transferring charges further comprises the step of discharging the bias charge from the second charge transfer path. Further, it is preferable that before the signal charges are transferred to the second charge transfer path, the bias charge is outputted from the second charge transfer path; and the outputted bias charge is subtracted from a charge composed of the signal charge and the bias charge both outputted from the second charge transfer path, to obtain a signal output charge.

FIG. 1 is a characteristic diagram showing the relationship between the signal charge and the output charge output after transfer between the registers in the prior art image sensing device;

FIG. 2 is a plan view showing a linear image sensor of multiline CCD structure;

FIG. 3 is a partial plan view showing a first embodiment of the solid state image sensing device according to the present invention;

FIG. 4 is a cross-sectional view taken along a line C--C' in FIG. 3;

FIG. 5 is a cross-sectional view taken along a line A--A' in FIG. 3;

FIG. 6 is a cross-sectional view taken along a line B--B' in FIG. 3;

FIGS. 7 to 11 are partial plan views for assistance in explaining the operation of a first embodiment of the solid state image sensing device according to the present invention;

FIG. 12 is a charge transfer timing chart of the first embodiment of the solid state image sensing device;

FIG. 13 is a characteristic diagram showing the relationship between the signal charge and the output charge output after transfer between the registers in the image sensing device according to the present invention;

FIGS. 14 to 17 are partial plan views for assistance in explaining the operation of a second embodiment of the solid state image sensing device according to the present invention;

FIG. 18 is a charge transfer timing chart of the second embodiment of the solid state image sensing device;

FIGS. 19 to 24 are partial plan views for assistance in explaining the operation of a third embodiment of the solid state image sensing device according to the present invention;

FIG. 25 is a charge transfer timing chart of the third embodiment of the solid state image sensing device;

FIGS. 26 to 31 are partial plan views for assistance in explaining the apparition of a fourth embodiment of the solid state image sensing device according to the present invention;

FIG. 32 is a charge transfer timing chart of the fourth embodiment of the solid state image sensing device; and

FIG. 33 is a cross-sectional view taken along a line A--A' in FIG. 26.

FIG. 2 shows an image sensor of multiline CCD register structure according to the present invention, which is formed on a semiconductor substrate. The image sensor is composed of a photoelectric transfer element line 10 (each element of which corresponds to one pixel), a shift register 20, two stage charge transfer sections (registers) 30 and 60 each composed of a plurality of CCDs, a transfer gate 50, and two output sections (buffers) 40 and 70.

FIG. 3 is an enlarged plane view showing a part of the image sensor shown in FIG. 2. In FIG. 3, the shift gate 20 and the transfer gate 50 are connected to dedicated drive pulse lines SH (SH1 and SH2) and TG, respectively. Further, drive pulse lines P1 and P2 are connected alternately to the arranged transfer electrodes of the CCD registers 30 and 60, respectively.

Further, as shown in FIG. 3, the drive pulse lines SH1 and SH2 are connected alternately to the arranged electrodes of the shift gate 20. That is, the respective electrodes of the shift gate 20 are arranged and connected alternately to either of the drive pulse lines SH1 or SH2. Further, since the shift gates 20 shown in figures other than FIG. 3 are of the same structure as that shown in FIG. 3, the reference symbols SH1 and SH2 are omitted herein in the other figures.

The drive pulse line SH1 is connected to the electrode as arranged alternately along the A--A' line portion shown in FIG. 3, and the drive pulse line SH2 is connected to the electrode as arranged alternately along the B--B' line portion shown in FIG. 3. As shown in FIGS. 4 to 6 (which correspond to the cross-sectional views taken along the lines C--C', A--A' and B--B' all shown in FIG. 3), each photoelectric transfer element 10 is formed in an impurity diffusion region formed in a surface of a semiconductor substrate 100. Further, the shift gate 20, the transfer gate 50, and the CCD registers 30 and 60 are composed of electrodes (e.g., formed of polysilicon) formed on the semiconductor substrate 100, respectively. Further, in this embodiment, an input section is composed of a charge input electrode 110 and a charge input drain region 120 both formed in the CCD register 30 to inject fat zero charge bias charge) to the CCD register S0. The charge input electrode 110 is an electrode formed of polysilicon on the semiconductor substrate 100. The charge input electrode 110 is connected to a drive pulse line IG, and the charge input drain region 120 is connected to a drive pulse line 18. Further, the input section 120 is formed by an impurity diffusion region formed in the surface of the semiconductor substrate 100, which constitutes a kind of photoelectric transfer section for obtaining the fat zero charge on the basis of light incident thereupon.

With reference to FIGS. 3, 7 to 9 and 12 (timing chart), the operation of the image sensor according to the present invention will be described hereinbelow. First, at time t1, the drive pulse line IG connected to the input section 110 is turned on to inject fat zero charges 30a from the input section 110 to the CCD register 30 (see FIG. 3). Further, at time t2, the drive pulse line TG connected to the transfer gate 50 is turned on to transfer the fat zero charges 30a from the CCD register 30 to the CCD register 60 (see FIG. 7). Further, at this time, in case there exists a defect in a charge transfer-path (not shown) between the CCD 31 of the CCD register 30 and the CCD 61 of the CCD register 60 (as shown at the middle portions of the two CCD registers in FIG. 7), the fat zero charge 30a is transferred to the CCD register 60 by leaving a remaining charge 30b at the CCD register 30 (as a charge 60a excluding a remaining fat zero charge 30b). After that, at time t3, the drive pulse line SH1 connected to the shift register 20 is turned on to transfer signal charges 30c from the photoelectric transfer elements 10 to the CCD register 30 alternately (see FIG. 8), Further, when there exists a remaining charge 30b, at time t4, the drive pulse line TG connected to the transfer gate 50 is turned on to transfer the signal charges 30c together with the remaining fat zero charge 30b from the CCD register 30 to the CCD register 60 (see FIG. 9), because the remaining fat zero charge 30b still remains at the first CCD register 30. After that, at time t5, the drive pulse line SH2 connected to the shift register 20 is turned on to transfer signal charges 30d from the remaining photoelectric transfer elements 10 to the CCD register 30 alternately (see FIG. 10).

Further, at time t6, the signal charges 30d are shifted within the CCD register 30 to join the remaining fat zero charge 30b on the basis of two-phase pulses P1 and P2 (see FIG. 11). The joined charges are outputted through an output buffer (not shown). In the same way, the signal charges 30c are shifted within the CCD register 60 to join the signal charges 30c with the fat zero charge 30a or 60a on the basis of the two-phase pulses P1 and P2 (see FIG. 11). The joined charges are outputted through an output buffer (not shown).

As described above, since the signal charges transferred from the photoelectric transfer elements 10 alternately are joined with the fat zero charges and the remaining charges, it is possible to obtain the signal charge (30d+30b) obtained by adding the normal signal charge 30d and the remaining fat zero charge 30b, the signal charge (30c+30a) obtained by adding the signal charge 30c and the normal fat zero charge 30a, and the signal charge (30d+60a) obtained by adding the signal charge 30d and the small fat zero charge 60a, in addition to the normal signal charges 30c and 30d.

FIG. 13 shows the relationship between the magnitude of the signal charge and the magnitude of the output charge obtained after transfer between the two CCD registers 30 and 60 at this time; that is, FIG. 13 shows the characteristics showing the dependency of the magnitude of the output charge of the image sensing device upon the magnitude of the signal charge obtained by the photoelectric transfer elements in this embodiment. In FIG. 13, the ordinate indicate the output charge magnitude and the abscissa indicates the signal charge magnitude. In FIG. 13, since the non-linear characteristics are maintained when the signal charge magnitude is small, although the offset rate changes according to the presence or absence of the remaining charges, it is possible to correct the signals easily along the linear characteristics. In FIG. 13, the line 200 designates the output charge having no remaining charge of the register 60; the line 210 designates the output charge having the remaining charge of the register 60; the line 220 designates the output charge having no remaining charge of the register 30; and the line 230 designates the output charge having the remaining charge of the register 30, respectively.

A second embodiment of the present invention will be described herein below with reference to FIGS. 14 to 18. Further, in the respective embodiments described later, the assumption is made that there exists a defect in the charge transfer path between the CCD 31 (see FIG. 7) of the CCD register 30 and the CCD 61 (see FIG. 7) of the CCD register 60, in the same way as with the case of the first embodiment.

The feature of this second embodiment is that the signal charge is joined with the fat zero charge, and after that the joined charges are transferred from the CCD register 30 to the CCD register 60. First, in the same way as explained with reference to FIG. 3, at time t1, the drive pulse line IG connected to the input section 110 and the drive pulse line SH1 connected to the shift register 20 are both turned on to inject the fat zero charges 30a from the input section 110 to the CCD register 30. Further, at time t2, the signal charges 30c of the photoelectric transfer elements 10 are transferred to the CCD register 30 alternately (see FIG. 14). Then, at time t3, the drive pulse line TG connected to the transfer gate 50 is turned on to transfer the signal charges 30c and the fat zero charge 30a from the CCD register 30 to the CCD register 60 (see FIG. 15). At this time, the fat zero charge shown at the middle in FIG. 15 is transferred by leaving the remaining fat zero charge 30b in the CCD register 30. Next, at time t4, the drive pulse line SH2 connected to the shift register 20 is turned on to transfer the signal charges 30d from the photoelectric transfer elements 10 to the CCD register 30 alternately (see FIG. 16).

Further, at time t5, the signal charges 30d are shifted within the CCD register 30 on the basis of the two-phase pulses P1 and P2 to join the signal charges 30d with the remaining fat zero charge 30b (see FIG. 17), and then outputted through the output buffer. In the same way, the signal charges 30c are shifted within the CCD register 60 on the basis of the two-phase pulses P1 and P2 to join the signal charges 30c with the fat zero charge 30a (see FIG. 17), and then outputted through the output buffer. In the same way as with the case of the first embodiment, since the signal charges transferred from the photoelectric transfer elements 10 alternately are joined with the fat zero charges and the remaining charges, it is possible to obtain the signal charge (30d+30b) obtained by adding the normal signal charge 30d and the remaining fat zero charge 30b, the signal charge (30c+30a) obtained by adding the signal charge 30c and the normal fat zero charge 30a, and the signal charge (30c+60a) obtained by adding the signal charge 30c and the small fat zero charge 60a, in addition to the normal signal charges 30c and 30d.

In this second embodiment, the dependency of the magnitude of the output charge upon the magnitude of the signal charge is the same as shown in FIG. 13. Since the non-linear characteristics are maintained when the signal charge magnitude is small, although the offset rate changes according to the presence or absence of the remaining charge, it is possible to correct the signals easily along the linear characteristics.

In the above-mentioned embodiments, to join the signal charges with the fat zero charges, it is possible to generate the fat zero charges by irradiating bias light upon the photoelectric transfer elements. Further, at the register 60 at which the signal charges are joined with the fat zero charges, since the magnitude of the transfer charge is larger than that of the register 30, it is necessary to use the COD register 60 having a higher maximum charge transfer rate, as compared with that of the CCD register 30.

Further, in the case of the first embodiment, it is possible to obtain the real signal charge magnitude by transferring the charges in the CCD registers to the output section in FIG. 7 and further by subtracting the outputted charge from the output charges transferred from the CCD registers in the operation shown in FIG. 11.

Further, in the second embodiment, it is possible to obtain the real signal charge magnitude by outputting the charges in the CCD registers to the outside when the signal charges are being transferred from the COD register 30 the CCD register 60 as shown in FIG. 15 and then by subtracting the outputted signal charges from the outputted charges transferred in the operation shown in FIG. 17.

Further, in the above-mentioned embodiments, the signal charges are transferred once between the CCD registers. However, when the signal charges are transferred several times, it is necessary to retrain the remaining charges the same electrode while the signal charges are transferred between the CCD registers. This case will be described hereinbelow.

A third embodiment corresponding to this case will be described hereinbelow with reference to FIGS. 19 to 25. The feature of this third embodiment is to provide charge discharging sections 130 and 140 for discharging the charges of the CCD register 60. The charge discharging section 130 is composed of polysilicon electrodes formed on the semiconductor substrate 100 and connected to a drive pulse line OFG. Further, the charge discharging section 140 is composed of impurity diffusion regions formed in the surface of the semiconductor substrate 100 and connected to a drive pulse line OFD.

The operation of this third embodiment will be explained hereinbelow. First, at time t1, the drive pulse line IG connected to the input section 110 is turned on to inject the fat zero charges 30a from the input section 110 to the CCD register 30 (see FIG. 19). Then, at time t2, the drive pulse line TG connected to the transfer gate 50 is turned on to transfer the fat zero charges 30a from the CCD register 30 to the CCD register 60 (see FIG. 20). At this time, the fat zero charge at the middle of the CCD register 30 is transferred to the CCD register 60 by leaving the remaining fat zero charge 30b thereat. After that, at time t3, the drive pulse line OFG connected to the charge discharging section 130 is turned on to transfer the fat zero charges 30a of the CCD register 60 to the charge discharging section 140 so that the fat zero charges 30a ere removed from the register transfer path (see FIG. 21).

Further, at time t4, the drive pulse line SH1 connected to the shift register 2 is turned on to transfer the signal charges of the photoelectric transfer elements 10 to the CCD register 30 alternately (see FIG. 22). Further, at time t5, when there exists a remaining charge, the signal charges 30c are transferred from the CCD register 30 to the CCD register 60 together with the remaining fat zero charge (see FIG. 23). The remaining fat zero charge 30b still remains at the CCD register 30. Next, at time t6, the drive pulse line SH2 connected to the shift register 20 is turned on to transfer the signal charges from the remaining photoelectric transfer elements 10 to the CCD register 30 alternately. After that, at time t6, the signal charges 30d are shifted within the CCD register 30 on the basis of the two-phase pulses P1 and P2 to join the signal charge 30d with the remaining fat zero charge 30b (see FIG. 24), and the joined charges are outputted through an output buffer. In the same way, the signal charges 30c are shifted within the CCD register 60 on the basis of the two-phase pulses P1 and P2 and outputted through an output buffer.

After the fat zero charge has been transferred from the CCD register 30 to the CCD register 60 as shown in FIG. 20, since the charges of the CCD register 60 are discharged, the charge added to the signal charge is only the remaining fat zero charge, so that it is possible to reduce the magnitude of the charge to be transferred between the CCD registers 30 and 60. Further, since the fat zero charge is not added to the signal charge, the signal charge is not subjected to the influence of noise included in the fat zero charge. Further, instead of the charge discharging section, it is also possible to provide another set of the transfer gate and the CCD register in the vicinity of the CCD register 60 to transfer the fat zero charge to the additional CCD register.

A fourth embodiment will be described hereinbelow with reference to FIGS. 26 to 33. The feature of this embodiment is that the charges of the register 60 are discharged perfectly immediately before the signal charges are transferred between the two CCD registers and in addition the remaining fat zero charges in the CCD register 30 are discharged before the succeeding signal charges are transferred. Further, FIG. 33 is a cross-sectional view showing the semiconductor substrate 100 taken along the line A--A' shown in FIG. 26. In this fourth embodiment, the charge discharging sections 150 and 160 (see FIG. 33) are additionally formed to discharge the charges in the CCD registers 30 and 60, respectively. These charge discharging sections 150 and 160 are formed by N-type impurity diffusion regions buried just under the register electrodes 30 and 60, respectively, and connected to drive pulse lines D1 and D2, respectively.

The operation of this fourth embodiment will be described. First, at time t1, the drive pulse line IG connected to the input section 110 is turned on to inject the fat zero charges 30a from the input section 110 to the CCD register 30 (see FIG. 26). Then, at time t2, the drive pulse line TG connected to the transfer gate 50 is turned on to transfer the fat zero charges 30a from the CCD register 30 to the CCD register 60 (see FIG. 27). At this time, the fat zero charge at the middle of the CCD register 30 is transferred to the CCD register 60 by leaving the remaining fat zero charge 30b at the CCD register 30. After that, at time t3, the drive pulse line SH1 connected to the shift register 20 is turned on to transfer the signal charges of the photoelectric transfer elements 10 to the CCD register 30 alternately (see FIG. 28). Further, at time t4, the drive pulse line D2 connected to the charge discharging section 160 is turned on to discharge the fat zero charges 30a of the CCD register 60. Further, at time t5, when there exists the remaining charge, the signal charges 30c are transferred from the CCD register 30 to the CCD register 60 together with the remaining charge (see FIG. 29). In this case, the remaining fat zero charge 30b remains at the CCD register 30.

Further, at time t6, the drive pulse line D1 connected to the charge discharging section 150 is turned on to discharge the remaining fat zero charge 30b at the CCD register 30. Further, at time t7, the drive pulse line SH2 connected to the shift register 20 is turned on to transfer the signal charges 30d of the remaining photoelectric transfer elements 10 to the CCD register 30 alternately (see FIG. 30). After that, at time t8, the signal charge 30d are shifted within the CCD register 30 on the basis of the two-phase pulses P1 and P2 (see FIG. 31), and then outputted through an output buffer. In the same way, the signal charges 30c are shifted within the CCD register 60 on the basis of the two-phase pulses P1 and P2, and then outputted through an output buffer.

In this embodiment, since the charges of the register 60 are discharged completely immediately before the signal charges are transferred between the CCD registers and further the remaining charges in the register 30 are discharged before the succeeding signal charges are transferred, it is possible to obtain the perfect output signal charges having no remaining charges.

As described above, in the present invention, since the fat zero charges are injected to the CCD register and since the remaining signal charges can be kept constant, after the transfer between the two CCD registers, irrespective of the magnitude of the signal charges, it is possible to easily correct the signals even if remaining signal charges are generated. Further, when the remaining charges are discharged, it is possible to eliminate the remaining signal charges.