Redundancy Circuit

The present invention relates to a redundancy circuit of a highly integrated semiconductor memory device, and more particularly to a redundancy circuit that can improve integration of the semiconductor memory device.

Highly integrated semiconductor devices such as DRAM(Direct Random Access Memory), SRAM(Static Random Access Memory) and Pseudo SRAM have a plurality of divided memory blocks due to the power consumption and the increase in capacitance impedance of word line. The memory block has a plurality of memory cell arrays and at least one redundancy cell array for replacing defective memory cell array among the plurality of memory cell arrays. The highly integrated semiconductor memory device has redundancy circuits, as many as the redundancy memory cell arrays, respectively connected to said at least one redundancy memory cell array, to drive the redundancy memory cell array instead of the defective memory cell array. However, the number of defective memory cell arrays generated in memory block is much smaller than the number of redundancy memory cell arrays, and there exists many unused redundancy memory cell arrays and redundancy circuits. The unused plural redundancy circuits unnecessarily consume the predetermined region of the highly integrated semiconductor memory device. The unnecessarily consumed region limits the integration of the highly integrated semiconductor memory device.

Accordingly, it is an object of the present invention to provide a redundancy circuit that can improve the integration of the highly integrated semiconductor memory device.

To achieve the object, the redundancy circuit of the present invention comprises at least two memory blocks, each memory block having a plurality of normal memory cell arrays and a redundancy memory cell array for replacing a defective memory cell array, at least two redundancy cell array driving means respectively connected to at least two redundancy memory cell arrays for driving at least two redundancy memory cell arrays, a defective-cell-array detection fuse box for detecting address corresponding to the defective memory cell array, a block selection fuse box for selecting the plurality of memory blocks, and driving control means for driving one among at least two redundancy cell array driving means.

The above objects and other advantage of the present invention will become more apparent by describing the preferred embodiment of the present invention with reference to the attached drawings, in which:

FIG. 1 is a block diagram of a row redundancy circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a highly integrated semiconductor memory device having two redundancy memory cell arrays per memory block where the row redundancy circuit according to the embodiment of the present invention is applied; and

FIG. 3 is a schematic diagram of a highly integrated semiconductor memory device having four redundancy memory cell arrays per memory block where the row redundancy circuit according to the embodiment of the present invention is applied.

Turning now to FIG. 1, a row redundancy circuit according to an embodiment of the present invention which has first and second memory blocks 10 and 12, and a defective-cell-array detection fuse box 16 for receiving 8-bit address signals A0 to A7 from an address bus 11 is illustrated. Each of first and second memory blocks 10 and 12 has 256 memory cell arrays MA0 to MA255 and a redundancy memory cell array RMA. The defective-cell-array detection fuse box 16 generates a redundancy mode selection signal having high logic, when the 8-bit address signals A0 to A7 have the same logic value as the address of defective cell arrays programmed by a manufacturer. While a pre-charge signal of high logic is supplied from a first control line 13, the defective-cell-array detection fuse box 16 generates a redundancy mode selection signal having low or high logic according to the logic value of the 8-bit address signals A0 to A7. Also, the defective-cell-array detection fuse box 16 is driven by a driving signal from a second control line 15. The address programmed in the defective-cell-array detection fuse box 16 has a logic value of row address of the defective memory cell array generated in the first memory block 10 or the second memory block 12. The 8-bit address signals A0 to A7 include true address signal and complementary address signal, and are supplied to the defective-cell-array detection fuse box 16 via the address bus 11 from an address buffer (not shown).

The row redundancy circuit additionally has a redundancy cell array controller 50 for receiving the redundancy mode selection signal, and a block selection fuse box 18 for selecting the driving of the redundancy memory cell arrays RMA within the first and second memory cell blocks 10 and 12. The block selection fuse box 18 generates first and second block selection signals having opposite logics with each other, according to the state previously set by the manufacturer, and supplies the first and second block selection signals to the first and second controlling switches SW1 and SW2. The first block selection signal has a high logic, to drive the redundancy memory cell array RMA within the first memory block 10, and a low logic, to drive the redundancy memory cell array RMA within the second memory block 12. To generate the first and second block selection signals, two fuses programmable by the manufacturer are provided. The first controlling switch SW1 supplies a block enable signal from the third control line 17 to the redundancy cell array controller 50, when the first block selection signal from the block selection fuse box 18 has high logic. Meanwhile, when the second block selection signal has high logic, the second controlling switch SW2 supplies the second block enable signal from the fourth control line 19 to the redundancy cell array controller 50. Accordingly, the first and second controlling switches SW1 and SW2, maintaining opposite switching states, supply to the redundancy cell array controller 50 a first block enable signal from the third control line 17 or a second block enable signal from the fourth control line 19 according to logic values of the first and second block selection signals from the block selection fuse box 18. When all of the redundancy mode selection signal from the defective-cell-array detection fuse box 16, and the first block enable signal from the first controlling switch SW1 or the second block enable signal from the second controlling switch SW2 have high logic, the redundancy cell array controller 50 generates a redundancy strobe signal of high logic. The redundancy cell array controller 50 receives a driving signal from the second control line 15 and is operated when the driving signal has high logic. The high logic redundancy strobe signal makes a driving voltage generator 52 generate a driving voltage signal.

Also, the row redundancy circuit has a first NAND gate 20 for receiving the first block selection signal from the block selection fuse box 18 and the redundancy mode selection signal the defective-cell-array detection fuse box 16, and a second NAND gate 34 for receiving the second block selection signal and the redundancy mode selection signal from the first block selection fuse box 18 and the defective-cell-array detection fuse box 16. The first NAND gate 20 inverts the redundancy mode selection signal when the first block selection signal has high logic. The first NAND gate 20 supplies the inverted redundancy mode selection signal to the first redundancy cell array driver 54 and the first normal cell array driver 48, which are then complementarily driven. While the inverted redundancy mode selection signal from the first NAND gate 20 has low logic, the first redundancy cell array driver 54 supplies the driving voltage signal from the driving voltage generator 52 to the redundancy memory cell array RMA of the first memory block 10, to drive the redundancy memory cell array RMA within the first memory block 10 instead of the defective memory cell array. Meanwhile, when the first block selection signal has low logic, the first NAND gate 20 supplies a logic signal of high logic to the first normal cell array driver 48 and the first redundancy cell array driver 54, and accordingly, the first normal cell array driver 48 is always driven. At this time, the first redundancy cell array driver 54 and the first redundancy memory cell array RMA within the first memory block 10 are not used.

Similarly, when the second block selection signal has high logic, the second NAND gate 34 also supplies the inverted redundancy mode selection signal to the second normal cell array driver 58 and the second redundancy cell array driver 56, so that the second normal cell array driver 58 and the second redundancy cell array driver 56 are complementarily driven. While the inverted redundancy mode selection signal from the second NAND gate 34 has low logic, the second redundancy cell array driver 56 supplies the driving voltage signal from the driving voltage generator 52 to the redundancy memory cell array RMA of the second memory block 12, so that the redundancy memory cell array RMA within the second memory block 12 is driven instead of the defective memory cell array. Contrarily, when the second block selection signal has low logic, the second NAND gate 34 supplies a logic signal of high logic to the second normal cell array driver 58 and the second redundancy cell array driver 56, so that the second normal cell array driver 58 are always driven, but the second redundancy cell array driver 56 and the redundancy memory cell array RMA within the second memory block 12 are not driven. Accordingly, the first and second NAND gates 20 and 34 function to selectively drive the first redundancy cell array driver 54 and the second redundancy cell array driver 56 according to logic values of the first and second block selection signals.

The first normal cell array driver 48 driven by logic signal of high logic or the inverted redundancy mode selection signal from the first NAND gate 20 has a normal cell array controller 22 for receiving an output signal of the first NAND gate 20, and a driving signal and a first block enable signal from the second and third control lines 15 and 17. When all of the output signal of the first NAND gate 20, driving signal, and first block enable signal have high logic, the normal cell array controller 22 generates a normal strobe signal of high logic, and supplies the normal strobe signal to four driving voltage generators 24 to 30. The four driving voltage generators 24 to 30 are selectively driven by the logic values of first to fourth address decoding signals from the fifth to eighth control lines 21 to 27, and generate a driving voltage signal for driving a normal memory cell array. When the normal strobe signal and the first address decoding signal have high logic, the driving voltage generator 24 generates a driving voltage signal for driving (4n+0)-th memory cell arrays MA0, MA4, . . . , MA252 within the first memory block. When the normal strobe signal and the second address decoding signal have high logic, the driving voltage generator 26 generates a driving voltage signal for driving (4n+1)-th memory cell arrays MA1, MA5, . . . , MA253 within the first memory block 10. When the normal strobe signal and the third address decoding signal have high logic, the driving voltage generator 28 generates a driving voltage signal for driving the (4n+2)-th memory cell arrays MA2, MA6, . . . , MA254 within the first memory block 10. When the normal strobe signal and the fourth address decoding signal have high logic, the driving voltage generator 30 generates a driving voltage signal for driving the (4n+3)-th memory cell arrays MA3, MA7, . . . , MA255 within the first memory block 10. The first to fourth address decoding signals have specific logic (for example, high or low logic), when least and next-least significant complementary address signals /A0 and /A1, least significant true address signal A0 and next-least significant complementary address signal /A1, least significant complementary address signal /A0 and next-least significant true address signal A1, and least and next-least significant true address signals A0 and A1 have high logic, respectively. The first normal cell array driver 32 selects 4n+0 to 4n+3 memory cell arrays within the first memory block 10 by a 12-bit fifth address decoding signal from a control bus 29. The first normal cell array driver 32 supplies the driving voltage signal to any one memory cell array among the selected 4n+0 to 4n+3 memory cell arrays, to drive memory cell array in the address corresponding to the logic value of the 8-bit address signals A0 to A7. Also, the first normal cell array driver 32 is operated by a pre-charge signal from the first control line 13.

The second normal cell array driver 58 receiving the output of the second NAND gate 34 and the second block enable signal from the fourth control line 19 drives a normal memory cell array within the second memory block 12 according to the logic values of the fifth to ninth address decoding signals. To do this, the second normal cell array driver 58 has a second normal cell array controller 36, a second normal cell array driver 46, and four driving voltage generators 38 to 44, which respectively have the same constitutions as those of the first normal cell array driver 48. The operation of the second normal cell array driver 58 having the same circuit components as those of the first normal cell array driver 48 is omitted. The sense amplifier 14 amplifies data stored in the first and second memory blocks 10 and 12, or amplifies data read out from the first and second memory blocks 10 and 12.

FIG. 2 illustrates a semiconductor memory device where the row redundancy circuit, according to the embodiment of the present invention, comprising first to fourth memory blocks 60 to 66, each having two redundancy memory cell arrays, four normal cell array drivers 68 to 74, and two sense amplifiers 76 and 78, is applied. The first redundancy memory cell array RMA0 within the first memory block 60 is used instead of the first defective memory cell array FDMA0 by the first block selection fuse box 96, the first cell array controller 104, and the redundancy cell array driver 82. The first redundancy memory cell array RMA2 within the first memory block 62 is used instead of the second defective memory cell array FDMA1 by the second block selection fuse box 98, the second cell array controller 106, and the redundancy cell array driver 84. Also, the first redundancy cell array RMA4 within the third memory block 64 driven by the third block selection fuse box 100, the third cell array controller 108, and the redundancy cell array driver 88, and the second redundancy memory cell array RMA5 within the third memory block 64 driven by the fourth block selection fuse box 102, the fourth cell array controller 110 and the redundancy cell array driver 90 are used instead of two memory cell arrays DFMA2 and DFMA3, respectively. Meanwhile, the second redundancy memory cell array RMA1 within the first memory block 60, the second redundancy memory cell array RMA3 within the second memory block 62, the first and second redundancy memory cell arrays RMA6 and RMA7 within the fourth memory block 66, and four redundancy cell array drivers 82, 84, 92 and 94 are not used. The first to fourth redundancy cell array controllers 104 to 110 include the first and second NAND gates 20 and 34, the first and second controlling switches SW1 and SW2, the defective-cell-array detection fuse box 16, the redundancy cell array controller 50, and the driving voltage generator 52, shown in FIG. 1.

FIG. 3 is a block diagram of a semiconductor memory device where the row redundancy circuit, according to the embodiment of the present invention, comprising n memory blocks BL1 to BLn, each of which has four redundancy memory cell arrays RMA1 to RMA4n, n sense amplifiers SA1 to SAn, and n normal cell array drivers NCD1 to NCDn is applied. The semiconductor memory device shown in FIG. 3 has 2n+2 block selection fuse boxes BSFD1 to BSFD2n+2, 2n+2 redundancy cell array drivers RCC1 to RCC2n+2, and 4n redundancy cell array drivers RCD1 to RCD4n. In the semiconductor memory device, the redundancy memory cell arrays RMA1 to RMA4, RMA7, RMA9, RMA11, RMA4n-3, RMA4n-1 and RMA4n, indicated with the solid lines, are used instead of the defective memory cell arrays DFMA1 to DFMA10. However, the redundancy memory cell arrays RMA5, RMA6, RMA8 to RMA10, RMA12 and RMA4n-2, indicated with the dotted lines, are not used, and the redundancy cell array drivers RCD5, RCD6, RCD8 to RCD10, RCD12 and RCD4n-2, indicated with the dotted lines, are not driven.

As described above, the redundancy circuit of the present invention selectively drives two redundancy memory cell arrays to improve the efficiency of the redundancy circuit of the semiconductor memory device. Accordingly, the redundancy circuit of the present invention minimizes the unneeded space consumption of the semiconductor memory device and improves the integration of the semiconductor memory device.