Method and Apparatus for Reading/Writing Data From/Into Semiconductor Memory Device

1. Field of the Invention

The present invention relates in general to a method and an apparatus for reading/writing data from/into a semiconductor memory device, and more particularly to a method and an apparatus for reading/writing data from/into a semiconductor memory device, in which, instead of true and complementary data input/output lines connected respectively to true and complementary bit lines, true and complementary column decoding lines are used to perform data read/write operations, thereby reducing the area of a semiconductor memory chip.

2. Description of the Prior Art

Referring to FIG. 1, there is shown a circuit diagram of a conventional data read/write apparatus for a semiconductor memory device such as a dynamic random access memory (referred to hereinafter as DRAM) device. As shown in this drawing, the DRAM device comprises a plurality of memory cell array blocks 10, each of which includes a plurality of memory cells 11 for storing data therein. Although not shown, each of the memory cells 11 is provided with one NMOS transistor and one capacitor.

The conventional data read/write apparatus comprises a plurality of bit line sense amplifier array blocks 12, each of which includes a plurality of bit line sense amplifiers 13 for sense-amplifying the data which are transferred from the memory cells 11 to true and complementary bit lines BL and /BL.

The conventional data read/write apparatus further comprises transfer transistors Q1 and Q3 for transferring the data on the bit lines BL to a true data input/output line IO in response to an output signal Yi from a column decoder (not shown), transfer transistors Q2 and Q4 for transferring the data on the bit lines BL to a complementary data input/output line/IO in response to the output signal Yi from the column decoder, a read sense amplifier 15 for sense-amplifying the data on the data input/output lines IO and /IO and transferring the sense-amplified data to a data output buffer (not shown), and a write driver 14 for transferring external write data to the data input/output lines IO and /IO.

Although not shown, a precharge circuit is provided to maintain the true and complementary bit lines BL and /BL at a precharge voltage level Vblp in a standby mode.

The operation of the conventional data read/write apparatus for the DRAM device with the above-mentioned construction will hereinafter be described.

First, when a signal/RAS which is a main signal for operating the DRAM device is made active, address signals from an address buffer (not shown) are received. At this time, a row decoding operation is performed which decodes the received address signals and selects one of word lines to the memory cell array block 10 in accordance with the decoded result. Data from the memory cells 11 connected to the selected word line are placed on the bit lines BL and /BL. At this time, the data placed on the bit lines BL and /BL have a feeble signal level. For this reason, the bin line sense amplifiers 13 are driven to sense-amplify the data on the bit lines BL and /BL to a supply voltage level Vcc and a ground voltage level vss. The transfer transistors Q1-Q4 act to transfer the data on the bit lines BL and /BL, sense-amplified by the bit line sense amplifiers 13, respectively to the data input/output lines IO and /IO in response to the output signal Yi from the column decoder. In more detail, the transfer transistors Q1-Q4 select one of columns in response to the output signal Yi from the column decoder. The data on the bit lines BL and /BL of the selected column are placed respectively on the data input/output lines IO and /IO by the turned-on transfer transistors Q1 and Q2 or Q3 and Q4. Then, the read sense amplifier 15 sense-amplifies the data on the data input/output lines IO and /IO and transfers the sense-amplified data to the data output buffer. On the other hand, external write data are placed on the data input/output lines IO and /IO by the write driver 14. The write data placed on the data input/output lines IO and /IO are written into the memory cell 11 by the bit line sense amplifier 13 of a column selected by the output signal Yi from the column decoder.

Referring to FIG. 2, there is shown a circuit diagram of another conventional data read/write apparatus for a semiconductor memory device. Some parts in this drawing are the same as those in FIG. 1. Therefore, like reference numerals designate like parts. As shown in this drawing, the true and complementary bit lines BL and /BL are connected to a plurality of true and complementary input/output lines IO0 and /IO0 and IO1 and /IO1 to embody a wide bit memory capacity.

In FIG. 2, a plurality of columns are simultaneously selected by one column address. In order to simultaneously read a plurality of data from the memory cells 11 in the selected columns, the same number of true and complementary input/output lines as the selected columns are required. For this reason, many true and complementary input/output lines to each bit line sense amplifier are required in wide bit memory devices with a large number of input/output bits. This results in an increase in the area of a semiconductor memory chip.

Therefore, the present invention has been made in view of the above problem, and it is an object of the present invention to provide a method and an apparatus for reading/writing data from/into a semiconductor memory device, in which, instead of true and complementary data input/output lines connected respectively to true and complementary bit lines, true and complementary column decoding lines are used to perform data read/write operations, thereby reducing the area of a semiconductor memory chip.

In accordance with one aspect of the present invention, there is provided a method for reading data from a semiconductor memory device, comprising the steps of selecting a memory cell array block from which data is to be read, in response to a row address signal; selecting a column of the selected memory cell array block in response to a column address signal; sense-amplifying data which are transferred from a memory cell of the selected column to a pair of bit lines of the selected column; decoding a read signal and allowing a pair of column decoding lines of the selected column to become a desired logic state in accordance with the decoded result; forming a current path between one of the column decoding lines and a ground terminal in response to the sense-amplified data on the bit lines; selecting data on the column decoding lines; and sense-amplifying the selected data and outputting the sense-amplified data externally.

In accordance with another aspect of the present invention, there is provided a method for writing data into a semiconductor memory device, comprising the steps of selecting a memory cell array block into which data is to be written, in response to a row address signal; selecting a column of the selected memory cell array block in response to a column address signal; allowing a pair of column decoding lines of the selected column to become a desired logic state in response to a write signal; transferring data on one of the column decoding lines to a bit line sense amplifier connected to a memory cell of the selected column; and restoring data on the other column decoding line to a logic state opposite to that of the data on the one column decoding line.

In accordance with a further aspect of the present invention, there is provided a method for reading/writing data from/into a semiconductor memory device, comprising the steps of reading data from the semiconductor memory device, the data reading step including the first step of selecting a memory cell array block from which data is to be read, in response to a row address signal; the second step of selecting a column of the memory cell array block selected at the first step in response to a column address signal; the third step of sense-amplifying data which are transferred from a memory cell of the column selected at the second step to a pair of bit lines of the selected column; the fourth step of decoding a read signal and allowing a pair of column decoding lines of the column selected at the second step to become a first logic state in accordance with the decoded result; the fifth step of forming a current path between one of the column decoding lines and a ground terminal in response to the sense-amplified data on the bit lines; the sixth step of selecting data on the column decoding lines; and the seventh step of sense-amplifying the selected data and outputting the sense-amplified data externally; and the step of writing data into the semiconductor memory device, the data writing step including the eighth step of selecting a memory cell array block into which data is to be written, in response to the row address signal; the ninth step of selecting a column of the memory cell array block selected at the eighth step in response to the column address signal; the tenth step of allowing a pair of column decoding lines of the column selected at the ninth step to become a second logic state in response to a write signal; the eleventh step of transferring data on one of the column decoding lines to a bit line sense amplifier connected to a memory cell of the column selected at the ninth step; and the twelfth step of restoring data on the other column decoding line to a logic state opposite to that of the data on the one column decoding line.

In accordance with yet another aspect of the present invention, there is provided an apparatus for reading/writing data from/into a semiconductor memory device, comprising bit line sense amplification means for sense-amplifying data which are transferred from memory cells to a pair of bit lines; column decoding means for outputting a first logic signal to a pair of column decoding lines in a read mode and a second logic signal to the pair of column decoding lines in a write mode in response to a column address signal, write input/output signals and a read/write signal; first transfer transistor means connected between the bit lines and the column decoding lines, the first transfer transistor means being driven in response to a block selection row address signal; second transfer transistor means connected in a cross coupled manner between the first transfer transistor means and the column decoding lines, the second transfer transistor means being driven in response to logic signals on the column decoding lines; multiplexing means for transferring data on the column decoding lines of a selected column; and read sense amplification means for sense-amplifying the data transferred by the multiplexing means and transferring the sense-amplified data to a data output buffer,

The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a circuit diagram of a conventional data read/write apparatus for a semiconductor memory device;

FIG. 2 is a circuit diagram of another conventional data read/write apparatus for a semiconductor memory device;

FIG. 3 is a circuit diagram of a data read/write apparatus for a semiconductor memory device in accordance with a first embodiment of the present invention;

FIG. 4 is a circuit diagram of a data read/write apparatus for a semiconductor memory device in accordance with a second embodiment of the present invention;

FIG. 5 is a circuit diagram of a data read/write apparatus for a semiconductor memory device in accordance with a third embodiment of the present invention; and

FIG. 6 is a timing diagram illustrating the operation of the data read/write apparatus in FIG. 3.

Referring to FIG. 3, there is shown a circuit diagram of a data read/write apparatus for a semiconductor memory device in accordance with a first embodiment of the present invention. Some parts in this drawing are the same as those in FIGS. 1 and 2. Therefore, like reference numerals designate like parts.

As shown in FIG. 3, the data read/write apparatus comprises a plurality of column decoders 16 being driven in response to a column address signal Col ADD, write input/output signals WIO and /WIO and a read/write signal R/W. As being driven, each of the column decoders 16 outputs a first logic signal to true and complementary column decoding lines Yi and /Yi in a read mode and a second logic signal to the column decoding lines Yi and /Yi in a write mode.

The data read/write apparatus further comprises a first transfer transistor part 20 connected between a sense amplifier part and a second transfer transistor part 21. The first transfer transistor part 20 is adapted to transfer the data on the bit lines BL and /BL, amplified by the bit line sense amplifiers 13, to the second transfer transistor part 21 in response to a block selection row address signal BS. The second transfer transistor part 21 is connected in a cross coupled manner between the first transfer transistor part 20 and the column decoding lines Yi and /Yi. The second transfer transistor part 21 is adapted to transfer the data transferred by the first transfer transistor part 20 to the column decoding lines Yi and /Yi in response to logic signals on the column decoding lines Yi and /Yi.

The data read/write apparatus further comprises a multiplexing circuit 17 for transferring the transferred data on the column decoding lines Yi and /Yi of a selected column to the read sense amplifier 15.

The operation of the data read/write apparatus for the semiconductor memory device with the above-mentioned construction in accordance with the first embodiment of the present invention will hereinafter be described in detail.

The read/write signal R/W is supplied to the column decoders 16 to discriminate between the read and write modes. In the read mode, one of the column decoders 16 is selected by the column address signal Col ADD. The selected column decoder 16 outputs a high logic signal to both the column decoding lines Yi and /Yi because write data is ignored by the read/write signal R/W. In the second transfer transistor part 21, a pair of NMOS transistors with a cross-coupled structure are turned on in response to the high logic signals on the column decoding lines Yi and /Yi. As a result, a current path is formed between the selected column decoder 16 and the bit line sense amplifier 13 of the same column through one of the column decoding lines Yi and /Yi, latched into low in logic by the bit line sense amplifier 13.

With reference to FIG. 6 which is a timing diagram illustrating the operation of the data read/write apparatus, the reference character a indicates a read cycle interval. In the read mode, the level of first high logic data on the complementary column decoding line /Yi becomes a little lower than that of first high logic data on the true column decoding line Yi because of a current path to the bit line sense amplifier 13. Similarly, the level of first low logic data on the complementary bit line/BL becomes a little higher than that of general low logic data under the influence of the complementary column decoding line/Yi.

The multiplexing circuit 17 transfers the data on the true and complementary column decoding lines Yi and /Yi of the selected column to the read sense amplifier 15. Then, the read sense amplifier 15 sense-amplifies the data transferred by the multiplexing circuit 17 and transfers the sense-amplified data to the data output buffer.

In the write mode, the read/write signal R/W is supplied to the column decoders 16 to discriminate between the read and write modes. Only one of the true and complementary column decoding lines Yi and /Yi selected by the column address signal Col ADD goes high in logic in response to write data received by the read/write signal R/W. Provided that the write data is high in logic, the true column decoding line Yi will become high in logic and the complementary column decoding line /Yi will become low in logic. To the contrary, if the write data is low in logic, the true column decoding line Yi will become low in logic and the complementary column decoding line /Yi will become high in logic. In the second transfer transistor part 21, one of the pair of NMOS transistors with the cross-coupled structure is turned on in response to the high logic column decoding line being connected to its gate terminal. The turned-on NMOS transistor transfers low logic data on the other column decoding line to the bit line sense amplifier 13 of the same column. The bit line sense amplifier 13 writes the transferred low logic data from the turned-on NMOS transistor into the memory cell 11 of the same column through a corresponding one of the bit lines BL and /BL. At this time, the bit line sense amplifier 13 restores the other bit line to high in logic.

with reference to FIG. 6, the reference character b indicates a write cycle interval. In the write mode, for example, if the true column decoding line Yi becomes low in logic, the complementary column decoding line /Yi goes high in logic. The true and complementary bit lines BL and /BL have inverted ones of the data values on the true and complementary column decoding lines Yi and /Yi, respectively.

On the other hand, the block selection row address signal BS is applied to gate terminals of NMOS transistors in the first transfer transistor part 20 to maintain blocks, not selected, at low logic states in the read/write modes. As a result, the block selection row address signal BS functions to prevent the bit lines of the non-selection blocks from being driven when the column decoding lines become high in logic. Also, the second transfer transistor part 21 with the cross coupled structure acts to prevent the flow of data in the non-selection columns.

In this manner, the data can be freely read and written with no increase in the number of input/output lines when a plurality of column decoders in one block are enabled. Therefore, the present invention has the effect of reducing the area of a semiconductor memory chip.

Referring to FIG. 4, there is shown a circuit diagram of a data read/write apparatus for a semiconductor memory device in accordance with a second embodiment of the present invention. As shown in this drawing, the construction of the second embodiment is the same as that of the first embodiment in FIG. 3, with the exception that the second transfer transistor part 21 includes a pair of NMOS transistors Q29 and Q30 cross coupled between the bit line sense amplifier 13 and the first transfer transistor part 20, and the first transfer transistor part 20 includes a pair of NMOS transistors Q31 and Q32 connected between the second transfer transistor part 21 and the column decoding lines Yi and /Yi and having their gate terminals for commonly inputting the block selection row address signal BS.

The operation of the second embodiment with the above-mentioned construction is performed in a similar manner to that of the first embodiment and a description thereof will thus be omitted. Noticeably, a load between the second transfer transistor part 21 and the first transfer transistor part 20 is separated from the column decoding lines Yi and /Yi in non-selection blocks. As a result, a small amount of power is consumed when the column decoding lines Yi and /Yi make a transition. However, a voltage drop may occur due to a loss resulting from threshold voltages of the NMOS transistors Q31 and Q32 in the first transfer transistor part 20 when the column decoding lines Yi and /Yi in a selected block become high in logic. In order to prevent such a voltage drop, the block selection row address signal BS to the first transfer transistor part 20 must be bootstrapped.

Referring to FIG. 5, there is shown a circuit diagram of a data read/write apparatus for a semiconductor memory device in accordance with a third embodiment of the present invention. As shown in this drawing, the construction of the third embodiment is the same as that of the first embodiment in FIG. 3, with the exception that the first transfer transistor part 20 includes a pair of NMOS transistors Q35 and Q36 connected between the second transfer transistor part 21 and the column decoding lines Yi and /Yi and having their gate terminals for commonly inputting the block selection row address signal BS, and the second transfer transistor part 21 includes a pair of NMOS transistors Q33 and Q34 connected between the bit line sense amplifier 13 and the first transfer transistor part 20 and having their gate terminals cross coupled to the column decoding lines Yi and /Yi.

The operation of the third embodiment with the above-mentioned construction is performed in a similar manner to that of the first embodiment and a description thereof will thus be omitted. Noticeably, it is not necessary to bootstrap the block selection row address signal BS to the first transfer transistor part 20 because the gate terminals of the NMOS transistors Q33 and Q34 are directly connected in the cross coupled manner to the column decoding lines Yi and /Yi.

As apparent from the above description, in the case where the data read/write apparatus of the present invention is applied in a semiconductor memory device, the true and complementary column decoding lines are used to perform the data read/write operations, instead of true and complementary data input/output lines connected respectively to the true and complementary bit lines. Therefore, the data read/write apparatus of the present invention has the effect of reducing the area of a semiconductor memory chip.

Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.