Tester for Integrated Circuits

The present invention relates to the field of testing of integrated circuits. More specifically, the present invention relates to the field of automatic testing or programming of integrated circuits.

Before an integrated circuit is placed in a final product, electrical testing must be performed to insure that the integrated circuit is not defective. With the increase in complexity of integrated circuits, the time required to perform the necessary testing has increased exponentially. The complexities of the testing process have become so great that testing has become a bottleneck in the manufacturing process. This is particularly true with custom integrated circuits such as programmable arrays and application specific integrated circuits (ASICs). For these custom circuits, specific, carefully designed testing programs must be performed to insure that the customized integrated circuit meets the customer's specifications.

Present testing techniques utilize a mechanical system whereby the integrated circuit is removed from a storage tray and placed into an electrical socket. This mechanical manipulation requires a certain amount of time. Because this manipulation must be repeated for each integrated circuit, the time lost to the mechanical manipulation is multiplied by the number of integrated circuits in a storage tray. Also, the mechanical manipulation of the integrated circuit increases the possibility that destruction of the chip may occur from cracking the package or bending the lead.

Disclosed is a device for providing temporary interconnection of a connected device to an integrated circuit, the integrated circuit having a plurality of signal leads extending from an encapsulating package, the device comprising: a tray for holding the integrated circuit; a gantry positioned above the tray for lowering a jig onto the integrated circuit in the tray, the jig having a plurality of conductive contacts positioned to come in contact with said leads when said gantry lowers the jig onto the integrated circuit; and a plurality of leads, one for each of the contacts, one end of the leads being connected to one of the contacts and the other end being connected to the device to be temporarily connected to the integrated circuit.

Also disclosed is a device for providing temporary interconnection of a connected device to more than one integrated circuit, the integrated circuits having a plurality of signal leads extending from an encapsulating package, the device comprising: a tray for holding the integrated circuit; a gantry positioned above the tray for lowering more than one jig onto the integrated circuit in the tray, the jigs having a plurality of conductive contacts positioned to come in contact with said leads when said gantry lowers the jigs onto the integrated circuits; and a plurality of leads, one for each of the conductive contacts, one end of the leads being connected to one of the contacts and the other end being connected to the device to be temporarily connected to the integrated circuit.

FIG. 1 is a perspective view of a conveyor system including the use of the present invention, for testing integrated circuits;

FIG. 2 is cross section view of one integrated circuit resting in a storage tray and a jig according to the present invention disposed above said integrated circuit;

FIG. 3 is an orthogonal cross section perpendicular to schematic view of FIG. 2;

FIG. 4 is a top view of the jig and pin structure of the jig shown in FIGS. 2 and 3;

FIG. 5 is a top view of another embodiment of the present invention wherein multiple jigs are used to test multiple integrated circuits at one time;

FIG. 6 is a top view of a plate, on which a tray of devices will sit, and which would have a support mechanism to interface with the row of contact heads shown in FIG. 5.

FIG. 7 is a top view of an arrangement of multiple jigs for testing all integrated circuits which would be stored in the tray of FIG. 6.

FIG 1 is a perspective view of an integrated circuit testing station in accordance with the present invention. Trays of integrated circuits 10 are placed in a rack 12. Conveyor 14 selectively selects trays from rack 12 to pass along beneath testing station 16 rejects/refill station 18 and laser marking station 20. Gantry 22 lowers testing apparatus onto the integrated circuits stored in the tray positioned below gantry 22. Gantry 24 removes the bad integrated circuits identified at testing station 16 from the tray and places the bad chips in tray 26. Previously tested, good integrated circuits are placed in tray 28 and are used to replace the bad circuits removed by gantry 24. This may be done by gantry 24 grabbing the integrated circuits using a vacuum grasping device or may be done manually. Once a complete tray of good integrated circuits is assembled, the tray is passed on to laser marking station 20 where the appropriate laser markings are burned into the surface of the integrated circuit using a laser manipulated by gantry 30. When marking is completed, the marked trays of good integrated circuits are placed on rack 32 and are subsequently sealed and shipped.

FIG. 2 is a cross sectional view of a jig 40 for testing an individual integrated circuit 42 placed in a tray 44. Tray 44 is fabricated from an appropriate molded plastic such as carbon filled, conductive black polyethene. Tray 44 must be capable of being molded into a specific configuration and stiff enough to avoid excess movement of the integrated circuits stored in tray 44 but flexible enough to avoid being brittle. Springs 46 and 48 provide buffering between integrated circuit 42 and jig 40 when jig 40 is lowered onto integrated circuit 42. Also, springs 46 and 48 provide compression to help hold integrated circuit 42 in place during testing. Leads 50-1 through 50-N are a plurality of leads, one for each lead of integrated circuit 42. Leads 50-1 through 50-N are fabricated from a suitably conductive and springy metal such as beryllium, copper, platinum, gold, silver, stainless steel, or flexible printed circuit board material. As jig 40 is lowered onto integrated circuit 42 leads 50-1 through 50-N make contact with the outside curvature of the leads of integrated circuit 42 at contact points 52-1 through 52-N. Because contact points 52-1 through 52-N are positioned above the curved portion of the leads of integrated circuit 42, the bottom surface of contact points 52-1 through 52-N will find a point of good contact regardless of the precise orientation of the surfaces of contact points 52-1 through 52-N. Contact points 52-1 through 52-N are also plated in gold to provide a high quality corrosion-free contact point for the shoulder of the leads of integrated circuit 42. Also, an optional particle coating comprising of the particle interconnect material disclosed in U.S. Pat. Nos. 4,804,132, and 5,033,697 may be formed on contact points 52-1 through 52-N. Contacts 52-1 through 52-N are designed to contact the shoulders of the leads of integrated circuit 42 to provide an area which may contact the lead at any point along the curvature and also because the shoulder area of the lead provides improved strength and less likelihood of package breakage as opposed to contacting the leads closer to the edge of the integrated circuit.

Leads 50-1 through 50-N are designed to provide an outward spring-type bias which is contained by retainer ring 54. Pins 56-1 through 56-m are provided from block 58 in between leads 50-1 through 50-N to position block 58 and retainer ring 54. The assembly is held in place by rubber band 60. The outward bias on leads 50-1 through 50-N is maintained by tension block 62. Tension block 62 and assembly block 64 are held to cap 66 by allen bolts 68 and 70. Tension is maintained between the upper portion of the assembly and block 58 by spring 72 which is held in place by screw 74. The tensioning features of leads 50-1 through 50-N provides buffering between the upper portion of jig 40, which is solidly connected to gantry 22 (FIG. 1), and the leads of integrated circuit 42 to avoid excessive force on the leads of integrated circuit 42 which may cause cracking of the encapsulating material of integrated circuit 42 or damage the leads themselves.

Integral with cap 66 is a printed circuit board (not shown) which makes contact to leads 50-1 through 50-N an may be soldered thereto. The printed circuit board provides separate electrical path from each lead 50-1 through 50-n to pins 76-1 through 76-N. Pins 76-1 through 76-N are inserted into corresponding sockets in gantry 22 of FIG. 1 which provide electrical interconnection to the circuitry which performs the electrical testing on integrated circuit 42. In this configuration, it is possible to imbed electrical components in the actual test head. FIG. 3 is an orthogonal cut-away view to the view of FIG. 2.

FIG. 4 is a top view of cap 66 showing a pin configuration where pins 76-1 through 76-N where N is equal to 15. Any number of pins 76-1 through 76-N can be formed in accordance with this invention to provide all necessary contact points to fully test integrated circuit 42 of FIGS. 2 and 3.

FIG. 5 is a top view of a rack 82 containing six jigs 40-1 through 40-6 in the embodiment shown in FIG. 5, an entire row of integrated circuits in tray 44 (FIG. 1) are tested and gantry 22 (FIG. 1) steps sequentially down each row of integrated circuits in tray 44. Gantry 22 holds the rack in place while the testing procedure is conducted and then moves to the next row for complete testing of the next row.

FIG. 6 is a top view of a plate for supporting a tray with integrated circuits positioned six circuits side-by-side for testing using rack 82 and testing jigs 40-1 through 40-6. FIG. 7 is a rack 84 comprising another embodiment of the present invention wherein sixty-six jigs 40 are positioned six wide and eleven deep to provide simultaneous testing of sixty-six integrated circuits. This will provide complete testing of an entire tray of sixty-six integrated circuits at one time. Of course, necessary driving circuitry for each of the jigs is required at testing station 16 (FIG. 1).

FIG. 7 is merely an example of a whole-tray test head array, 66 jigs is only one possible array and other array sizes are possible.

Although specific embodiments of the present invention described herein, this detailed description is not intended to be limiting to the scope of the invention. Other embodiments of the present invention will become apparent to those skilled in the art in light of the teachings of the specification. For example, the present embodiments show that the jigs are lowered onto the integrated circuit. However, any movement which properly positions the jig onto the leads of the tested integrated circuit will accomplish the desired result. The scope of the invention is limited only by the claims appended hereto wherein: