Display Controller

The present invention relates to display controllers which generate a display control signals for a flat display panel (such as LCD, plasma display, etc.) to be used for computer systems.

In a conventional display controller, a display area setting element is limited to only to one setting method. For example, in case a flat display panel having a size of 640 dots (horizontal direction) 400 dots (vertical direction) is used, the display area (display size) of controller is set to 640.times.400 dots, while in case a flat display of 640 dots (horizontal direction) by 200 dots (vertical direction) in size is used, the display area of the controller is changed to 640.times.200 dots. Therefore, in case a plurality of display areas are used in one system; namely in case two kinds of display areas such as the in sizes of 640.times.400 and 640.times.200 dots are provided, two different kinds of flat displays are prepared and the display hardware corresponding to the desired display mode is selected.

Since a conventional display controller employs only one kind of display area setting element, if only one display area is prepared or desired in one system, no problem occurs but in case many kinds of display areas are used depending on the software in one system, the display hardware used must be selected to correspond to the software output. Namely, many different types of software cannot be displayed on a single display. For example, in the case of a personal computer IBM-PC type as manufactured by IBM, a plurality of display areas such as 640.times.350 dots or 640.times.200 dots, etc. are prepared electronically available for use in the system. Since the display area is selected by the software, if the display hardware is fixed to say, 640.times.350 dots, software which supports only the display of 640.times.200 dots can no longer be used by the system.

It is therefore an object of the present invention to solve a problem that exists when a plurality of display areas cannot be displayed on only one display unit by a mode setting method of display controller in order to widen the application field even if the display areas change.

The display controller of the present invention provides a means for independently setting the maximum display capacity a (first display size) of the display and the actual portion of the display used area (second display size).

Since the present invention has a structure described above, display is possible, even when the actual display area (second display size) is smaller than the display capacity (first display size), by independently setting them. Therefore, even when several display areas are prepared, many display areas may be displayed using a single display capacity by setting the respective corresponding values for the display areas.

FIG. 1 illustrates an embodiment of a the present invention.

FIG. 2 represents a format of video data signal VD.

FIG. 3 indicates the correspondence between external buffer memory addresses and display positions.

FIG. 4 illustrates an example of an LCD display.

FIG. 5 is a practical example of a write address conversion circuit.

FIG. 6 illustrates a practical example of a blanking control.

FIG. 7 is a timing chart for the operation of the blanking control FIG. 6.

FIG. 8 illustrates an LCD display example having blank data displayed in the upper and lower, right and left sides.

An example of applying the present invention to an LCD controller (hereinafter referred to as video--LCD interface) which converts a video signal for a CRT type displayed into a signal for a liquid crystal display device (LCD) is shown in FIG. 1. Operation of this type of controller are explained in further detail hereunder.

The video data signal VD and for a CRT generally includes the display data period (hatched area) and the fly back period (outside the hatched area) as shown in FIG. 2. The fly back period can further be classified into four kinds of periods vertical back porch, vertical front porch, horizontal back porch and horizontal front porch. The video data is sequentially scanned from the left upper point of a display and input along the VD bus of FIG. 1 in serial and is fetched by a serial/parallel conversion circuit (hereinafter referred to as S/P conversion circuit) 115 which uses the dot clock signal which is synchronized with VD. This serial data is converted to parallel data in units of 8 bits for ease of writing the data into an external buffer memory 120 through a data bus 130. In this case, the write address is sequentially counted up every 8 bits from the upper left as shown in FIG. 3 and is then output by the write address counter 105 which counts up the write clock 131 which has a frequency that is reduced to an eighth of that of the dot clock CK by a frequency divider 104. The write address AW is switched in or selected every 8 dots and is then output to a write address bus 122 through a write address conversion circuit 106. A read/write control circuit 107 outputs an address switching signal 125 and, write control signals 126, 127 in synchronization with the rising and falling edges of the write clock 131. The address switching circuit 129 outputs one address of the write address 122 and read address 123 to an address bus 124 by an address switching signal 125. Accordingly, in the write operation, when the write address is switched in every 8 dots of the dot clock CK, the write address is output to the bus 124 at the former half of the write clock 131, the parallel data of 8 bits is input in synchronization with the control signal 125 from the S/P conversion circuit 115, the external buffer memory 120 is caused to enter the write mode in response to the control signal 127 and the parallel format data is then written to an address in memory 120 depending on the address data of bus 124.

Since the video data includes invalid data (fly back period) as described previously, control is carried out by a horizontal back porch decision circuit/horizontal dot counter 113, and vertical back porch decision circuit/vertical line counter 114 so that the S/P conversion circuit transfers only the desired display data neglecting such invalid data. A horizontal synchronous signal HSC is input as a counter start pulse and the dot clock CK as the counter clock to the horizontal back porch decision circuit/horizontal dot counter 113. A vertical synchronous signal VSC is likewise input as a counter start pulse and the horizontal synchronous signal HSC as the counter clock to the vertical back porch decision circuit/vertical line counter 14.

Next follows an explanation of operations, read from the external buffer memory. A basic clock for read operations is output from the clock generating circuit 111. A read address counter 108 counts on the read clock 132 signal which is obtained by dividing the frequency of the basic clock for read operations by two using a frequency divider 110 in the sequence fitted to LCD and generates the appropriate read addresses. The data read from external buffer memory 120 is input to a LCD data conversion circuit 118 through the data bus 130, converted to the format fitted to, or required by, the LCD and is then output through a blanking control 119 (described later). Moreover, the control signals (data shift clock, data latch pulse, etc.) required for the LCD are generated by an LCD control signal generating circuit 117 which counts up the clock pulses sent from the clock generating circuit 111 and then supplies them the LCD. During the read operation, a control signal 128 is output from the read/write control circuit 107 and the external buffer memory 120 is set to the read mode by the control signal 127. A counter signal 128 is output in synchronization with the write clock 131 when the read address counter 108 counts up the read clock 132 and the address readout has changed. With this signal 128, a latch 109 latches the read address and outputs such address data to the bus 123. During the read cycle immediately after the read address has changed, the address switching circuit 129 outputs the address data read out and data is read from the address of memory depending on this address data. Described above is an outline of the video-LCD interface.

Next, a circuit using the present invention will be explained in detail. First, a mode setting register 101 forms a register group for setting the drive system of the LCD and display area etc., including independently a register 102 for setting the maximum display capacity (first display size) of LCD and a register 103 for setting the actually used display area (second display size) for a video signal. For example, when the display is carried out in a display area of 640.times.350 dots (for example, EGA mode of personal computer IBM-PC manufactured by IBM) in a LCD having a capacity 640.times.480 dot matrix, 640.times.480 dots are set in the register 102 and 640.times.350 dots are set in the register 103. In this case, display is carried out as shown in FIG. 4 and the buffer memory corresponding to the display capacity (640.times.480 dots) can be acquired. Here, since the video data (hatched area) only has as many as 350 lines effective, it is necessary to give an offset to the address for writing data to the buffer memory in order to realize the display as shown in FIG. 4. Such a conversion is carried out by a write address conversion circuit 106. The maximum count number counted is sent to a write address counter 105 by D103 indicating the display area. In the case of the display shown in FIG. 4, it is enough to add an address corresponding to the blank data of the upper display screen area or,

as the offset. The circuit for adding such an offset using an adder is shown in FIG. 5 as an example of this circuit.

Here, an offset address register 501 has the written offset value of the address described above. Since several offset values are necessary depending on the combination of display capacity and display area, a plurality of registers are prepared. Only one value is selected through a selector 502 from such registers. In this case, the selector 502 conducts selection based on the output signals D102 and D103 from the mode setting register of FIG. 1. The offset value of 16 bits, selected as explained above, is output to bus 503 and is then input to an adder 504, of 16 bits, together with the output WA from the write address counter 105. As a result, an address corresponding to adding the offset address to the ordinary write address AW is obtained from the output AAW. Namely, since the write address counter 105 only counts the value as being 640 dots.times.350 lines for the count value set by the signal D103, the address conversion circuit 106 adds the blank area for 640 dots.times.65 lines to the address AW. Therefore, the input video data is not stored in the buffer memory 120 for the first 5200 bytes of storage addressed and is stored in the successive addresses. When contents of mode setting registers 102, 103 are changed, the maximum count value of write address counter 105 and the offset value of address conversion circuit 106 also change. Therefore, various display areas can be set for the display having various display capacities.

When writing is conducted with this method, writing is not carried out to the buffer memory of the part corresponding to the blank data shown in FIG. 4 and the valid video data is written from the address next to that of an offset. On the other hand, since read operation is carried out for an entire part of the display capacity, namely of 640.times.480 dots, read operation is also carried out to the buffer memory to which any data is not written as described above and data transfer to LCD is carried out. Accordingly, if read operation is carried out and data is transferred to LCD, unwanted data is probably displayed in some cases to the upper and lower blank data areas. In order to avoid such an event, the contents of buffer memory is once cleared (when the power switch is turned ON) by preparing the memory clear sequence or also control must be done so that data is not transferred to LCD for the blanking data. The component which executes the latter control is prepared as the blanking control 119. This function disables data output to the LCD corresponding to the blanking data on the basis of information in register 102 and register 103. In this case, data output is disabled (fixed to a low level) during data transfer from the 1st line to 56th line and data transfer from the 416th line to 480th line. An example of a blanking control circuit is shown in FIG. 6. Operations of this circuit will be briefly explained hereunder. The input signal LINEC is an output signal from a line counter of 9 bits of LCD. This LCD line counter is comprised in the LCD control signal generating circuit 117 of FIG. 1 and provided as a 9-bit counter to count up the number of lines of LCD (480 lines in this case). This counter output LINEC is input to a decoder 601 in the blanking control 119. This decoder receives contents D102 and D103 of the mode registers 102 and 103 and switches the decoder output. Here, based on the signals D102 and D103, the decoder outputs a signal 607 by decoding the signal LINEC which indicates the content of the 65th line from which the display area starts and also outputs a signal 608 by decoding the signal LINEC indicating the 415th line from which the display area comes to the end and the blanking data starts. A timing chart for those signals is shown in FIG. 7. These signals are further input to the R/S flip-flop 602 to generate the enable signal LCDEN of LCD data. Only when LCDEN is in a high level state is LCD data enabled and the LCD data LCDD output from the LCD data conversion circuit 118 is output to the LCD through the respective AND gates 603 to 606. In other cases, the outputs of AND gates 603 to 606 are fixed to a low level and are not displayed on the LCD. It should be noted here that the maximum count value is set for the read address counter 108 and the line counter in the LCD control signal generating circuit 117 by the signal D102 which indicates the display capacity of the LCD. Therefore, the read address counter 108 counts up the addresses to repeatedly read the data indicating LCD display capacity from the buffer memory 120. Moreover, the line counter repeats the counting for 480 lines as shown in FIG. 7. Based on the output of this line counter, the enable signal LCDEN is output for the 350 lines from the 65th line to the 414th line during the count value of 480 lines. Therefore, the count value of these counters changes depending on changes in the signals D102 and D103 and various display areas may be set for display of various display capacities an resolutions.

In summary, the display controller of FIG. 1 defines the storage capacity corresponding to the display capacity of the display unit in the buffer memory 120 and in the writing operation does not store video data for the storing capacity of 640 dots.times.65 lines but stores the data for 640 dots.times.350 lines from the next address. Accordingly, display is realized in the preset display area by reading data from the addresses of display capacity and then displaying such data. But, in case data only is read, if erroneous data is stored in the address in the buffer memory not storing the video data, erroneous display occurs. In the present invention, however, since data is output to the display unit only during the period of scanning a desired display area by detecting the display position for display and data is set to a fixed level not allowing display during other periods, display is not carried out erroneously in the area outside a preset display area.

As explained above, display in the area outside the desired display area can be blanked off perfectly. Operations for display of 640.times.350 dots of data on an LCD of 640.times.480 dots capacity have been described above. If it is requested here to carry out the display of 640.times.200 dots, only changing the content of register 103 for setting the display area is required for 640.times.200 dots. Thereby, the address offset 503 of write address conversion circuit 106 and output of decoder 601 of blanking control 119 are also changed automatically and the display as shown in FIG. 8 can be obtained.

According to the present invention described previously, the register 102 for setting display capacity and the register 103 for setting display area are provided independently. Therefore, various .displays such as 640.times.350 dots and 640.times.200 dots, as well as 640.times.480 dots can be presented on the one LCD, for example, an LCD having a display capacity of 640.times.480 dots only by changing a value in register 103 without changing display hardware. In the embodiment of the present invention, a register which is a storage means ensuring random access for read and write operation has been used as a means for setting display capacity and display area but other means can also be used in place of this register. For example, the input terminals are provided for simplification to respective elements and setting may be changed by changing input signals to these terminals. In this explanation, the blanking areas are located in the upper and lower portions as shown in FIG. 4 but this explanation can also be applied to the case where the blanking areas exist in the upper and lower, right and left areas as shown in FIG. 8. In the latter case, only little modifications are necessary to the offset address selector 501 in the write address conversion circuit and decoder 601 in the blanking control. Moreover, an LCD has been considered for explanation but controllers for other flat displays (plasma display, for example) can also be used.

The present invention also realizes the display of various display modes (display areas) with only one unit of display. Therefore, it is no longer necessary to change the hardware (display) for each change of display mode by the software and the display can keep up with various software. It is particularly effective to apply the present invention to a lap top computer utilizing a flat display panel because a single kind of flat display can be flexibly used for various software.