High Breakdown Voltage Semiconductor Device

1. Field of the Invention

The present invention relates to a high breakdown voltage semiconductor device.

2. Description of the Related Art

In a high breakdown voltage semiconductor device, dielectric isolation method is known an an effective method of isolating each element.

FIG. 1 shows a conventional high breakdown voltage diode obtained by using such a dielectric isolation method. Reference numeral 101 denotes a p.sup.+ type silicon substrate, and there is formed a substrate wafer in which the p.sup.+ type silicon substrate and an n.sup.- (or p.sup.-) type silicon substrate are bonded to each other by a direct bonding method. Reference numeral 102 is an oxide film of a bonding interface. The n.sup.- type substrate of the substrate wafer is selectively etched up to the depth reaching the oxide film 102, so that a groove is formed. Thereby, an n.sup.- type layer 103, which is an island element region, is formed. In the groove, an oxide film 104 is formed inside and a polycrystalline silicon film 105 is buried therein. An n.sup.+ type layer 106, serving as a cathode region, is formed in the central surface portion of the island n.sup.- type layer 103 isolated from other portions by the oxide films 102 and 104. Then, p.sup.+ type layer 107, serving as an anode region, is formed in the peripheral surface portion. As result, a diode is formed. P.sup.+ layers 108 and 109 are formed along the oxide films 102 and 104 so as to enclose the surroundings of the island n.sup.- type layer 103. The p.sup.+ type layers 108 and 109 are formed so as to allow large current to flow. A cathode electrode 110 and an anode electrode 111 are formed on the n.sup.+ type layer 106 and p.sup.+ type layer 107, respectively.

In the above diode, if reverse bias is applied to the portion between the anode and the cathode and a depletion layer extends to the n.sup.- type layer 103, and all applied voltages are applied between the n.sup.+ type layer 106 of the surface portion and the p.sup.+ type layer 108 of the bottom portion. Therefore, in order to obtain a diode having sufficient high breakdown voltage, it is required that a distance d between the n.sup.+ type layer 106 and the p.sup.+ type layer 108 be sufficiently largely made. More specifically, in order to obtain voltage of 600V, d=45 .mu.m is needed.

If the thickness of the n.sup.- type layer 103 is made larger so as to ensure the above-mentioned distance d, the groove for the element isolation in a lateral direction must be deepened in accordance with the thickness of the n.sup.- type layer 103. This makes it extremely difficult to perform the element isolation in the lateral direction.

As mentioned above, according to the semiconductor device having the conventional dielectric isolation structure, it is necessary to make the thickness of the high resistance semiconductor layer whose depletion layer extends sufficiently large so as to obtain a sufficient high breakdown voltage. Due to this, there is a problem that the element isolation becomes difficult to be performed.

The following explains the other examples of the semiconductor device having the conventional dielectric isolation structure.

FIG. 2 shows a conventional lateral type diode having the conventional dielectric isolation structure. An n.sup.- type silicon layer (active layer) 133 is formed on a semiconductor substrate 131 via an insulating film 132 for isolation. An n.sup.+ type layer 134 having a high impurity concentration is formed in the bottom portion of the active layer 133. A p-type anode layer 135 is formed in the active layer 133 and an n-type cathode layer 136 is formed in a portion which is away from the p-type anode layer 135 with a predetermined distance, and an anode electrode 137 and a cathode electrode 138 are formed on the anode layer 135 and the cathode layer 136, respectively.

In the above-mentioned lateral type diode, for example, considering a reverse bias state in which the anode electrode 137 and the substrate 131 are grounded and a positive voltage is applied to the cathode electrode 138, the voltage to be applied to the cathode is applied to the depletion layer extending to the active layer under the p-type anode layer 137, and the insulation film 132 for isolation.

Due to this, if the thickness of the active layer 133 under n-type cathode layer 136 is thin, a large electric field is shared at this portion, and an electric field concentration occurs in the vicinity of the curved portion of the bottom of the n-type cathode layer 136, and avalanche breakdown is generated at a low applied voltage. In order to avoid the above problem and realize the sufficient high breakdown voltage, the thickness of the active layer 133 is conventionally set to be 40 .mu.m or more.

However, if the thickness of the active layer is large, a deep isolation groove is needed for the element isolating in the lateral direction by a V-groove, and an area of the isolation groove reaction becomes large. Due to this, work processing becomes difficult and an effective area of the element becomes small, so that the cost of an integrated circuit having the high breakdown voltage element increases.

As mentioned above, in the high breakdown voltage semiconductor device having the conventional dielectric isolation structure, if the active layer is thin, a sufficient breakdown voltage cannot be obtained. Moreover, if the active layer is thick, the element isolation in the lateral direction becomes difficult.

On the other hand, there is known a conventional power IC in which a high breakdown voltage element such as a high breakdown voltage driving circuit and a low breakdown voltage device such as a low breakdown voltage control circuit are formed on a single substrate. There are various uses of this conventional power IC. For example, an inverter circuit may be produced by using p-channel FETs or IGBTs as high breakdown voltage devices, thereby simplifying a level shifter or a high-side gate circuit.

However, because of structural limitations of the device, the high breakdown voltage driving circuit and low breakdown voltage control circuit cannot be manufactured by a common process. Thus, one of them is first formed, and then the other. For example, in the prior art, when a p-channel high breakdown voltage MOSFET is fabricated, a deep p type well is formed, as in a DMOS, and the device is formed therein. Thus, there is no steps common to those of the process of forming a logic portion. Consequently, the number of steps, the time for manufacture and the manufacturing cost increase.

In addition, in the conventional high breakdown voltage MOSFET, the breakdown voltage decreases if the dosage of impurities in the active region is increased to reduce the turn-on resistance.

In order to solve the above-mentioned problems, an object of the present invention is to provide a semiconductor device having high breakdown voltage using the dielectric isolation structure wherein a sufficiently high breakdown voltage can be obtained even if a relative thin high resistance semiconductor layer is used.

Another object of the present invention is to provide a high breakdown voltage semiconductor apparatus wherein a high breakdown voltage driving circuit and a low breakdown voltage control circuit are simultaneously formed, thereby greatly reducing the manufacturing cost and decreasing the turn-on resistance while maintaining a high breakdown voltage.

According to the present invention, there is provided a high breakdown voltage semiconductor apparatus comprising:

a substrate having an insulating layer formed thereon;

a high resistance semiconductor layer of a first conductivity type formed on said insulating layer;

a base region of a second conductivity type formed selectively in a surface region of said high resistance semiconductor layer;

a source region of the first conductivity type formed in said base region;

a drain region formed in said high resistance semiconductor layer;

a gate electrode formed on a region between said source region and said drain region, with a gate insulating film interposed between said gate electrode and said region between said source region and aid drain region;

a source electrode provided in contact with said base region and said source region; and

a drain electrode provided in contact with said drain electrode region,

wherein a high resistance semiconductor region of the second conductivity type is provided between said insulating layer and said high resistance semiconductor layer of the first conductivity type, and said base region reaches said high resistance semiconductor region of the second conductivity type.

According to the present invention, there is also provided a high breakdown voltage semiconductor apparatus comprising:

a substrate having an insulating layer formed thereon;

a high resistance semiconductor layer of a first conductivity type formed on said insulating layer;

a base region of the first conductivity type formed selectively in a surface region of said high resistance semiconductor layer;

a drift region of a second conductivity type formed selectively in the surface region of said high resistance semiconductor layer so as not to reach said insulating layer;

a source region of the second conductivity type formed in said base region;

a drain region formed in said drift region;

a gate electrode formed on a region between said source region and said drift region, with a gate insulating film interposed between said gate electrode and said region between said source region and said drift region;

a source electrode provided in contact with said base region and said source region;

a drain electrode provided in contact with said drain region,

wherein the dosage of impurities in said high resistance semiconductor layer is 2.times.10.sup.12 cm.sup.-2 to 3.times.10.sup.12 cm.sup.-2 and the dosage of impurities in said drift layer is 1.times.10.sup.12 cm.sup.-2 to 2.times.10.sup.12 cm.sup.-2.

Furthermore, according to the present invention, there is provided a high breakdown voltage semiconductor apparatus comprising:

a substrate having an insulating layer formed thereon;

a high resistance semiconductor layer of a first conductivity type formed on said insulating layer;

a base region of the first conductivity type formed selectively in a surface region of said high resistance semiconductor layer;

a drift region of a second conductivity type formed selectively in the surface region of said high resistance semiconductor layer so as not to reach said insulating layer;

a source region of the second conductivity type formed in said base region;

a buffer layer of the second conductivity type formed in said drift region;

a drain region of the first conductivity type formed in said buffer region;

a gate electrode formed on a region between said source region and said drift region, with a gate insulating film interposed between said gate electrode and said region between said source region and said drift region;

a source electrode provided in contact with said base region and said source region;

a drain electrode provided in contact with said drain region,

wherein the dosage of impurities in said high resistance semiconductor layer is 2.times.10.sup.12 cm.sup.-2 to 3.times.10.sup.12 cm.sup.-2 and the dosage of impurities in said drift layer is 1.times.10.sup.12 cm.sup.-2 to 2.times.10.sup.12 cm.sup.-2.

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.

FIGS. 1 and 2 are cross sectional views showing a conventional high breakdown voltage diode;

FIG. 3 is a view showing a diode relating a first embodiment of the present invention;

FIG. 4 is a view showing a MOSFTT relating to the other embodiment of the present invention;

FIG. 5 is a view showing a MOSFTT of an embodiment in which the structure of FIG. 4 is modified;

FIG. 6 is a view showing a MOSFET of an embodiment in which the structure of FIG. 4 is modified;

FIG. 7 is a cross-sectional view showing a high breakdown voltage MOSFET according to a first embodiment of a second aspect of the present invention;

FIG. 8 shows a flow of manufacturing steps for fabricating the high breakdown voltage MOSFET shown in FIG. 7 simultaneously with a logic portion;

FIG. 9 is a graph showing the variation of the breakdown voltage of the high breakdown voltage MOSFET shown in FIG. 7, in the case where the dosage of impurities in an n type drift layer was varied, with the dosage of impurities in a p type drift layer being used as a parameter;

FIG. 10 is a graph showing the relationship between the drain voltage and drain current of the high breakdown voltage MOSFET shown in FIG. 7;

FIG. 11 is a graph showing the relationship between the drain current and gate voltage of the high breakdown voltage MOSFET shown in FIG. 7;

FIG. 12 is a cross-sectional view of an IGBT according to a second embodiment of the second aspect of the invention;

FIG. 13 is a graph showing the relationship between the drain voltage and drain current, when the dosage in the p type buffer layer of the IGBT shown in FIG. 12 was used as a parameter; and

FIG. 14 is a graph showing the switching waveform of the IGBT shown in FIG. 12.

In a high breakdown voltage MOS semiconductor apparatus according to a first aspect of the present invention, a lateral type MOS semiconductor device is formed on an SOI substrate obtained by directly bonding two substrates to each other. Specific examples of the MOS semiconductor apparatus will now be described with reference to FIGS. 3 to 6.

FIG. 3 is a lateral type diode relating to the embodiment of the present invention. The n.sup.- type high resistance silicon layer (active layer) 303 is formed on the silicon substrate 301 through the silicon oxide film (first insulating film) 302. The thickness of the silicon oxide film 302 is about 1 to 5 .mu.m. The n-type active layer 303 has the total amount of impurities of 1.0.times.10.sup.10 /cm.sup.2 to 2.0.times.10.sup.12 /cm.sup.2, preferably 0.5.times.10.sup.12 to 1.8.times.10.sup.12 /cm.sup.2. The p type anode layer 304 having high impurity concentration and the n type cathode layer 305 having high impurity concentration are formed in the active layer 303 to be separated from each other with a predetermined distance. The p type anode layer 304 and the n type cathode layer 305 are formed to have the depth which does not reach to the silicon oxide film 302 as shown in the drawing. If voltage V.sub.1 and voltage V.sub.2 are applied to the p type anode layer 304 and the n type cathode layer 305, respectively, and voltages V.sub.1 and V.sub.2 are higher than the voltage Vsub of the silicon substrate 301, a p type channel region 303a is formed in the bottom portion of the high resistance silicon layer 303. Since the p.sup.- type channel region 303a has positive charge, capacitance is formed together with the substrate 301. Thereby, influence of the potential of the substrate 301 is shielded, and the high resistance silicon layer 303 is prevented from being depleted.

FIG. 4 is a MOSFET showing other example in which the p.sup.- type channel region 303a shown in FIG. 123 is formed. The n.sup.- type active layer 303 is formed on the substrate 301 through the silicon oxide film 302. The p type base layer 311 and the n type drain layer 312 are formed in the active layer 303. The p type base layer 311 and the n type drain layer 312 are formed to have the depth which does not reach to the silicon oxide film 302.

The n type source layer 313 is formed in the p type base layer 311, and the surface portion of the p type base layer 311, which is sandwiched between the n type source layer 313 and the n.sup.- type active layer 303, is used as a channel region, and the gate electrode 315 is formed on the channel region through the gate oxide film 314 having a thickness of about 60 nm.

The MOSFET shown in FIG. 4 is used as a switch on the high potential side of the circuit. If the MOSFET is turned on, both source potential and the drain potential become high potential to the substrate 301. In this case, if the influence of the potential of the substrate 301 is not shielded, the active layer 303 is depleted, and on resistance of the MOSFET becomes extremely high.

However, the distance l between the p type base layer 311 and the oxide film 302 and impurity concentration of the p type base layer 311 are suitably selected, a hole is injected from the p type base layer 311 and the p.sup.- channel region is formed in the bottom portion of the active layer 303 when the source potential V.sub.1 is a certain constant value or more. Thereby, the active layer 303 is prevented from being depleted.

In this case, the source potential Vp to form the p.sup.- type channel region can be obtained from the following equation.

wherein (q: 1.6.times.10.sup.-19 C) CN: N type impurity concentration and .epsilon.: dielectric constant (1.05.times.10.sup.-12 F/cm).

VP is preferably 10V or less. That is, l.sup.2 .ltoreq.20.epsilon./qC.sub.N.

In order to set VP to zero, the distance l may be changed to 0. In other words, the structure shown in FIGS. 5 and 6 may be used.

In a device shown in FIG. 6, a p.sup.- type layer 318 is provided between an n.sup.- type active layer 303 and an oxide film 302. A p type base layer 311 reaches the p.sup.- type layer 318. The device shown in FIG. 6 is an n.sup.- channel type MOSFET. However, the present invention is applicable to a p-channel type MOSFET in which the conductivity type is reversed.

A high breakdown voltage semiconductor apparatus according to a second aspect of the invention, a shallow drift region of a second conductivity type is formed on an SOI substrate of a first conductivity type. With this structure, as compared to a structure wherein a substrate of the first conductivity type with a uniform impurity concentration is used, the dosage of impurities in an active layer of the first conductivity type can be greatly increased. Accordingly, the turn-on resistance can be remarkably decreased while a high breakdown voltage is maintained.

In addition, since the SOI structure is adopted, devices can easily be isolated electrically from one another. Thus, noise can be effectively prevented.

Furthermore, in the high breakdown voltage semiconductor apparatus according to the second aspect of the invention, a drift region is formed without forming a deep well of the second conductivity type. Thus, the drift region can be formed in a step of forming a logic portion. As a result, the step of forming the logic portion can be utilized in many steps. Accordingly, the high breakdown voltage device and low breakdown voltage logic portion can be simultaneously formed, the number of manufacturing steps can be reduced, and the manufacturing cost can be remarkably reduced.

The high breakdown voltage semiconductor apparatus according to the second aspect of the invention will now be described with reference to FIGS. 7 to 14.

FIG. 7 is a cross-sectional view of a high breakdown voltage p channel MOSFET according to a first embodiment of the second aspect of the invention. In FIG. 7, an SiO.sub.2 layer 2 is formed on a semiconductor substrate 1. A high resistance n type active layer 3 is formed on the SiO.sub.2 layer 2. An n type drift layer 4 is formed on the high resistance n type active layer 3. A p type drift layer 5 is formed on the surface of the n type drift layer 4. In addition, an n type base layer 6 is formed adjacent to the p type drift layer 5 on the surface of the n type drift layer 4. The n type drift layer 4 may reach the oxide layer 2.

A p.sup.+ -drain region 7 is formed in the p type drift layer 5, and a p.sup.+ -source region 8 is formed in the n type base layer 6. In addition, an n.sup.+ -contact region 9 for fixing the potential of the active layer 3 is formed in the n type base layer 6.

A gate insulating film 10 is formed on a region between the p type drift layer 5 and p.sup.+ -source region 8, and a gate electrode 11 is formed on the gate insulating film 10. A drain electrode 12 is formed on the p.sup.+ -drain region 7, and a source electrode 13 is formed on the p.sup.+ -source region 8. A high breakdown voltage p channel MOSFET is thus constituted.

The high breakdown voltage p channel MOSFET having the above structure is fabricated in the following manner.

Two substrates, one of which is provided with an SiO.sub.2 layer, are directly bonded to each other, thereby obtaining an SOI-structure semiconductor substrate in which the SiO.sub.2 layer 2 and high resistance n type active layer 3 are formed on the n type semiconductor substrate 1. Phosphorus is ion-implanted in the high resistance n type active layer 3 with a dosage of 2.times.10.sup.12 cm.sup.-2 to 3.times.10.sup.12 cm.sup.-2, thus forming the n type drift layer 4. Further, boron is ion-implanted in the n type drift layer 4 to a depth of 1 to 2 .mu.m with a dosage of 1.times.10.sup.12 cm.sup.-2 to 2.times.10.sup.12 cm.sup.-2, thus forming a p type drift layer 5. If the thickness of the p type drift layer 5 is less than 1 .mu.m, the breakdown voltage lowers. If the thickness of the p type drift layer 5 is more than 2 .mu.m, the dosage in the n type drift layer 4 decreases.

Subsequently, the n type base layer 6 (having a thickness of 2 .mu.m when the p type drift layer 5 is 1 .mu.m thick) for forming a p channel and preventing punch-through is formed by using a channel implantation technique for controlling a threshold of a CMOS. Then, the gate insulating film 10, which is 15 nm thick, is formed and a polysilicon is deposited. Thus, the gate electrode 11 is formed on the side of the source region 8, and a field plate is formed on the side of the drain region 7.

Thereafter, using the gate electrode 11 and field plate as mask, boron is ion-implanted in a self-align manner. In the case where the p type drift layer 5 is 1 .mu.m thick, the drain region 7 and source region 8 each having a thickness of 0.5 .mu.m are formed. In order to fix the potential of the active layer 3, the n.sup.+ -contact region 9 is formed adjacent to the source region 8. Furthermore, the source electrode 13 and drain electrode 12 are formed. Thus, a high breakdown voltage p channel MOSFET is completed.

In the above-described manufacturing process, the manufacturing steps used for forming the CMOS, and not the manufacturing steps used for forming a conventional DMOS, are adopted. This process, therefore, includes many steps common to the steps of forming a low breakdown voltage device such as a logic circuit. FIG. 8 shows an example of the steps for simultaneously forming a high breakdown voltage device (p channel MOSFET) and a low breakdown voltage device (logic portion).

Of the 13 steps illustrated in FIG. 8, 10 steps are common to the manufacture of the p channel MOSFET and logic portion. Thus, the number of steps and the manufacturing time can be greatly reduced.

FIG. 9 shows the breakdown voltage of the high breakdown voltage p channel MOSFET having the above structure in the case where the dosage of impurities in the n type drift layer 4 was varied, with the dosage in the p type drift layer 5 being used as parameter (0 to 2.12.times.10.sup.12 cm.sup.-2). The data shown in FIG. 9 relates to the MOSFET with a drift length of 15 .mu.m, which was formed in the high resistance n type active layer 3 having a thickness of 5 .mu.m. The n type active layer 3 is formed on the SiO.sub.2 layer 2 having a thickness of 2 .mu.m.

As can be seen from the graph of FIG. 9, a high breakdown voltage is obtained when the dosage in the n type drift layer 4 is 2.times.10.sup.12 cm.sup.-2 to 3.times.10.sup.12 cm.sup.-2 and the dosage in the p type drift layer 5 is 1.times.10.sup.12 cm.sup.-2 to 2.times.10.sup.12 cm.sup.-2. When the dosage in the p type drift layer 5 is 0, i.e. when the p type drift 5 is not formed, the dosage in the n type drift layer 4 cannot be increased in order to obtain a high breakdown voltage. Thus, the device resistance cannot be decreased. On the other hand, when the dosage in the p type drift layer 5 is 1.times.10.sup.12 cm.sup.-2 to 2.times.10.sup.12 cm.sup.-2, the dosage of the n type drift layer 4 can be increased while a high breakdown voltage is maintained. As a result, the device resistance can be decreased.

Besides, a high breakdown voltage of 500V was obtained in the MOSFET having a drift length of 60 .mu.m, which was formed in the high resistance n type active layer 3 having a thickness of 15 .mu.m. The active layer 3 was formed on the SiO.sub.2 layer 2 having a thickness of 3 .mu.m. In this case, the dosage in the n type drift layer 4 was 2.7.times.10.sup.12 cm.sup.-2, and the dosage in the p type drift layer 5 was 1.5.times.10.sup.12 cm.sup.-2.

FIG. 10 shows the relationship between the drain voltage and drain current in the case where the gate voltage was 5V, with respect to the above MOSFET. In this case, the turn-on resistance was 180.OMEGA..multidot.mm.sup.2. FIG. 11 shows the relationship between the drain current and gate voltage in the case where the source-drain voltage was 3V.

FIG. 12 is a cross-sectional view of an IGBT according to a second embodiment of the second aspect of the invention. In FIG. 12, an SiO.sub.2 layer 22 is formed on an n type semiconductor substrate 21, and a high resistance n type active layer 23 is formed on the SiO.sub.2 layer 22. An n type drift layer 24 is formed on the high resistance n type active layer 23, and a p type drift layer 25 is formed in a surface portion of the n type drift layer 24. An n type base layer 26 is formed adjacent to the p type drift layer 25 in a surface portion of the n type drift layer 24.

A p type buffer layer 20 is formed in the p type drift layer 25 and n type drift layer 24. An n.sup.+ -drain region 27 is formed in the p type buffer layer 20, and a p.sup.+ -source region 28 is formed in the n type base layer 26. An n.sup.+ -contact region 29 for fixing the potential of the active layer 3 is formed in the n type base layer 26.

A gate insulating film 30 is formed on a region between the p type drift layer 25 and p.sup.+ -source region 28, and a gate electrode 31 is formed on the gate insulating film 30. A drain electrode 32 is formed on the p.sup.+ -drain region 27, and a source electrode 33 is formed on the p.sup.+ -source region 28. An IGBT is thus constituted.

The IGBT shown in FIG. 12 is formed in the same process as the MOSFET shown in FIG. 7, except that the p type buffer layer 20 is formed in the p type drift layer 25 and n type drift layer 24. The p type buffer layer 20 may be formed by ion-injecting boron before or after the field implantation.

FIG. 13 is a graph showing the relationship between the drain voltage and drain current, when the dosage in the p type buffer layer 20 of the IGBT shown in FIG. 12 was used as a parameter. It is understood from FIG. 13 that if the dosage of the p type buffer layer 20 is set at or below 2.5.times.10.sup.13 cm.sup.-2, sufficient conductivity modulation can be effected and current/voltage characteristics can be improved. The dosage in the p type buffer layer 20 is preferably 1.times.10.sup.13 cm.sup.-2 to 2.5.times.10.sup.13 cm.sup.-2.

FIG. 14 is a graph showing a switching waveform of the IGBT shown in FIG. 12. It is understood from FIG. 14 that the switching speed is high, i.e. about 0.5 .mu.sec.

As has been described above, according to the second aspect of the present invention, the shallow drift region of the second conductivity type is formed on the SOI substrate of the first conductivity type. As compared to the case where a substrate of the first conductivity type with a uniform impurity concentration is used, the dosage of impurities in an active layer of the first conductivity type can be greatly increased. Accordingly, the turn-on resistance can be remarkably decreased while a high breakdown voltage is maintained.

In addition, since the SOI structure is adopted, devices can easily be isolated electrically from one another. Thus, noise can be effectively prevented.

Furthermore, a drift region is formed without forming a deep well of the second conductivity type. Thus, the step of forming the logic portion can be utilized in many steps. Accordingly, the high breakdown voltage device and low breakdown voltage logic portion can be simultaneously formed, and the manufacturing cost can be remarkably reduced.