US 5,588,151 AGrant

Apparatus and Method for Communication Switching Including Providing Information Overflow Indications

Issue Date:1996-12-24

•12 Claims

•6 Drawing Sheets

Abstract

Communication switching apparatus for providing communication between a multiplicity of digital information processors, the apparatus including a plurality of ports each communicating with at least one of the multiplicity of digital information processors, and a port interconnector operative to provide communication between more than one pair of ports from among the plurality of ports, characterized in that, when an overflow of information is caused at the port interconnector or at one of the plurality of ports, an overflow indication is provided to the digital information processors which communicate with the port interconnector or with the overflowed one of the plurality of ports.

Metadata

Assignee

Lannet Data Communications Ltd.

Inventors

Jacob Segal
Josef Ben-Moshe
Zvika Weinstock
Zvika Harnik

Application Information

Application Number:US 5255007

Filing Date:1995-09-08

Priority Date:1994-01-31

Art Unit:232

Classifications

IPC:

G06F 1300

Field of Search:

395370800;200;370.6;500;200.21;200.1360;44.1

Patent Drawings (6 sheets)

Description

Field of the Invention

The present invention relates to switching systems.

Background of the Invention

State of the art switching systems are described in the following publications:

"An In-Depth Look at Three Switching Hubs", (Translated reprint of) Telecoms & Reseaux, No. 69, September, 1993, IDG Communications, France;

"The Switching Advantage", Kalpana EtherSwitch Publication, Fall, 1991;

Axner, David H., "Evaluating Switching Hub Architectures", Business Communications Review, July 1993, pp. 35-39; and

"Novell Application Performance Testing", Synernetics Performance Networking, Aug. 25, 1993.

Summary of the Invention

The present invention seeks to provide an improved switching system and methods for using the same.

There is thus provided in accordance with a preferred embodiment of the present invention communication switching apparatus for providing communication between a multiplicity of digital information processors, the apparatus including a plurality of ports each communicating with at least one of the multiplicity of digital information processors, and a port interconnector operative to provide communication between more than one pair of ports from among the plurality of ports, characterized in that, when an overflow of information is caused at the port interconnector or at one of the plurality of ports, an overflow indication is provided to the digital information processors which communicate with the port interconnector or with the overflowed one of the plurality of ports.

Further in accordance with a preferred embodiment of the present invention each individual port includes an information overflow sensor and indicator operative to sense an overflow arriving from an individual digital information processor communicating therewith and to provide an overflow indication to the digital information processors communicating with the individual port.

Still further in accordance with a preferred embodiment of the present invention the port interconnector includes an information overflow sensor and indicator operative to sense an overflow arriving from an individual digital information processor and to provide an overflow indication to the digital information processors associated with the port interconnector.

Additionally in accordance with a preferred embodiment of the present invention each digital information processor is operative to refrain from transmitting information when it encounters a traffic congestion symptom and wherein the overflow indication includes an artificially generated occurrence of the traffic congestion symptom.

Also in accordance with a preferred embodiment of the present invention the communication provided includes LAN communication.

Further in accordance with a preferred embodiment of the present invention the multiplicity of processors includes at least one printer.

Still further in accordance with a preferred embodiment of the present invention the multiplicity of processors includes at least one workstation.

Additionally in accordance with a preferred embodiment of the present invention the multiplicity of processors includes at least one computer.

Brief Description of the Drawings

The present invention will be understood and appreciated from the following detailed description, taken in conjunction with the drawings in which:

FIG. 1 is a simplified functional block diagram of a plurality of interconnected communication switching systems 10 which are each constructed and operative in accordance with a preferred embodiment of the present invention;

FIG. 2 is a simplified block diagram of an individual one of ports 60; and

FIG. 3 is a simplified flowchart of a preferred method for selective activation of congestion symptom simulation.

FIG. 4 is a simplified flowchart illustration of a preferred method by which a back-pressurizing port of FIG. 1 generates back-pressure by simulating traffic on a line connecting elements 30 and 60 or 50 and 60;

FIG. 5 is a simplified flowchart illustration of a preferred method by which the RX buffer full flag of FIG. 4 is updated as a result of a port sending packets to the switching fabric; and

FIG. 6 is a simplified flowchart illustration of a preferred method by which the RX buffer full flag of FIG. 4 is updated as a result of a port receiving packets from digital information processors.

Attached herewith are the following appendices which are useful in generating a communication switching module which is constructed and operative in accordance with a preferred embodiment of the invention shown and described herein:

Appendices 1-5 are program listings which relate to a first LSI Logic ASIC (application specific integrated circuit) chip netlist which is useful in constructing communication switching apparatus constructed and operative in accordance with a preferred embodiment of the present invention. Specifically, Appendix 1 includes computerized starting information useful for setting up a working environment of LSI Logic tools;

Appendix 2 is the netlist itself according to which the chip layout may be generated;

Appendix 3 is RAM generating information;

Appendix 4 is a listing of test vectors useful in verifying the operation of the chip; and

Appendix 5 is layout information indicating a preliminary placing of the elements of the ASIC chip.

Appendices 6-9 are program listings which relate to a second LSI Logic ASIC chip netlist which is useful in constructing communication switching apparatus constructed and operative in accordance with a preferred embodiment of the present invention. Specifically, Appendix 6 includes computerized starting information useful for setting up a working environment of LSI Logic tools;

Appendix 7 is the netlist itself according to which the chip layout may be generated;

Appendix 8 is a listing of test vectors useful in verifying the operation of the chip; and

Appendix 9 is layout information indicating a preliminary placing of the elements of the ASIC chip.

Appendices 10-13 are program listings which relate to a third LSI Logic ASIC (application specific integrated circuit) chip netlist which is useful in constructing communication switching apparatus constructed and operative in accordance with a preferred embodiment of the present invention. Specifically, Appendix 10 includes computerized starting information useful for setting up a working environment of LSI Logic tools;

Appendix 11 is the netlist itself according to which the chip layout may be generated;

Appendix 12 is a listing of test vectors useful in verifying the operation of the chip; and

Appendix 13 is layout information indicating a preliminary placing of the elements of the ASIC chip.

Appendix 14 is a program listing for a Motorola 68HC11K1 microcontroller useful in the module.

Appendices 15-32 are listings of computerized manufacturing instructions for various layers and other portions of a printed circuit board; and

Appendices 33-42 are JEDEC files for programming GALs.

As a matter of practicality, these appendices will not appear as part of the printed patent, but remain as part of the application file.

Detailed Description of Preferred Embodiments

Reference is now made to FIG. 1 which is a simplified functional block diagram of a plurality of interconnected communication switching systems 10 which are each constructed and operative in accordance with a preferred embodiment of the present invention. Each system 10 typically interfaces with and provides communication between a multiplicity of digital information processors 20 such as but not limited to PC's 30, printers 40 and workstations 50. Alternatively or in addition, each system 10 may interface with one or more similar systems 10 as shown.

Each switching system 10 typically includes a plurality of ports 60, each of which is connected to one or more of the digital information processors 20. The plurality of ports 60 are interconnected through a switching fabric 70, also termed herein a "port interconnector".

It is a particular feature of the present invention that, when an overflow of information arrives from one or more digital information processors 20 which flow toward a common element such as an individual port 60 or the switching fabric 70, an overflow indication is provided to the digital information processor/s which flow toward the common element.

According to one preferred embodiment of the present invention, the ports 60 each comprise back pressurizing ports which implement the above overflow indication providing feature. Alternatively, the switching fabric 70 may comprise a back pressurizing switching fabric which implements the above overflow indication providing feature.

It is appreciated that, commonly, conventional digital information processors are operative to refrain from transmitting information when they encounter a traffic congestion symptom. Accordingly, the back pressurizing port or back pressurizing switching fabric of the present invention is preferably operative to artificially generate an occurrence of the traffic congestion symptom.

For example, in Ethernet and in the IEEE 802.3 protocol, the associated digital information processor only transmits information over the communication link (e.g. the communication link to a corresponding port, in FIG. 1) if it does not sense a carrier signal. If a carrier signal is sensed, no information is transmitted. Accordingly, the back pressurizing port or back pressurizing switching fabric of the present invention is preferably operative to transmit an artificial "carrier signal" to the offending digital information processor.

In the present specification, the term "carrier signal" is intended to include any type of signal which indicates to a digital information processor receiving the carrier signal that there is traffic and that, therefore, no information should be transmitted at the present time.

Reference is now made to FIG. 2 which is a simplified block diagram of an individual one of ports 60.

The port 60 preferably includes a line interface 100 which receives and transmits information from and to the digital information processors. The line interface 100 preferably carries out all information processor-switching system interface operations such as regulating use of the transmission line between the system and the information processor, interpretation of data and extracting clocks from data, all during reception, as well as converse operations during transmission to the information processors.

A received information buffer 110 stores information received from the digital information processors via the line interface 100 until it can be dealt with by controller 120. According to a first preferred embodiment of the present invention, an entire unit of data, such as an entire packet or an entire cell, is received from the digital information processors and stored in RX buffer 110 before the unit of data is forwarded by controller 120 to a switching fabric interface 130. Alternatively, data is transferred to the switching fabric interface 130 as it is received in which case the RX buffer 110 is only employed to stored data which cannot be transferred due, typically, to congestion at the switching fabric interface.

The switching fabric interface 130 performs all necessary interface operations in order to transmit and receive data from the back-pressurizing port 60 to the switching fabric 70 and vice versa.

A TX buffer 140 is provided which stores information being transferred from the switching fabric interface 130 to the digital information processors via line interface 100. Typically, information is transferred as soon as it is received unless there is congestion at the line interface 100. Alternatively, however, an entire data unit, such as a packet or cell, is accumulated in the TX buffer before being transferred to the line interface 100.

A congestion symptom simulator 150 is operative to simulate a symptom of congestion which is transferred to the digital information processors via the line interface 100, thereby to prevent the processors from transmitting any more information until the congestion situation is alleviated. For example:

a. In Ethernet or IEEE 802.3 applications, a carrier is transmitted to the digital information processors. The carrier may, for example, comprise a square wave of frequency 5 MHz transmitted for 1.8 msec, followed by a 5.6 microsec pause, and then followed by the square wave again, and so on.

If a digital information processor initiates transmission during one of the pauses, this occurrence is dealt with the same as an occurrence of collision, which eventuality is dealt with in the IEEE 802.3 protocol.

Preferably, the carrier is discontinued if information arrives from the switching fabric interface which is intended for the digital information processors whose transmission it is desired to block. In this case, the information is allowed to reach the digital information processor, via TX buffer 140 and the line interface since transmission of genuine information to the digital information processor is effective in blocking transmission from the processor. Once all the information has reached the processor, and if the port 60 is still congested, transmission of the carrier signal is renewed.

b. In Token Ring applications (IEEE 802.5), the processors and the port to which they are linked belong to a Ring which shares a single token. Each processor only transmits when it is in possession of the token. In this case, the congestion symptom simulator 150 prevents the processors from ever obtaining a token while congestion of the port exists. This is typically done by utilizing the priority system. The processors only obtain a token when their own priority is greater than or equal to the token's priority. Therefore, the processors' ability to gain the token can be eliminated by giving the token a priority level, such as priority level 7, which exceeds the priority level of all of the processors.

The operation of all units of the port 60 are controlled by a controller 120. The controller is responsible for:

a. Monitoring transfer of information from the line interface 100 into the RX buffer, from the RX buffer onto the switching fabric interface 130, from the switching fabric interface 130 onto the TX buffer and from the TX buffer onto the line interface; and

b. Selectively activating congestion symptom simulation by the simulator 150. A preferred method for selective activation of congestion symptom simulation is now described with reference to FIG. 3.

FIG. 3 is a simplified flowchart of a preferred method for selective activation of congestion symptom simulation. The method of FIG. 3 preferably includes the following steps:

STEP 200: Initially, the back pressurizing function is not activated. In the illustrated embodiment, this is implemented by deactivation of the congestion symptom simulator 150.

STEP 210: A congestion criterion is inspected. For example, the criterion may be whether or not there is a predetermined amount of space left in the RX buffer 110. If the congestion criterion is not satisfied, return to step 200. If the congestion criterion is satisfied (STEP 220), operate the back pressurizing function, or, in other words, activate congestion symptom simulator 150.

STEP 230: A congestion criterion is inspected. For example, the criterion may be whether or not there is a predetermined amount of space left in the RX buffer 110. If the congestion criterion is satisfied, return to step 220. If the congestion criterion is not satisfied, return to step 200.

A very detailed description of a preferred method for constructing a communication switching module constructed and operative in accordance with one preferred embodiment of the present invention is as follows:

a. Elements U70-U73 of the module each comprise a first ASIC chip, also termed herein "MTR", which is generated as follows:

i. Generate digital UNIX files whose contents is the contents of the listings of Appendices 1 to 5, except that the first line of each page should be ignored. One file should be generated for Appendix 3. One file should be generated for each of the three pages of Appendix 1. A plurality of files should be generated for Appendices 2 and 4 as indicated by the pagination thereof. Two files, named "15a4170s.bdcmd" and "15a4170s.cfun" should be generated for Appendix 5 as indicated by the pagination of Appendix 5. Editing software suitable for the Sun workstation may be employed to generate these digital files.

ii. Set up a LSI Logic working environment on a Sun workstation.

iii. Initialize the working environment using the three files generated using Appendix 1, which may be named "setuproj.dat", "LCB007.CELLIBS" and "M.sub.-- T.sub.-- R.OPTSPEC".

iv. Install the LSI memory library specified by the RAM information of Appendix 3.

v. Purchase from LSI Logic a Cellbase 1 micron ASIC using a LCB7050P die in a 160PQFP package designed in accordance with Appendices 1-3 and 5. Use the test vectors of Appendix 4 for verification.

b. Element U14 of the module comprises a second ASIC chip, also termed herein "MBLI", which is generated as follows:

i. Generate digital UNIX files whose contents is the contents of the listings of Appendices 6 to 9, except that the first line of each page should be ignored. One file should be generated for Appendix 7. One file should be generated for each of the two pages of Appendix 6. A plurality of files should be generated for Appendix 8, as indicated by the pagination thereof. Two files, named "MBLI.sub.-- IO.sub.-- PINS.BDCMD" and "MBLI.sub.-- IO.sub.-- PINS.BLOCKS" should be generated for Appendix 9 as indicated by the pagination of Appendix 9. Editing software suitable for the Sun workstation may be employed to generate these digital files.

ii. Set up a LSI Logic working environment on a Sun workstation.

iii. Initialize the working environment using the two files generated using Appendix 6, which may be named "setuproj.dat", and "MBLI.sub.-- IO.sub.-- PINS.OPTSPEC".

iv. Purchase from LSI Logic a Cellbase GATE ARRAY ASIC using a L100073P die in a 208PQFP package designed in accordance with Appendices 6, 7 and 9. Use the test vectors of Appendix 8 for verification.

c. Elements U41 and U39 of the module each comprise a third ASIC chip, also termed herein "MPR", which is generated as follows:

i. Generate digital UNIX files whose contents is the contents of the listings of Appendices 10 to 13, except that the first line of each page should be ignored. One file should be generated for Appendix 11. One file should be generated for each of the two pages of Appendix 10. A plurality of files should be generated for Appendix 12 as indicated by the pagination thereof. Two files, named "L5A4124.bdcmd" and "mpr.cfun" should be generated for Appendix 13 as indicated by the pagination of Appendix 13. Editing software suitable for the Sun workstation may be employed to generate these digital files.

ii. Set up a LSI Logic working environment on a Sun workstation.

iii. Initialize the working environment using the two files generated using Appendix 10, which may be named "setuproj.dat" and "L5A4124.OPTSPEC".

iv. Purchase from LSI Logic a GATE ARRAY ASIC using a L100066P die in a 144PQFP package designed in accordance with Appendices 10, 11 and 13. Use the test vectors of Appendix 12 for verification.

c. Generate 18 DOS files from the listings of Appendices 15-32 respectively. The file names should be as follows:

Appendix 15--424L10G.LGR

Appendix 16--424L1G.LGR

Appendix 17--424L2G.LGR

Appendix 18--424L3G.LGR

Appendix 19--424L4G.LGR

Appendix 20--424L5G.LGR

Appendix 21--424L6G.LGR

Appendix 22--424LGG.LGR

Appendix 23--424L7G.LGR

Appendix 24--424L8G.LGR

Appendix 25--424L9G.LGR

Appendix 26--424DG.LGR

Appendix 27--424EG.LGR

Appendix 28--424FG.LGR

Appendix 29--UN424A.APR

Appendix 30--UN424A.DRL

Appendix 31--UN424A.MFG

Appendix 32--424LHG.LGR

d. Purchase a printed circuit manufactured in accordance with the 18 DOS files generated in step c, from a printed circuit manufacturer such as Diceon Electronics Inc., 18522 Von Karman, Irvine, Calif. 92714, U.S.A.

e. Generate a DOS file from the listing of Appendix 14 and program a 32K.times.8, 120 nanosec EPROM (code 27C256-120), using a suitable programming device such as a Data I/O Model 2900, commercially available from Data I/O Corporation, POB 97046, Redmond, Wash., 98072-9746, U.S.A.

f. Generate JEDEC files in accordance with the listings of Appendices 33-42. Use these 10 files to program 10 respective GALs of the following types:

Appendices 33--40:GAL 22V10B-10

Appendix 41: GAL 16V8-15

Appendix 42: GAL 6001.

g. Purchase the off-the-shelf elements listed in the following partlist:

h. Assemble the parts listed in the above partlist onto the printed circuit board of step d, by matching the printed labels on the printed circuit board to the reference column of the partlist. The following instructions should preferably be followed:

1. Use jumpers to short legs 1-8, 2-7, 3-6, 4-5, of CMC1-CMC8.

2. Make the following patches, using wire-wrap black wire, 30 AWG, on the print side between:

U27(8)-U27(1)

U27(7)-U27(2)

U27(6)-U27(6)

U74(10)-U109(1)

U106(1)-U74(11)

J1B(10)pad-U74(10)

3. Connect the resistor RS-85-4.7K between resistor's R11 pad and J1B(10).

4. Disconnect the following legs: U74(11), U109(1).

5. Disconnect the wire which routed to U107(17) prior to socket insertion.

Notes:

The resistor should not stand out from the print side.

The resistor leg which is connected to the pad should have Teflon isolation.

The following parts should remain unassembled: Component side:

1. U78,75,200,90,91,110,21,61

2. C600,500,466

3. R500,501,681,683,677,678,743,744,666,134,135,189,185,227

R221,265,259,303,297,731,745,733

4. D19,36

5. L2

6. TP1-9, 11-13

7. JMP8,9

8. CON1,2,4-6

Print side:

1. C160,169,168

2. R634,635,470-473,466-469,50,51,665,668,321,700-703

R354-357,313,308,311,315,318,316,317,322,330,331,326,325,

R333,334,338,339,346,347,342,341,48,49,46,47,675,42,43,54,

R55,81,82,600,601,44,45,65,69,64,68,635,634,671,672,673,669

R748,742,741,674,496,10

3. D50

The EPROM of step e should be inserted into the U26 socket.

The 10 GALs programmed in accordance with Appendices 33-42 should be inserted into the following sockets, respectively:

Appendix 33: U85

Appendix 34: U36

Appendix 35: U38

Appendix 36: U35

Appendix 37: U37

Appendix 38: U84

Appendix 39: U17

Appendix 40: U16

Appendix 41: U12

Appendix 42: U107.

The assembled board is preferably used with LET 36/20 HUBS, commercially available from Lannet Data Communications Ltd., Tel Aviv, Israel.

FIG. 5 is a simplified flowchart illustration of a preferred method by which the RX buffer full flag of FIG. 4 is updated as a result of a port sending packets to the switching fabric; and

FIG. 6 is a simplified flowchart illustration of a preferred method by which the RX buffer full flag of FIG. 4 is updated as a result of a port receiving packets from digital information processors.

All of the steps in the flowchart illustrations of FIGS. 4-6 are fully disclosed in the description of a preferred implementation of the present invention which appears on page 12, third complete paragraph on to the paragraph bridging pages 33 and 34 and which makes reference to Appendices 1-42 described in the Brief Description section of this specification. The components which chiefly implement each of the steps of FIGS. 4-6 are as follows:

Steps 320, 380, 430, 440, 450, 460, 560, 570 and 580 of the flowcharts of FIGS. 4-6 are implemented chiefly in the component described in paragraph a on page 12.

Steps 300, 340, 360, 540 and 550 of the flowcharts of FIGS. 4 and 6 are implemented chiefly in the components described in paragraph a on page 12, paragraph b on page 13 and paragraph c on page 14. All three of these components are initialized by a microprocessor termed U26 on the partlist on page 19 (second part from the bottom of page 19). The code for the U26 microprocessors is provided in the listing of Appendix 14 as described in paragraph e on page 15.

Steps 400, 410, 420 and 470 of the flowchart of FIG. 5 are implemented chiefly in the components described in paragraph a on page 12 and paragraph b on page 13.

Steps 330, 350 and 370 of the flowchart of FIG. 4 are implemented chiefly in the components described in paragraph b on page 13 and paragraph c on page 14.

Step 310 of the flowchart of FIG. 4 is implemented chiefly in the component described in paragraph b on page 13.

All of the above components are mounted on a printed circuit board described on page 15 in paragraphs c and d.

It is appreciated that the chips described above with reference to the Appendices are intended only to provide an extremely detailed disclosure of a sample embodiment of the present invention and is not intended to be limiting.

It is appreciated that various features of the invention which are, for clarity, described in the contexts of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features of the invention which are, for brevity, described in the context of a single embodiment may also be provided separately or in any suitable subcombination.

It will be appreciated by persons skilled in the art that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention is defined only by the claims that follow:

Claims

We claim:

1. Communication switching apparatus for providing LAN communication among a multiplicity of digital information processors, each said processor conventionally including an activity detector operative to cause the processor to refrain from transmitting information onto a medium when the activity detector encounters a symptom of activity on said medium, the switching apparatus including: a plurality of ports each communicating with at least one of the digital information processors via said medium; a LAN port interconnector interconnecting at least two of said plurality of ports; and an overflow indicator, sensing overflow at at least one of: the LAN port interconnector; and at least one of the plurality of ports; the switching apparatus being characterized in that the overflow indicator, upon sensing said overflow, provides an artificially generated symptom of activity to at least one said activity detector.

2. Apparatus according to claim 1 wherein said symptom comprises LAN traffic.

3. Apparatus according to claim 1 wherein said LAN port interconnector comprises an Ethernet interconnector.

4. Apparatus according to claim 1 wherein said LAN port interconnector comprises a Token Ring interconnector and wherein said symptom of activity comprises inability to obtain a token.

5. Apparatus according to claim 1 wherein said LAN port interconnector comprises an IEEE 802.3 standard interconnector.

6. Apparatus according to claim 1 wherein each individual port includes an information overflow sensor and indicator operative to sense an overflow and operative to provide an overflow indication to the digital information processors communicating with the individual port.

7. Apparatus according to claim 1 wherein said LAN port interconnector comprises an IEEE 802.5 standard interconnector.

8. Apparatus according to claim 1 wherein all of said multiplicity of digital information processors are operative to refrain from transmitting information onto said medium upon encountering the symptom of activity on said medium and would otherwise transmit information.

9. A method for providing LAN communication among a multiplicity of digital information processors, each said processor conventionally including an activity detector operative to cause the processor to refrain from transmitting information onto a medium when the activity detector encounters a symptom of activity on said medium, the method including: providing a plurality of ports each communicating with at least one of the digital information processors via said medium; providing a LAN port interconnector interconnecting at least two of said plurality of ports; and sensing overflow at at least one of: the LAN port interconnector; and at least one of the plurality of ports; and upon sensing said overflow, providing an artificially generated symptom of activity to at least one said activity detector.

10. A method according to claim 9 wherein said symptom comprises LAN traffic.

11. A method according to claim 9 wherein said step of sensing overflow comprises the step of inspecting for a congestion criterion.

12. Communication switching apparatus for providing LAN communication among a multiplicity of digital information processors for which a token is defined, each said processor conventionally including a token possession detector operative to cause the processor to refrain from transmitting information onto a medium when the token possession detector detects that the processor does not possess a token, the switching apparatus including: a plurality of ports each communicating with at least one of the digital information processors via said medium; a LAN port interconnector interconnecting at least two of said plurality of ports; and an overflow indicator, sensing overflow at at least one of: the LAN port interconnector; and at least one of the plurality of ports; the switching apparatus being characterized in that the overflow indicator includes a priority indicator which, upon sensing said overflow, elevates the token's priority such that the token possession detector of at least one of said processors detects that its processor does not possess the token.

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Abstract

Description