Digital Trimming for Frequency Adjustment

1. Field of the Invention

The present invention relates to digital trimming for frequency adjustment for correcting a temporal shift of a time reference signal with regard to absolute time. More particularly, the digital trimming to correct the temporal shift of the time reference signal is performed in an IC (integrated circuit) used in a watch.

2. Description of Related Art

In an IC used in a watch, for instance, digital trimming methods have been used to correct a temporal shift of a time reference signal output from an oscillator circuit with regard to absolute time. One type of digital trimming method uses a frequency-divided signal functioning as the time reference signal. Another type of digital trimming method uses a fundamental signal that is expanded/compressed only by a required correction amount (digital trimming amount) at a predetermined correction period (digital trimming period).

In FIG. 13, a digital trimming circuit employing a conventional digital trimming method is shown. This digital trimming circuit includes an oscillator circuit 10 oscillated at a frequency of 32 KHz as a basic oscillation. A variable frequency dividing circuit 20 is connected to the output of the oscillator circuit 10. The variable frequency dividing circuit 20 uses 1/2-frequency dividers 22, 24 and 26 which each have data set functions. A frequency dividing circuit 30 generates a time reference signal S.sub.T from the output of the variable frequency dividing circuit 20. A digital trimming period forming circuit 40 generates a digital trimming period signal S.sub.F based on the signal from the frequency dividing circuit 30. The digital trimming circuit further includes a digital trimming execution timing signal forming circuit 50 for generating a digital trimming timing signal VCW based upon the digital trimming period signal S.sub.F and the basic oscillation clock f.sub.0 having the frequency of 32 KHz. Correction data supplying means 60 supplies, for example, a 3-bit correction data (CBA).sub.2 to a frequency division rate setting circuit 70. When the digital trimming execution timing signal VCW has been generated, the frequency division rate setting circuit 70 transfers the correction data (CBA).sub.2 to the respective set inputs "S" of the 1/2-frequency dividers 22, 24, 26. The correction data in position "A" is transferred to the set input of the 1/2-frequency divider 22. The correction data in position "B" is transferred to the set input of the 1/2-frequency divider 24. The correction data in position "C" is transferred to the set input of the 1/2-frequency divider 26.

The digital trimming execution timing signal forming circuit 50 is constructed of a latch 52 and a NOR gate 54. The latch 52 receives the digital trimming period signal S.sub.F as the data input "D" when the clock input CL is under a high level (hereinafter referred to as an "H" level). The latch 52 transfers this data input to the invert output XM, and maintains the invert output XM when the clock input CL is under a low level (hereinafter referred to as an "L" level). The NOR gate 54 receives as an input the digital trimming period signal S.sub.F and the invert output XM.

The frequency dividing ratio setting circuit 70 has three AND gates 72, 74 and 76. Each AND gate receives the VCW signal and one of the bits from the 3-bit correction data (CBA).sub.2.

Normally, the time period "T" of the digital trimming period signal S.sub.F is a relatively long time period defined from several seconds to several hundred seconds. As shown in FIG. 14, the digital trimming period signal S.sub.F is obtained by frequency dividing the output signal (4 KHz) of the 1/2-frequency divider 26 by the frequency dividing circuit 30. When the signal level of this digital trimming period signal S.sub.F is changed from the "H" level into the "L" level, all of the frequency signals, 32 KHz-signal, 16 KHz-signal, 8 KHz-signal, and 4 KHz-signal, are in the "L" state. Before S.sub.F changes state, the signal level of the digital trimming period signal S.sub.F and the signal level of the original oscillation clock f.sub.0 as the clock input CL are in the "H" state, and the signal level of the invert output XM of the latch 52 is in the "L" state. Then the digital trimming period signal S.sub.F changes from the "H" level to the "L" level. After this change of states and during a t/2 time period (1/2 time period) where the basic oscillation clock f.sub.0 is under the "L" level, the signal level of the invert output XM is maintained at the "L" state. As a consequence, the digital trimming execution timing signal VCW with the "H" level is produced over the 1/2 time period.

When the signal state of the digital trimming timing signal VCW is at the "H" level, and the correction data (CBA).sub.2 is (011).sub.2, for example, the content of the variable frequency circuit 20 is set to the condition of the point "P" during this t/2 time period. If, for example, the correction data (CBA).sub.2 is (111).sub.2, then the content of the variable frequency dividing circuit 20 is set to the condition of the point "Q" during this t/2 time period. As a result, when the variable frequency dividing circuit 20 is set to the point P, the period reference signal S.sub.T is shortened by a digital trimming amount T.sub.p =(1/32 KHz).times.3=92 microseconds with respect to the digital trimming time period. Also, when the variable frequency dividing circuit 20 is set to the point Q, the period reference signal S.sub.T is shortened by a digital trimming amount T.sub.Q =(1/32 KHz).times.7=214 microseconds with regard to the digital trimming time period.

In this example and in the preferred embodiments, the correction data is 3-bit data to make the circuits simpler. However, the correction data can be any number of bits and is usually on the order of 5 bits. When a 5-bit correction data is used, the maximum digital trimming amount reaches 0.98 milliseconds.

In general, assume that a number of bits in the correction data is selected to be "K," a digital trimming amount .DELTA.T is given by the following equation:

For example, in the case of an N-bit correction data, the correction data value "K" is 0 through 2.sup.N -1. Therefore, the digital trimming rate ".eta." corresponding to the digital trimming amount within a unit time is given by the following formula:

Also, the digital trimming solution ".mu." corresponding to the minimum digital trimming rate is given by the following equation:

The above-described digital trimming apparatus suffers from the following problems, especially if the apparatus is used in a watch which has motor drive pulse outputs or an acoustic output. With respect to the period reference signal S.sub.T, the necessary digital trimming amount .DELTA.T has been performed during every time digital trimming time period T. If the digital trimming amount .DELTA.T becomes large, then the period reference signal S.sub.T is considerably expanded/compressed at a time instant when the digital trimming operation is executed. As a result, if the motor drive pulse output and the acoustic output happened to be superimposed at the digital trimming timing, the waveforms of the respective output pulses would be changed. This waveform change may cause a deterioration in the stability of the operation of the motor drive or an interruption in the acoustic outputs. In order to avoid this problem, the digital trimming timings are shifted from the timings of the motor drive pulse outputs and the acoustic outputs.

This solution may not always solve the problem. There are long periods of "unknown" time if a watch has a chronograph function in which a motor must be rotated at a fast time period for a long time. Long periods of time may be created if a multi-hand/multi-motor watch, which uses a plurality of motors, are controlled in an asynchronous mode. Also, a watch may have a melody output function in which an acoustic output is continued for a long time. In these situations, the digital trimming timing cannot be shifted; however, the digital trimming operations should be interrupted. Therefore, the time reference signal may drift from the original time reference signal during these long interrupt time periods.

The present invention solves the above-described problems, and therefore, provides a digital trimming apparatus capable of achieving a necessary digital trimming rate while suppressing an expansion/compression amount of a time reference signal at a time instant when a digital trimming operation is carried out. In this invention, an interference occurring between a digital trimming timing and a predetermined output timing are avoided.

In the present invention, a dispersive digital trimming method is employed. A plurality of digital trimming operations with short digital trimming are dispersively executed during one digital trimming time period. In a digital trimming apparatus according to the present invention, a digital trimming amount supplying means executes the digital trimming operation with a predetermined digital trimming amount in response to the initiation control pulse signal. The time reference signal produced is based upon the original oscillation signal derived from the oscillating means. The apparatus also includes a digital trimming amount-to-pulse number converting means for producing the initiation control pulse signal within one digital trimming time period. The number of pulses corresponds to the correction data for designating the digital trimming amount which should be executed within one digital trimming time period.

The digital trimming amount-to-pulse number converting means may have a digital trimming timing interval decision means for producing a timing reference signal. This timing reference signal has a time period shorter than one digital trimming time period based upon the basic oscillation frequency. This converting means may also have a digital trimming timing decision means for outputting the initiation control signal at each time period. The decision means counts the number of pulses in the time period for the timing reference signal until that number reaches the pulse number corresponding to the correction data.

There are other ways to construct the digital trimming amount-to-pulse number converting means. A digital trimming timing equally allocating means will allocate the generation of the initiation control signal so as to create substantially equal time intervals. These time intervals are obtained by dividing one digital trimming time period by the number of pulses necessary to shorten the reference time signal. The digital trimming amount applying means may include a variable frequency dividing means. In the alternative, this digital trimming amount applying means may have complementary signal forming means to generate an in-phase signal and a reverse phase signal based upon the original oscillation signal. A signal selecting means is used to selectively output the in-phase signal and the reverse phase signal in response to the control signal. The digital trimming amount-to-pulse number converting means may include a microcomputer. The digital trimming apparatus may be a semiconductor integrated circuit.

The digital trimming amount-to-pulse number converting means produces the initiation control pulse signal within one digital trimming time period, the number of pulses corresponds to the correction data for designating the digital trimming amount which should be executed within one digital trimming time period. Since the initiation control pulse signals are obtained within one digital trimming time period, a plurality of digital trimming operations are dispersively performed within one digital trimming time period. The digital trimming amount of the digital trimming amount applying means is coincident with such a value calculated by dividing, for instance, the digital trimming amount to be operated within one digital trimming time period by the pulse number. Then, the digital trimming amount required within one digital trimming time period is applied. Therefore, the digital trimming amount can be coincident with the logic digital trimming rate required for the time reference signal.

The expansion/reduction amount for the time reference signal at the digital trimming timing can be suppressed. In other words, since the digital trimming operation with the minimum expansion/reduction amount corresponding to the time period of the basic oscillation signal can be realized, interference caused by the digital trimming timing and a predetermined output timing may be negligible, or greatly suppressed.

The digital trimming timing equal-allocating means generates the initiation control signal. This means allocates pulses at substantially equivalent time intervals. The time intervals are calculated by dividing one digital trimming time period by the above-described pulse number. Therefore, a plurality of digital trimming timings are not concentrated into a portion of one digital trimming time period, but are dispersed. As a result, a reduction in the negative affect of the output timings is achieved.

When the complementary signal forming means generates the in-phase signal and the reverse phase signal in response to the basic oscillation signal, and also the signal selecting means for selecting the in-phase signal and the reverse phase signal to be output are employed as the digital trimming amount applying means, the digital trimming operation with the minimum digital trimming amount equal to a half time period of the original oscillation signal can be performed. The above-described benefits are achieved by the present invention.

For a better understanding of the present invention, reference is made to the following detailed description in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic block diagram showing an arrangement of a digital trimming circuit according to a first preferred embodiment of the present invention;

FIG. 2 is a timing chart for explaining an operation of the digital trimming circuit according to the first preferred embodiment;

FIG. 3 is a schematic block diagram representing an arrangement of a digital trimming circuit according to a second preferred embodiment of the present invention;

FIG. 4 is a flow chart for explaining an operation of a microcomputer employed in the second preferred embodiment;

FIG. 5 is a schematic block diagram indicating an arrangement of a digital trimming circuit according to a third preferred embodiment of the present invention;

FIG. 6 is a timing chart for explaining an operation of a binary rate multiplier in the third preferred embodiment;

FIG. 7 is a timing chart for explaining an operation of a synchronous differentiating circuit employed in the third preferred embodiment;

FIG. 8 is a timing chart for explaining a lead digital trimming operation in the third preferred embodiment;

FIG. 9 is a timing chart for explaining a delay digital trimming operation in the third preferred embodiment;

FIG. 10 is a schematic block diagram representing an arrangement of a digital trimming circuit according to a fourth preferred embodiment of the present invention;

FIG. 11 is a timing chart for indicating a producing condition of the digital trimming timing signal ZDmn in the fourth preferred embodiment;

FIG. 12 is a timing chart for explaining an operation of the clock selecting circuit in the fourth preferred embodiment;

FIG. 13 is a schematic block diagram showing an arrangement of the conventional digital trimming circuit; and

FIG. 14 is a timing chart for explaining an operation of the conventional digital trimming circuit.

Referring now to the accompanying drawings, preferred embodiments of the present invention will be described. FIG. 1 is a schematic block diagram showing a circuit arrangement of a digital trimming apparatus according to a first preferred embodiment of the present invention. This digital trimming apparatus of FIG. 1 may be performed by a semiconductor integrated circuit. This digital trimming circuit 100 includes an oscillator circuit 110 oscillated at a basic oscillation frequency f.sub.0 of 32 KHz. A 1/2-frequency divider 120, which has a data setting function, divides the basic oscillation frequency f.sub.0. The 1/2-frequency divider 120 functions as a digital trimming amount applying means. Two 1/2-frequency dividers 132 and 134 generate signals having frequencies of 8 KHz and 4 KHz, respectively. Frequency dividing circuit 130 divides the 4 KHz signal to obtain a time reference signal S.sub.T.

The digital trimming circuit 100 further includes a digital trimming period forming circuit 140 for generating a digital trimming period signal S.sub.F based on the signal of the frequency dividing circuit 130. A digital trimming timing decision circuit 160 produces a digital trimming timing signal (pulse) P.sub.T. This pulse corresponds to a correction data within a digital trimming time period. The digital trimming timing signal P.sub.T is generated from the following signals: the digital trimming period signal S.sub.F ; a timing reference signal S.sub.B having a shorter period than the period of the digital trimming period signal S.sub.F, and produced from the frequency dividing circuit 130; and correction data (CBA).sub.2 from the correction data supplying means 150. A digital trimming start control circuit 170 produces a digital trimming execution control signal S.sub.C in response to the digital trimming timing signal P.sub.T and the basic clock f.sub.0. The digital trimming execution control signal S.sub.C is used to set, or initialize, the 1/2-frequency divider 120 which has a data set function.

The digital trimming timing decision circuit 160 has an AND gate 161 which operates like an open/close circuit. In response to a gate open/close controlling signal, the AND gate 161 receives a propagation of a timing reference signal S.sub.B from the frequency dividing circuit 130. The output of the AND gate 161 is the digital trimming timing signal P.sub.T. A 3-bit down counter 163 is constructed of three 1/2-frequency dividers 163a, 163b, 163c with set/reset functions. Each 1/2-frequency divider can be reset by the digital trimming time period signal S.sub.F. The 3-bit down counter 163 performs the count down operation of the correction data (CBA).sub.2 in response to the digital trimming timing signal P.sub.T. A correction data setting circuit 164 is constructed of AND gates 164a, 164b and 164c. The inputs of the AND gates 164a, 164b and 164c are each connected to receive one bit from the correction data supplying means 150 and the output of a delay circuit 165 which is produced from the digital trimming time period signal S.sub.F. The AND gates 164a, 164b and 164c are connected to the set terminals of 1/2-frequency dividers 163a, 163b and 163c, respectively. The correction data setting circuit 164 transfers the correction data (CBA).sub.2 to the 3-bit down counter 163 when a level of a delay signal from the delay circuit 165 is changed from "H" to "L". An AND gate 166, which functions as a digital trimming cancel detecting circuit, "is connected to the invert outputs of the 1/2-frequency dividers 163a, 163b and 163c. This AND gate 166 produces a detecting output signal "D", which is in the "H" state when all of the inverted outputs "XQ" from the respective 1/2-frequency dividers of the down counter 163 are in an "H" state. An inverter 167 is added to invert the detection output signal D to the "L" state in order to obtain a gate opening/closing control signal "G". When the detection output signal D is in the "L" state, then the timing reference signal S.sub.B is sent through the AND gate 161 to form the digital trimming timing signal P.sub.T.

In the digital trimming timing decision circuit 160, the delay circuit 165 provides a time difference so as to set the correction data (CBA).sub.2 after the 3-bit down counter 163 has been set. In other words, when S.sub.f changes to the "L" state, the reset signal ceases to be applied to the 3-bit down counter 163. The delay circuit 165 continues to supply the "H" state to the data correction setting circuit 164 long enough to transfer the (CBA).sub.2 signal to set the 3-bit down counter 163.

The digital trimming start control circuit 170 has a latch 172 and a NOR gate 174. The latch 172 transfers the digital trimming timing signal P.sub.T, which is fluctuating, to the invert output XM when the clock input CL becomes "H". The invert output XM is maintained while the level of the clock input CL is in the "L" state. The NOR gate 174 receives the digital trimming timing signal P.sub.T and the invert output XM. The output of NOR gate 174 generates the digital trimming execution control signal Sc which sets the 1/2-frequency divider 120.

The correction data supplying means 150 may be comprised of means for converting the correction data supplied by an external operation member (not shown) and a signal input unit (not shown) which generates the data in the form of binary notation (CBA).sub.2. A switch group (not shown) forms the binary-notation (CBA).sub.2 logic, and a network of wire connection/disconnection directs the binary numbers to the appropriate outputs.

In FIG. 2, a timing chart illustrates the operation of the first preferred embodiment. The time period "T" of the digital trimming period signal S.sub.F is a relatively long time period which may last from several seconds to several hundreds of seconds. Both of the digital trimming period signal S.sub.F and the timing reference signal S.sub.B are obtained by frequency-dividing the 4 KHz output of the 1/2-frequency divider 134.

As an example, the digital trimming period signal S.sub.F is set to 125 Hz, and the timing reference signal S.sub.B is set to 2 KHz. Also, the correction data (CBA).sub.2 is selected, for example, to be (101).sub.2. When the signal level of the digital trimming period signal S.sub.F changes from the "H" state to the "L" state, all of the following signal levels are in the "L" state: the 32 KHz-signal, the 16 KHz-signal, the 8 KHz-signal, the 4 KHz-signal, and the timing reference signal S.sub.B. As soon as the digital trimming period signal S.sub.F changes to the "L" state, the reset signal ceases to be applied to the 3-bit down counter 163.

After the reset signal is removed, the delay circuit 165 continues to supply the "H" state to the data correction setting circuit 164 long enough to transfer the (101).sub.2 signal to set the 3-bit down counter 163. At this point, the following signals change: the invert output XQ of the 1/2-frequency divider 163a becomes an "L" level; the invert output XQ of the 1/2-frequency divider 163b becomes an "H" level; and the invert output xQ of the 1/2-frequency divider 163c becomes an "L" level under initial conditions. The digital trimming cancel circuit, i.e. the AND gate 166, changes state so that the detection output signal D is in the "L" state. The gate opening/closing control signal "G" is changed from an "L" state into an "H" state by the inverter 167, therefore the AND gate 161 functions as an open gate. As a consequence, the timing reference signal S.sub.B passes through the AND gate 161 to become the digital trimming timing signal P.sub.T. Then, this timing signal P.sub.T is supplied to the down counter 163 as a clock input and to the digital trimming start control circuit 170 as an input signal.

Every time the pulses of the digital trimming signal P.sub.T are entered into the 3-bit down counter 163, the count down operation of this down counter is performed. Therefore, the output of the 3-bit down counter (XQ.sub.163c,xQ.sub.163b,XQ.sub.163a).sub.2 are changed as follows: (101).sub.2, (100).sub.2, (011).sub.2, (010).sub.2, (001).sub.2, and (000).sub.2. When the fifth timing pulse is supplied to the down counter 163, the count value becomes (000).sub.2 and the invert output XM of the 3-bit down counter becomes (111).sub.2. Since all three of the invert output xQ of the 1/2-frequency divider 163a, 163b, and 163c, are in the "H" state, the signal level of the detection output "D" of the AND gate 166 functioning as the digital trimming cancel circuit is changed from an "L" level into an "H" level. This causes the signal level of the gate opening/closing control signal "G" to change from an "H" level into an "L" level due to the inverter 167. Therefore, the AND gate 161 is closed and the timing reference signal S.sub.B is blocked. The digital trimming timing signal P.sub.T remains in the "L" state.

When the timing reference signal S.sub.B was passing through the AND gate 161, five pulses of the digital trimming timing signal P.sub.T are output during a time duration from a gate opening point of the AND gate 161 to a gate closing point thereof.

The following scenario occurs in the digital trimming start control circuit 170. Before the signal level of the digital trimming timing signal P.sub.T changes from an "H" level into an "L" level, the 32 KHz basic oscillation clock f.sub.0 that functions as the clock input CL is also in the "H" state. The signal level of the invert output XM of the latch 172 changes to the "L" state. Then, the signal level of the basic oscillation clock f.sub.0 changes to the "L" state so that the invert output XM is maintained. During this time period t/2 (1/2 time period), the signal level (state) of the digital trimming timing signal P.sub.T is changed from the "H" level into the level. Therefore, the digital trimming execution control signal S.sub.c produced by the AND gate 174 has an "H" level during the t/2-time period. The digital trimming execution control signal S.sub.c is applied to the set input of the 1/2-frequency divider 120 with data set function (thus, the 1/2-frequency divider 120 functions as a digital trimming amount applying means). Since the 1/2-frequency divider 120 is set to "1" at a time instant when the signal level of this output Q (16 KHz signal) is changed from the "H" level into the "L" level, this output Q (16 KHz signal) is shortened only by one time period (about 30 microseconds) of the basic oscillation clock f.sub.0. Similarly, as the basic oscillation clock f.sub.0 is shortened by one time period (30 microseconds) in response to each of the second, third, fourth and fifth digital trimming execution control signals S.sub.c, the basic oscillation clock f.sub.0 is shortened by 5.times.30=150 microseconds. Therefore, the five digital trimming initiations are performed within one digital trimming time period. As a result, the time reference S.sub.T is obtained by frequency-dividing this basic oscillation clock f.sub.0 that is shortened by 150 microseconds within one digital trimming time period T. This amount of digital trimming time is not given within one digital trimming initiation, but a plurality of digital trimming initiations are discretely or distributely allocated within one digital trimming time period.

In this first preferred embodiment, five sets of the digital trimming initiations, in total, are carried out for a time interval of the timing reference signal S.sub.B within one digital trimming period in accordance with the correction data (101).sub.2. Therefore, the digital trimming amount for one digital trimming initiation may be selected to be 1/5 of the total digital trimming amount, i.e., 150 microseconds. Furthermore, it is possible to neglect such an adverse influence caused by one digital trimming correction, which will be given to a system such as a clock. For instance, in such a conventional system in which a motor driving pulse having a pulse width of 3.9 milliseconds is continuously output at a rate of 128 pulses per digital trimming second, when a 5-bit digital trimming operation is performed, the pulse width of the motor driving pulse, or the pulse interval thereof, is varied by 0.98 milliseconds maximum in a conventional system. This variation corresponds to 25% of the pulse width, or the pulse interval, and is not allowable, due to the requirements necessitated for a stable motor drive. If the timing reference signal S.sub.B is selected to be 30 microseconds, a resultant degree of this adverse influence becomes 0.78%. Therefore, the shortening/expanding amount of the pulse width, or the pulse interval, is negligible. As a consequence, the digital trimming timings in the system are not a concern, and therefore a degree of freedom in the setting operation is improved.

Although the digital trimming timing decision circuit 160 is constructed of 1/2-frequency dividers, this decision circuit may be an arrangement of shift registers. Also, as will be discussed later, the digital trimming timing decision circuit 160 may include a microcomputer (CPU) together with the digital trimming period forming circuit 140.

Furthermore, the digital trimming start control circuit 170 in the above-described first preferred embodiment is provided by the latch 172 and the NOR gate 174. However, this control circuit 170 is not limited thereto, but may be constructed of a delay means for slightly delaying the phase of the digital trimming timing signal P.sub.T with respect to the phase of the basic oscillation clock f.sub.0 having the frequency of 32 KHz. The control circuit 170 could also have an exclusive OR gate for producing the digital trimming execution control signal S.sub.c from the delayed digital trimming timing signal and the basic oscillation clock f.sub.0.

Furthermore, in this first preferred embodiment, the digital trimming operation with the minimum digital trimming amount (time period "t" of basic oscillation clock=30 microseconds) is performed by way of a one stage 1/2-frequency divider 120. Alternatively, the number of stages of the 1/2-frequency divider may be increased within a range where no adverse influence is given to the system, whereby one digital trimming amount may be increased. In addition, the digital trimming operation of this preferred embodiment is carried out along the direction of time reduction in order to correct time delays. Alternatively, when the variation of the digital trimming timing signal P.sub.T is synchronized with the falling edge ("H" level to "L" level) of the 16 KHz signal and also the 1/2-frequency divider 120 is reset by the digital trimming execution control signal S.sub.c, such a digital trimming operation may be carried out along the direction of time expansion, so that a time lead may be corrected. In this case, it is required that the frequency divider 132 is simultaneously reset in response to the digital trimming execution control signal S.sub.c in order that the negative effect of the variation ("H" level to "L" level) of the 16 KHz signal by resetting the 1/2-frequency divider 120 is not passed to the subsequent 1/2-frequency divider.

Although 32 KHz is used as the oscillation frequency of the basic oscillation clock in this first preferred embodiment, the present invention is not limited to this oscillation frequency. Any other oscillating circuits capable of oscillating frequencies higher than, or lower than, 32 KHz may be employed so as to oscillate the basic oscillation clock.

A second preferred embodiment of the present invention will be described with reference to FIG. 3. The digital trimming timing decision circuit 160 and digital trimming period forming circuit 140 of the first preferred embodiment are replaced by a microcomputer. In FIG. 3, a schematic block diagram shows a logic digital trimming circuit 200 employing a microcomputer. The same reference numerals shown in FIG. 1 will be employed for denoting the same circuit portions in the following drawings, and explanations thereof are omitted.

A microcomputer 280 is constructed of a core CPU 282, a ROM (read-only memory) 284 used to hold a program memory, and a RAM (random access memory) 286 that functions as a counter. A frequency dividing circuit 130 supplies a timing reference signal S.sub.B to the core CPU 282. Several signals are produced within microcomputer 280, including a digital trimming period signal S.sub.F, which has a time period N-times higher than the timing reference signal S.sub.B ("N" being an integer.) A correction data supplying means 150 supplies to the microcomputer 280 correction data in the form of serial or parallel data. The microcomputer 280 produces the digital trimming timing signal P.sub.T which is supplied to the digital trimming start control circuit 170.

FIG. 4 is a flow chart representing an operation of the microcomputer according to this second preferred embodiment. At step 500, the core CPU 282 reads the correction data supplied from the correction data supplying means 150. The core CPU 282 also stores a digital trimming initiation number "n " to be executed within one digital trimming time period into a digital trimming initiation number counter. The program advances to step 502 where a time measuring process is carried out. The time measuring process performs two processes. The first process produces the time reference signal S.sub.T by counting up the digital trimming time period. The second process counts up the timing reference signal S.sub.B.

At step 504, a decision is made to determine whether the digital trimming time period has been reached. If the digital trimming time period has not yet been reached, then the program advances to step 506 and a digital trimming end flag is set to OFF. After the flag is set, then the process operation is returned to step 502 to continue the time measuring process. If the digital trimming time period has been reached, then another check is made to verify if the digital trimming end flag is turned ON at step 508. If the digital trimming end flag is set to ON, then the process operation is returned to step 502 to continue the time measuring process. If the digital trimming end flag is in the OFF state, then a determination as to whether a digital trimming timing period has been reached is made in step 510.

If in step 510 a determination is made that the digital trimming timing period has not yet been reached, the process operation is returned to the step 502. If in step 510 the determination is made that the digital trimming timing period has been reached, then the program advances to step 512. If the digital trimming initiation number "n" is not equal to zero, then one digital trimming timing signal P.sub.T is output to the digital trimming start control circuit 170 at step 514. As a consequence, the digital trimming correction is carried out.

After the process operation defined at step 514 has been executed, a new digital trimming initiation number is set by subtracting 1 from the digital trimming time "n" in step 516. The process operation is returned to step 502. After "n" pieces of digital trimming timing signals P.sub.T are produced in accordance with such a process flow, the content of the digital trimming initiation counter becomes zero. Therefore, in step 512 the determination that n=0 is made and the process operation advances to step 518. The content of the digital trimming initiation number counter is set to "n" at step 518 in order to return the number of the digital trimming initiation operation, which should be executed within the next digital trimming period, to the initial value. At step 520, the digital trimming end flag is set to ON. Thereafter, the process operation is returned to step 502.

As described above, the timing controls of the software control in the microcomputer replace both the digital trimming timing decision circuit 160 and the digital trimming period forming circuit 140 in the first preferred embodiment.

A third preferred embodiment of the present invention is shown in FIG. 5. A digital trimming circuit 300 according to this preferred embodiment includes an oscillator circuit 110 oscillating at a frequency of 32 KHz as a basic oscillation frequency. A variable frequency divider 320, which functions as a digital trimming amount applying means, generates a time reference signal S.sub.T based on the basic oscillation clock f.sub.0. A digital trimming timing decision circuit 340 generates a digital trimming timing (pulse) signal P.sub.T. The correction data supplying means 150 supplies digital trimming amount data (CBA).sub.2 to the digital trimming timing decision circuit 340. The number of pulses in the digital trimming timing signal P.sub.T corresponds to digital trimming amount data (CBA).sub.2 within one digital trimming time period and the basic oscillation clock f.sub.0. A digital trimming start control circuit 360 designates a frequency division ratio of the frequency divider 320 based upon delay-speed designation data (V).sub.2 (also supplied by correction data supplying means 150) and a digital trimming timing signal P.sub.T.

The variable frequency divider 320 has a down counter 322 with a data set function and an inverter 324. The down counter 322 has the following connections: a clock input for the basic oscillation clock f.sub.0 ; 3-bit data set inputs A, B, C; 3-bit count outputs Q.sub.A, Q.sub.B, .sub.C ; a zero signal output CO for outputting a signal with an "H" level when a count value is zero; and a load input into which an invert signal CO of zero signal output CO is input via the inverter 324. From this zero signal output CO of the variable frequency divider 320, a time reference signal S.sub.T is derived. Normally, the variable frequency divider 320 functions as a 1/4-frequency divider, and operates in such a manner that any one of 1/3 frequency division and 1/5 frequency division is inserted during the 1/4 frequency dividing operation in response to the value of the delay-speed designation data at the digital trimming timings, as will be discussed later.

The digital trimming timing decision circuit 340 has a pulse generation allocating circuit 342 and a synchronous differentiate circuit 344. The pulse generation allocating circuit 342 allocates the digital trimming timing pulses CT at substantially equal intervals within one digital trimming time period. The number of timing pulses corresponds to the digital trimming amount data (CBA).sub.2. The synchronous differentiate circuit 344 generates one digital trimming timing signal P.sub.T upon detection of the rising edge of the digital trimming timing pulse.

The pulse generation allocating circuit 342 has a frequency divider 342a and a binary rate multiplier (BRM) 342b. The frequency divider 342a divides the 32 KHz basic oscillation clock f.sub.0 by 1/2.sup.15 to produce a 1 Hz-pulse allocation reference clock CL.phi..sub.1. The binary rate multiplier (BRM) 342b generates an output pulse CT, the number of which is set by the digital trimming amount data (CBA).sub.2, within one digital trimming time period "T" (namely, a period of 8 reference clocks CL.phi..sub.1 in this third preferred embodiment).

The synchronous differentiating circuit 344 has a first-stage D flip-flop 344a, a second-stage D flip-flop 344b and an AND gate 344c. The first-stage D flip-flop 344a uses as a clock input the invert signal CO of the zero output signal from the variable frequency divider 320. The digital trimming timing pulse CT is used as a data input D. The second-stage D flip-flop 344b uses a Q output of the first-stage D flip-flop 344a as a data input D, and the invert signal CO as a clock input. The AND gate 344c uses a Q output of the second-stage D flip-flop 344b and the Q output of the first-stage D flip-flop 344a to produce the digital trimming timing signal P.sub.T.

Referring now to timing charts shown in FIGS. 6 to 9, operations of the above-described third preferred embodiment will be explained. Referring to FIG. 6, the frequency divider 342a frequency-divides the basic oscillation clock f.sub.0 by 1/2.sup.15 to produce a pulse allocation reference clock CL.phi..sub.1. This reference clock is supplied to the binary rate multiplier (BRM) 342b. The time period during which 8 reference clocks CL.phi..sub.1 are generated of corresponds to one digital trimming time period T=8t. The rate multiplier (BRM) 342b outputs the digital trimming timing pulse CT, the number of pulses of which corresponds to the number of the digital trimming amount data CD=(CBA).sub.2 with respect to the 8 reference clocks.

There are seven different digital trimming timing pulse CT sequences produced. When the digital trimming amount data CD is equal to 1, so that (CBA).sub.2 =(001).sub.2, only the 5th reference clock CL.phi..sub.1 is derived. In the case when the digital trimming amount data CD is equal to 2, so that (CBA).sub.2 =(010).sub.2, only the 3rd and the 7th reference clocks CL.phi..sub.1 are derived. When the digital trimming amount data CD is equal to 3, so that (CBA).sub.2 =(011).sub.2, only the 3rd, the 5th, and the 7th reference clocks CL.phi..sub.1 are derived. When the digital trimming amount data CD is equal to 4, so that (CBA).sub.2 =(100).sub.2, the 2nd, the 4th, the 6th and the 8th reference clocks CL.phi..sub.1 are derived. When the digital trimming amount data CD is equal to 5, so that (CBA).sub.2 =(101).sub.2, the 2nd, the 4th, the 5th, the 6th and the 8th reference clocks CL.phi..sub.1 are derived. When the digital trimming amount data CD is equal to 6, so that (CBA).sub.2 =(110).sub.2, the 2nd, the 3rd, the 4th, the 6th, the 7th and the 8th reference clocks CL.phi..sub.1 are derived. When the digital trimming amount data CD is equal to 7, so that (CBA).sub.2 =(111).sub.2, the 2nd, the 3rd, the 4th, the 5th, the 6th, the 7th and the 8th reference clocks CL.phi..sub.1 are derived. The rate multiplier 342b produces a predetermined number of pulses within one digital trimming time period T, and has a function to divide the one digital trimming time period T, whereby pulses are allocated at substantially equal intervals.

To the clock inputs of the D flip-flops 344a and 344b of the synchronous differentiate circuit 344, the invert signal CO of the zero signal CO from the variable frequency divider 320 is applied. As will be discussed, normally, this invert signal CO corresponds to a 11/4-frequency division signal. When the output pulse CT of the rate multiplier 342b is produced, the D flip-flop 344a stores a value of the output pulse CT just before the invert signal CO falls to an "L" state. The D flip-flop 344a generates a waveform Q.sub.1 as shown in FIG. 7. Also, the D flip-flop 344b stores a value of the waveform Q.sub.1 just before the invert signal CO falls to the "L" state. The D flip-flop 344b generates a waveform Q.sub.2 from the Q output, as shown in FIG. 7. Since the falling edge of the waveform Q.sub.2 contains one clock delay of the invert signal CO with respect to the rising edge of the waveform Q.sub.1, the pulse width of the digital trimming timing signal "P.sub.T " output from the AND gate 344c corresponds to one clock of the invert signal CO. As described above, the pulse width of the pulse CT generated from the rate multiplier (BRM) 342b is compressed by the synchronous differentiate circuit 344, thereby generating the digital trimming timing signal P.sub.T.

As shown in FIG. 8, the delay speed data (V).sub.2 derived from the correction data supplying means 150 is equal to (O).sub.2 during such a time period. Furthermore, the level of the digital trimming timing signal P.sub.T is under the "L" state and the logic value (CBA).sub.2 =(011).sub.2 of the digital trimming start control circuit 360 is set to the down counter 322 as an initial value at the rising timing of the invert signal CO. As a consequence, every time the basic oscillation clock f.sub.0 is entered, the count value (Q.sub.C, Q.sub.B, Q.sub.A) is shifted from (011).sub.2, and then is again set to the initial value (011).sub.2 at the next clock when the zero signal CO is produced.

The variable frequency divider 320 performs the 1/4 frequency division during a time period when the delay speed data (V).sub.2 is equal to (O).sub.2 and the level of the digital trimming timing signal P.sub.T is under the "L" state. When the delay speed data (V).sub.2 remains (O).sub.2 and the level of the digital trimming timing signal P.sub.T becomes an "H" level, as indicated in FIG. 8, the logic value (CBA).sub.2 of the digital trimming start control circuit 360, which is (010).sub.2, is sent to the down counter 322 as an initial value at the rising time of the invert signal CO. As a result, every time the basic oscillation clock f.sub.0 is entered, the count value (Q.sub.C, Q.sub.B, Q.sub.A).sub.2 is shifted from (010).sub.2 via (001).sub.2 to (000).sub.2. It is then reset to the initial value of (010).sub.2 at a clock subsequent to the occurrence of the zero signal CO. Thus, when the delay speed data (V).sub.2 is (O).sub.2 and the level of the digital trimming signal P.sub.T is in the "H" state, the variable frequency divider 320 executes the 1/3-frequency dividing operation only once.

As described above, the time reference signal S.sub.T is shortened only by one time period of the basic oscillation clock in accordance with a single 1/3-frequency dividing operation in response to a single digital trimming timing signal P.sub.T. As a result, when "n" pieces of digital trimming timing (pulse) signals P.sub.T are produced within one digital trimming time period "T", the lead digital trimming operation is carried out only by "n" time periods of the basic oscillation clock f.sub.0 within one digital trimming time period "T". Therefore, the third preferred embodiment can achieve an advantage similar to that of the first preferred embodiment. Moreover, according to this third preferred embodiment, since the rate multiplier 342b is employed so as to produce the digital trimming timing signal P.sub.T at equal intervals allocated within one digital trimming time period, there is another merit that a plurality of digital trimming operations can be equally dispersed within one digital trimming time period. This is contrary to the first preferred embodiment where a plurality of digital trimming operations are concentrated at the beginning of the digital trimming time period. Accordingly, a degree of adverse influence given to the safety condition of the pulse motor may be mitigated.

Now referring to FIG. 9, the delay speed data (V).sub.2 derived from the correction data supplying means 150 is (1).sub.2. Furthermore, the level of the digital trimming timing signal P.sub.T is in the "L" state. During this time period, the logic value (CBA).sub.2 =(011).sub.2 of the digital trimming start control circuit 360 is sent as an initial value to the down counter 322 at the rising edge of the invert signal CO. As a result, every time the basic oscillation clock f.sub.0 is entered, the count value (Q.sub.C, Q.sub.B, Q.sub.A) is shifted from (011).sub.2 via (010).sub.2 via (001).sub.2 to (000).sub.2. The count value is then set to the initial value (011).sub.2 in response to the occurrence of the zero signal CO in the subsequent clock pulse. Accordingly, during this time period that the delay speed data (V).sub.2 becomes (O).sub.2 and the level of the digital trimming timing signal P.sub.T is under the "L" state, the variable frequency divider 320 performs the 1/4 frequency division irrelevant to the condition of the delay speed data (V).sub.2.

When the delay speed data (V).sub.2 is equal to (1).sub.2 and the level of the digital trimming timing signal P.sub.T changes to the "H" level, the logic value (CBA).sub.2 =(100).sub.2 of the digital trimming start control circuit 360 is sent to the down counter 322 as the initial value at the rising edge of the invert signal CO. As a consequence, every time the basic oscillation clock f.sub.0 is input, the count value (Q.sub.C, Q.sub.B, Q.sub.A) is shifted from (100).sub.2 via (011).sub.2, (010).sub.2, (001).sub.2 to (000).sub.2. Then, this count value is again set to the initial value (100).sub.2 in response to the next clock pulse when the zero signal CO is generated. Accordingly, when the delay speed data (V).sub.2 becomes (1).sub.2, and the level of the digital trimming timing signal P.sub.T is in the "H" state, the variable frequency divider 322 performs the 1/5-frequency dividing operation only once. Thus, the time reference signal S.sub.T is expanded only by one time period of the basic oscillation clock f.sub.0 in accordance with a single 1/5-frequency dividing operation by a single digital trimming timing signal P.sub.T. As a result, when "n" pieces of digital trimming timing signals P.sub.T are produced within one digital trimming time period, a delay digital trimming operation is carried out by "n" time periods of the basic oscillation clock f.sub.0 within one digital trimming time period "T".

In accordance with this third preferred embodiment, since the digital trimming timing signal P.sub.T has been allocated within one digital trimming time period at substantially equal intervals, a plurality of digital trimming operations can be equally dispersed within one digital trimming time period. Again, this is in contrast to the first embodiment where a plurality of digital trimming operations are concentrated at the initial stage of the digital trimming time period.

Since a duty ratio of the zero signal CO from the variable frequency divider 320 is not equal to 50%, there are some cases that this zero signal is not properly used as the clock of the time reference signal S.sub.T. In such a case, the duty ratio of this zero signal CO is processed by a wave shaping circuit, or the like, to be 50%. This shaped zero signal may be used as a reference signal of the time reference signal S.sub.T.

In this third preferred embodiment, it is so arranged that the digital trimming timing signal P.sub.T is produced, the number of which corresponds to the value of the digital trimming amount data "CO". Alternatively, since a detection can be done regardless of whether the digital trimming operation is under execution by monitoring the digital trimming timing signal P.sub.T, a process operation such as an operation interruption for other circuit blocks may be performed.

FIG. 10 is a schematic block diagram showing a circuit arrangement of a digital trimming apparatus according to a fourth preferred embodiment of the present invention. A digital trimming circuit 400 has an oscillator circuit 110 oscillated at a basic oscillation frequency f.sub.0 of 32 KHz. A correction data supplying means 150 supplies a correction data (digital trimming period designation data) "m" to a digital trimming period decision circuit 440 which produces a digital trimming period pulse ZDm based on the basic oscillation frequency f.sub.0. A digital trimming timing decision circuit 460 (also called digital trimming converting device) receives the digital trimming period pulse ZDm, the basic oscillation frequency f.sub.0, and a correction data (digital trimming interval designation data) "n", which is supplied by the correction data supplying means 150, to produce a digital trimming timing signal ZDnm (also called start control pulse signal). A digital trimming amount applying circuit 420 receives the basic oscillation frequency f.sub.0 and the digital trimming timing signal ZDnm to generate the time reference signal S.sub.T.

The digital trimming amount applying circuit 420 has a complementary output circuit 422 and a clock selecting circuit 424. The complementary output circuit 422 produces an in-phase clock .phi.1 and the reverse phase clock .phi.1 based on the basic oscillation clock f.sub.0. The clock selecting circuit 424 generates a .phi..sub.out by selecting the in-phase clock .phi.1 and the reverse phase clock .phi.1 in response to the digital trimming timing signal ZDnm. The selected clock .phi..sub.out is the time reference signal S.sub.T.

The digital trimming period decision circuit 440 has a 1/m-frequency dividing circuit 442 and a zero detector 444. The 1/m-frequency dividing circuit 442 functions as a down counter with a preset function. The initial value "m" from the correction data supplying means 150 is set in response to the digital trimming period pulse ZDm. The zero detecting circuit 444 detects when the count value of the down counter becomes zero.

The digital trimming timing decision circuit 460 has a 1/n-frequency dividing circuit 462, a zero detecting circuit 464, and an OR gate 466. The 1/n-frequency dividing circuit 462 functions as a down counter with a preset function. The initial value "n" from the correction data supplying means 150 is set in response to the digital trimming timing signal ZDnm. The zero detecting circuit 464 detects when the count value of this down counter becomes zero. The OR gate 466 produces the digital trimming timing signal ZDnm based upon the zero detection signal ZDn of the zero detecting circuit 464 and the digital trimming period pulse ZDm of the zero detecting circuit 444.

The initial value "m" is supplied from the correction data supplying means 150 to the 1/m-frequency dividing circuit 442 which executes the count down operation upon receipt of the basic oscillation clock f.sub.0. When the count value becomes zero, the zero detection signal ZDm is generated from the zero detecting circuit 444, so that the initial value "m" is again set to this 1/m-frequency dividing circuit 442. As shown in FIG. 11, the zero detection signal ZDm is produced every time "m" pieces of basic oscillation clocks f.sub.0 are generated, which will then form a digital trimming period pulse. On the other hand, the initial value "n" is also supplied from the correction data supplying means 150 to the 1/n-frequency dividing circuit 462 which will then execute the count down operation upon receipt of the basic oscillation clock f.sub.0. When the count value of this down counter becomes zero, the zero detection signal ZDn is generated from the zero detecting circuit 464, so that the following will occur: the initial value "n" is reloaded on this 1/n-frequency dividing circuit 462, in response to the zero detection signal ZDn; and the initial value "m" is reloaded thereon in response to the digital trimming period pulse ZDm of the zero detecting circuit 444. To produce the digital trimming timing signals ZDnm at substantially equal intervals within one digital trimming time period T, the correction data "m" and "n" satisfy the following relationship:

where the symbol "r" indicates a minimum positive integer smaller than "n," and the symbol "p" denotes the quantity of the digital trimming timing signals ZDnm generated within one digital trimming time period T.

Assuming now that the correction data "m" is equal to 2.sup.15 =32768, as indicated in FIG. 11, the digital trimming period pulse is output from the zero detecting circuit 444 when the 32768th basic oscillation clock is produced. In this case, the digital trimming operation is executed at the starting point of the digital trimming time period T. In the case when n equals 16384, since the zero detection signal ZDn is also produced when the 16384th basic oscillation clock f.sub.0 is generated, p=2 and r=0. As a consequence, the digital trimming operations are executed at the starting point of the digital trimming time period T and at the T/2 time instant. When n equals 10923, the zero detection signal ZDn is produced when the 10923rd and 21846th basic oscillation clocks f.sub.0 are produced. The digital trimming period pulse ZDm is produced before the 32769th basic oscillation clock f.sub.0 is generated. The interval between the 21846th basic oscillation clock and the starting point of the digital trimming time period is shorter than the other pulse interval by only one basic oscillation clock. Since this shorter interval corresponds to a difference in 1% time interval, it can be asserted that the digital trimming timing signals ZDnm are allocated at substantially equal intervals. Accordingly, in this fourth preferred embodiment, a plurality of digital trimming operations can be uniformly dispersed within one digital trimming time period. Unlike the first preferred embodiment, the plural digital trimming operations are not concentrated at the beginning of the digital trimming time period. Furthermore, no digital trimming timing signals are obtained by curtailing the input pulses, which occurred in the third preferred embodiment.

The rounding effects of the digital trimming period pulse ZDm occur even under such cases when n equals 6554, 5462 and 4682 as shown in FIG. 11. The rounding effects may be negligible by setting the value of "m" to a large value.

Referring to FIG. 12, the following is an explanation of an operation of the digital trimming amount applying circuit 420. In the clock selecting circuit 424, every time the digital trimming timing signal ZDnm is produced, the output signal .phi..sub.out is changed. For example, when the in-phase clock .phi.1 has been selected as the output signal .phi..sub.out and the digital trimming timing signal ZDnm is input into the clock selecting circuit 424, the clock selecting circuit 424 selects the reverse phase clock .phi.1 as the output signal .phi..sub.out. Also when the reverse clock .phi.1 is input, the clock selecting circuit 424 selects the in-phase clock .phi.1 as the output signal .phi..sub.out. Since the clock changing timing of the clock selecting circuit 424 corresponds to the "L" period of the output signal .phi..sub.out, the output signal .phi..sub.out during this changing operation is expanded by a half period (Tc/2) of the basic oscillation clock f.sub.0, as represented in FIG. 12.

In the previous preferred embodiments, the variable frequency divider was employed as the digital trimming amount supplying means and the method for changing the frequency dividing ratio based on the digital trimming timing was used. In accordance with this fourth preferred embodiment, such a method for expanding/reducing the output signal by a half of the clock time period in response to the changing operation between the in-phase clock .phi.1 and the reverse clock 100 1 has been utilized. As a result, since the minimum digital trimming amount does not correspond to one time period of the basic oscillation clock, but a half period thereof, the expansion/reduction ratio of the time reference signal effected by the digital trimming operation may be further suppressed.

As previously described in detail, the dispersive digital trimming method is employed in which a plurality of digital trimming operations with the short digital trimming amounts are dispersively executed within one digital trimming time period. A digital trimming amount supplying means executes the digital trimming operation with a predetermined digital trimming amount in response to the initiation control signal. Therefore, the time reference signal, which is based on the basic oscillation frequency, is produced.

Also, the digital trimming amount-to-pulse number converting means produces the initiation control pulse signal within one digital trimming time period, the number of pulses corresponds to the correction data for designating the digital trimming amount which should be executed within one digital trimming time period. Since the initiation control pulse signals are obtained within one digital trimming time period, a plurality of digital trimming operations are dispersively performed within one digital trimming time period. The digital trimming amount of the digital trimming amount applying means is coincident with such a value calculated by dividing, for instance, the digital trimming amount to be operated within one digital trimming time period by the pulse number. Then, the digital trimming amount required within one digital trimming time period is applied. Therefore, the digital trimming amount can be coincident with the logic digital trimming rate required for the time reference signal.

The expansion/reduction amount for the time reference signal at the digital trimming timing can be suppressed. In other words, since the digital trimming operation with the minimum expansion/reduction amount corresponding to the time period of the basic oscillation signal can be realized, interference caused by the digital trimming timing and a predetermined output timing may be negligible, or greatly suppressed.

The digital trimming timing equal-allocating means generates the initiation control signal. This means allocates pulses at substantially equivalent time intervals. The time intervals are calculated by dividing one digital trimming time period by the above-described pulse number. Therefore, a plurality of digital trimming timings are not concentrated into a portion of one digital trimming time period, but are dispersed therethrough. As a result, a reduction in the negative affect of the output timings is achieved.

When the complementary signal forming means generates the in-phase signal and the reverse phase signal in response to the basic oscillation signal, and also the signal selecting means for selecting the in-phase signal and the reverse phase signal to be output are employed as the digital trimming amount applying means, the digital trimming operation with the minimum digital trimming amount equal to a half time period of the original oscillation signal can be performed. The above-described benefits are achieved.

Although the invention has been described and illustrated with particularity, it is intended to be illustrative of preferred embodiments and understood that the present disclosure has been made by way of example only. Numerous changes in the combination and arrangements of the parts and features can be made by those skilled in the art without departing from the spirit and scope of the invention, as hereinafter claimed.