Circuit Device and Corresponding Method for Resetting Non-Volatile and Electrically Programmable Memory Devices

This invention relates to a circuit device and associated method for generating a reset signal in storage devices.

As is known, many of the storage devices currently available commercially provide for the memory internal logic control circuitry to be reset.

The reset signal is normally generated within the integrated storage circuit, and the activation of this signal is responsive to a decrease in the circuit supply voltage Vcc.

This manner of operation is of special importance to devices being supplied a programming voltage Vpp from outside which usually has a relatively high value, in excess of 10 volts. The most dangerous situation likely to be encountered by such devices is, in fact, a decrease in the supply voltage Vcc while the value of the programming voltage Vpp is held at a high. Under this condition, lacking an ability to control the logic circuitry operation, erasure or incorrect programming of the storage elements may occur.

To avoid such problems, currently available devices on the market are arranged to include threshold detection devices which are supplied the programming voltage Vpp and effective to detect a drop in the supply voltage Vcc below a predetermined minimum value. Such circuits activate the device resetting by disabling all the circuits connected to the relatively high programming voltage Vpp.

The operation of the detection circuits is only ensured, however, in the presence of a programming voltage Vpp which has a positive value above a predetermined minimum value.

An example of a detection circuit based on the above-outlined operation principles is to be found in U.S. Pat. No. 4,975,885, to "INTEL." The circuit described therein has an output which would signal a drop in the supply voltage Vcc below a threshold value of 3.7 volts, but only for higher values of the programming voltage than 4.5 volts.

However, the reset mode provided by the prior art circuits affords no control at the device power-on stage, i.e., as the supply voltage Vcc is brought from 0 up to a steady-state value.

This deficiency is quite serious because on turning on, and in the absence of the programming voltage Vpp, no reset signal would be generated. In this way, the initial state of the internal control logic remains undetermined.

To obviate this drawback, some devices provide for the storage reset signal to be driven from outside. For instance, the integrated storage circuit currently available commercially has a PWD (Deep Power Down) pin intended to minimize the circuit's power consumption. However, that PWD pin may also receive a reset signal activated by the user.

This is not an adequate solution, because it depends on, among other things, the device user's proper recollection, skill and technical circuit knowledge.

An object of this invention is to provide a uniquely simple circuit solution which allows the storage device to be reset automatically even during the power-on transient, thereby overcoming all the drawbacks with which the prior art approaches are beset. A preferred aspect of the present invention provides for obtaining a logical sum between a logic signal responsive to a decrease in the supply voltage Vcc, being only effective in the presence of a programming voltage Vpp above a predetermined value, and a signal generated by a provided circuit which follows the power-on transient.

The features and advantages of a circuit and a method according to the invention will be apparent from the following detailed description.

FIG. 1 illustrates a non-volatile storage device incorporating a reset signal generating circuit according to the invention.

FIGS. 2 and 3 illustrate a voltage vs. time pattern of a set of electric signals present in the device shown in FIG. 1.

FIG. 1 illustrates a non-volatile storage circuit that is integrated to a semiconductor and electrically programmable. The circuit 1 is in particular, but not limited thereto, a storage device of the "flash" EEPROM type. This circuit 1 comprises a memory matrix 2 and a logic control circuit portion 3, as well as electric connections of the bus type, between the matrix 2 and the control logic 3.

The circuit 1 is supplied by a supply voltage Vcc of about 5 V and by a programming voltage Vpp of about 12 V. These voltages are supplied to the storage circuit through respective input terminals or pins.

The circuit 1 further comprises a threshold detection circuit 5 connected between the supply voltage Vcc, the programming voltage Vpp, and a signal ground GND.

The circuit 5 has an output 6 at which a logic signal LowVcc having a "high" logic value will appear upon detection of a decrease in the supply voltage Vcc below a predetermined minimum value Vccmin.

The circuit 5 would only be operative in the presence of a programming voltage Vpp higher than a predetermined minimum value Vppmin. Under this condition (Vpp>Vppmin), the signal LowVcc would be brought to a "high" logic value upon the supply voltage Vcc dropping below the minimum threshold Vccmin.

The signal LowVcc, in relation to the threshold value Vccmin, is illustrated by the graph of FIG. 2.

Also provided is a circuit 7 generating a reset logic signal POR (Power On Reset). The circuit 7 is supplied the supply voltage Vcc, and is also operative in the absence of the programming voltage Vpp. It plays its most important role as the device 1 is turned on.

The signal POR is passed to an output 8 of the circuit 7, and during the power-on or power-off transient it essentially tracks the value of the supply voltage Vcc while the voltage Vcc occurs between two predetermined values Va and Vb, the latter limit lying below the minimum threshold Vccmin. The signal POR, in relation to the predetermined values Va and Vb, is illustrated by the graph of FIG. 3. In a preferred embodiment of the present invention, the circuit I comprises a logic gate 10 having two inputs 9, 11 and an output 12. In the preferred embodiment illustrated, the logic gate 10 is of the OR type. The inputs 9 and 11 of said logic gate 10 are respectively connected to the output 6 of the circuit 5 and the output 8 of the circuit 7. As a result, the first input 9 of the gate 10 will be applied the logic LowVcc, whilst the second input 11 will be applied the logic signal POR. The output 12 of the logic gate 10 supplies a reset signal which is determined by the logical sum of the input signals and applied to the control logic 3.

The method of this invention for generating the reset signal will now be described.

As already brought out by the foregoing description, a preferred method of this invention provides for application of the reset signal to the control logic 3 as a function of the change-over between the output signal from the threshold detector 5 and the signal POR generated by the circuit 7 during the power-on transient of the device 1. In particular, the change-over function is a logical sum (OR).

The reset signal at the output of the logic gate 10 behaves like the signal LowVcc in the presence of programming voltage Vpp (of course, only if Vccmin is greater than Vb), and is logic "high" if the pattern of the signal POR is within Va and Vb in the absence of programming voltage Vpp.

Thus, when the circuit I is turned on, and absent the programming voltage Vpp, the whole logic circuitry 3 of the circuit 1 is held to a reset state for as long as the value of the supply voltage Vcc is held between Va and Vb. Thus, the whole circuitry will exhibit a logic state as defined before the operation is started, thereby overcoming the prior art problems previously pointed out.

The values of the threshold voltages Va and Vb used in the circuit are selected to meet the requirements for proper operation of the storage circuit. For example, the OR gate 10 is designed so that, for the selected voltage between Va and Vb, it outputs a reset signal to provide the reset function. (Alternatively, one may say that Va is selected in conjunction with the OR gate 10 to output a reset signal if the input at 11 is above Va.)

For instance, the threshold value Vb is selected to be lower than Vccmin but in all cases equal to a voltage whereby the entire logic of the device is expected to perform satisfactorily.

In a storage circuit provided with a PWD (Deep Power Down) terminal, this terminal would just serve the single function of lowering the device consumption. It would not be used for resetting the logic circuit 3. Thus, by virtue of the invention, a user having no need of lowering the device low consumption may connect the PWD terminal directly to ground. This connection makes for more convenient management of the device.

The detailed description provided above will enable those skilled in the art to make various modifications to the preferred embodiment that do not depart from the spirit and the scope of the present invention. As such, the present invention encompasses all such modifications that read on the appended claims and equivalents thereof.