Cache Control Method and Rotary Storage Device Having Cache Control

The present invention relates to a disk cache control method and a rotary storage device, and in particular, to a disk cache control technology effectively applicable to a magnetic disk subsystem or the like to be connected as an external storage device to an information processing apparatus.

For example, in the field of information processing technology in which distributed computer processing utilizes a disk storage media for a storage device, there has been required a disk subsystem which is compatible with a high-speed random data processing. In this case, to prevent elongation of the mean processing time associated with a mechanical seek time and a latency in the random read and write operations requested from a higher-level apparatus, such as a central processing unit (CPU), to a disk, there has been employed in a data transfer path to the disk unit a cache memory in the form of a semiconductor memory, and having a higher operation speed as compared with the disk storage, thereby increasing the processing speed. However, since the semiconductor memory has a bit cost which is significantly higher than that of the disk medium, the feasible capacity of the cache memory is limited in the present state of the art.

FIG. 23 shows the general configuration of an example of a disk device to be operated in association with a cache memory. When the disk device receives a command or instruction for the writing of data via an upper-level interface circuit 102 from a host computer 101, a CPU 107 writes the data via a cache controller 103 in a cache memory 104 at an address specified by the instruction. When the disk device receives a read instruction from the host computer 101, the CPU 107 references a cache control table in the cache controller 103. If the data exists in the cache memory 104, namely, in a case of a "cache hit" the CPU 107 activates the cache controller 103 to transmit the data from the cache memory 104 to the host computer 101.

If the data requested by the read instruction is missing in the cache memory 104, namely, in the case of a "cache miss" the CPU 107 activates a disk controller 105 to access the disk devices 1061 to 106N (N may be "one" depending on cases) to read data from the pertinent address so as to store the obtained data via the cache controller 103 in the cache memory 104 and to concurrently transfer the read data via the upper-level interface circuit 102 to the host computer 101.

There may also be considered a method in which operations of the upper-level interface circuit 102, the cache controller 103, and the disk controller 105 are autonomously conducted without using instructions from the CPU 107 and without necessitating the monitoring operation of the CPU 107.

In the write operation, even when a cache hit occurs for each access request (hit rate=100%) in the cache memory 104, it is necessary to finally write each data item in the destination storage position in the disk devices 1061 to 106N in a random fashion.

Further, in the case where a miss hit occurs due to insufficient capacity of the cache memory 104 or in a case where write cache data is written on a disk, random processing in the disk devices 1061 to 106N also must be performed.

On the other hand, in JP-A-60-258661 entitled "Cache Memory Controller", there have been described a scheme for utilization of a cache memory to minimize the number of accesses to disks and an efficient method of controlling the cache memory. However, the control operation for reading data in the event of a miss hit of the cache, the control operation to be effected when power is interrupted, and the control operation for writing cache data on a disk in response to a processing request from a higher-level apparatus are substantially identical to those employed in the example of FIG. 23 in that the access operations are actually conducted according to random addresses on the disks.

In the prior art referenced above, when the capacity of the cache memory is increased to improve the hit rate, the cost of the apparatus inevitably increases substantially. Moreover, in a case where a disk write operation is required due to a miss hit in the cache memory during a data write operation, there occurs a random access to the disk. Namely, the seek time and the latency remain as relevant factors, which leads to a problem of a longer processing time.

For example, in the case where the cache capacity is 16 megabytes (MB) and the data processing unit includes 16 kilobytes (KB), when it is desired to save data in a termination processing of the system, there occur 1000 input/output (I/O) operations. Each I/O operation takes a period of time represented as follows. ##EQU1## Assuming that the values of the above items are applied to a 5-inch disk device with a rotary speed of 5400 rotations per minute (RPM), as generally used, the I/O processing time Tpc of each I/O operation is as follows. ##EQU2##

In the disk device with a rotary speed of 5400 rpm, one disk rotation takes 11.1 ms. Half the rotation period is consumed by the latency. In a case where each sector includes 512 bytes and each track has 80 sectors by way of example, the period of time required to access 16 kilobytes (=32 sectors) is expressed as 32/80 x (one disk rotation time).

In consequence, the processing time necessary for 1000 I/O operations is 23.8 seconds in this apparatus.

It is therefore an object of the present invention to provide a method of and an apparatus for controlling a disk cache, which are capable of improving at a low cost the hit rate and minimizing the processing time at the time of a miss hit.

Another object of the present invention is to provide a method of and an apparatus for controlling a disk cache which are capable of effectively improving the hit rate according to various modes of access of the rotary storage media.

Still another object of the present invention is to provide a method of and an apparatus for controlling a disk cache, which are capable of minimizing the period of time necessary to save data from a cache memory onto a rotary storage medium.

Still a further another object of the present invention is to provide a rotary storage device, which is capable of improving at a low cost the hit rate and minimizing the processing time at the time of a miss hit.

Another object of the present invention is to provide a cache control method, which is capable of effectively improving the hit rate according to various modes of access of a rotary storage media.

Still another object of the present invention is to provide a rotary storage device, which is capable of minimizing the period of time necessary to save data from a cache memory onto a rotary storage medium.

The foregoing and other objects and novel features of the present invention will be understood from the following detailed description when read in connection with the accompanying drawings.

According to an aspect of the present invention, there is provided a cache control method in which, in a transfer path for data communicated between a rotary storage medium and an upper-level apparatus, there is disposed a cache memory to hold therein a copy of the data in the rotary storage medium such that for at least either one of a data read request from the upper-level apparatus to read data from the rotary storage medium and a data write request from the upper-level apparatus to write data in the rotary storage medium, a response operation thereto is performed by use of the cache memory and a cache controller. The method includes the steps of subdividing the rotary storage medium into an ordinary user area and a secondary cache area and executing at least either one of a write processing to save in the rotary storage medium data which has overflowed from the cache memory and a read processing, when data requested by the data read request is missing in the cache memory, to read the data from the rotary storage medium, the write or read processing being executed preferentially for the secondary cache area as compared to the ordinary user's area.

According to another aspect of the present invention, there is provided a rotary storage device including a rotary storage medium and a cache memory disposed in a transfer path of data communicated between the rotary storage medium and an upper-level apparatus, the cache memory holding therein a copy of the data in the rotary storage medium, such that for at least either one of a data read request from the upper-level apparatus to read data from the rotary storage medium and a data write request from the upper-level apparatus to write data in the rotary storage medium, a response thereto is achieved by use of the cache memory. The rotary storage device includes subdividing means for subdividing the rotary storage medium into an ordinary user area and a secondary cache area in a program-controlled manner and preferential execution means for executing at least either one of a write processing to save in the rotary storage medium data which has overflowed from the cache memory and a read processing, when data requested by the data read request is missing in the cache memory, to read the data from the rotary storage medium, the write or read processing being executed preferentially for the secondary cache area.

In the cache control method and the rotary storage device according to the present invention, even when an overflow of data occurs in a cache memory and the data is required to be written in a rotary storage medium, the data write operation is conducted not with actual random addresses in the ordinary user area on the rotary storage medium, but with successive addresses of a "secondary cache area" which is disposed, for example, in a range of several cylinders from the outer-most peripheral cylinder of the rotary storage medium, and which is not accessible from the user. As a result, the access to the rotary storage medium can be accomplished as a sequential operation and hence the total time including the seek time and the latency is minimized, thereby reducing the processing time.

The operation to write data on the rotary storage medium according to the actual addresses is achieved during a period of time when the traffic of the I/O operations from upper-level apparatuses is relatively decreased.

Moreover, in the case where data missing in the cache memory and existing in the "secondary cache area" is requested from an upper-level apparatus, the data is transferred from the secondary cache area to the cache memory. In this situation, since the data access is carried out to a limited range of the rotary storage medium, the transfer operation is accomplished at a high speed. Namely, the operation can be achieved in a shorter period of time as compared with the operation to access the actual user area.

For example, in the case of a banking online system, data accesses for transactions of online terminals are conducted to the cache memory and the "secondary cache area". After the online operation is finished, the data written in these cache memories are moved therefrom into the actual user areas on the rotary storage media.

These and other objects and advantages of the present invention will become apparent by reference to the following description and accompanying drawings wherein:

FIG. 1 is a schematic block diagram showing an example of a rotary storage device in an embodiment according to the present invention;

FIG. 2 is a schematic block diagram showing an example of a rotary storage device in another embodiment according to the present invention;

FIG. 3 is a diagram showing an example of a cache control table for use in controlling a cache memory;

FIG. 4 is a diagram showing an example of a secondary cache control table for use in controlling a secondary cache data area;

FIG. 5 is a schematic diagram showing an example of transition of data transfer processing between the cache memory, the secondary cache data area, and the user data area;

FIG. 6 is a schematic diagram showing another example of transition of data transfer processing between the cache memory, the secondary cache data area, and the user data area;

FIG. 7 is a schematic diagram showing still another example of transition of data transfer processing between the cache memory, the secondary cache data area, and the user data area;

FIG. 8 is a schematic diagram showing a further example of transition of data transfer processing between the cache memory, the secondary cache data area, and the user data area;

FIG. 9 is a schematic diagram showing another example of transition of data transfer processing between the cache memory, the secondary cache data area, and the user data area;

FIG. 10 is a schematic diagram showing still another example of transition of data transfer processing between the cache memory, the secondary cache data area, and the user data area;

FIG. 11 is a schematic diagram showing a further example of transition of data transfer processing between the cache memory, the secondary cache data area, and the user data area;

FIG. 12 is a schematic diagram showing an example of the update state of the cache control table and the secondary cache control table in the data transfer processing between the cache memory, the secondary cache data area, and the user data area;

FIG. 13 is a schematic diagram showing another example of the update state of the cache control table and the secondary cache control table in the data transfer processing between the cache memory, the secondary cache data area, and the user data area;

FIG. 14 is a schematic diagram showing still another example of the update state of the cache control table and the secondary cache control table in the data transfer processing between the cache memory, the secondary cache data area, and the user data area;

FIG. 15 is a schematic diagram showing a further example of the update state of the cache control table and the secondary cache control table in the data transfer processing between the cache memory, the secondary cache data area, and the user data area;

FIG. 16 is a schematic diagram showing another example of the update state of the cache control table and the secondary cache control table in the data transfer processing between the cache memory, the secondary cache data area, and the user data area;

FIG. 17 is a schematic block diagram showing an example of a rotary storage medium in the rotary storage device in an embodiment according to the present invention;

FIG. 18 is a schematic block diagram showing another example of a rotary storage medium in the rotary storage device in an embodiment according to the present invention;

FIG. 19 is a schematic block diagram showing a further example of a rotary storage medium in the rotary storage device in an embodiment according to the present invention;

FIG. 20 is a schematic block diagram showing still another example of a rotary storage medium in the rotary storage device in an embodiment according to the present invention;

FIG. 21 is a flowchart showing an example of a data read processing in a rotary storage device in an embodiment according to the present invention;

FIG. 22 is a flowchart showing an example of a data write processing in a rotary storage device in an embodiment according to the present invention; and

FIG. 23 is a block diagram showing an example of the general construction of a prior art disk device operating in association with a cache memory.

Referring now to the accompanying drawings, description will be given in detail of embodiments according to the present invention.

FIG. 1 shows in a block diagram an example of the structure of a rotary storage device using the cache control method according to the present invention.

The rotary storage device includes a plurality of disk devices 6x (x=1 to N) each having a rotary storage medium 70, such as a magnetic disk (of which examples are shown later in FIGS. 17 to 20), and each operating under control of a disk controller 5. A higher-level interface circuit 2 for controlling communication of commands and data between a host computer 1 and the rotary storage device, a cache controller 3 and a cache memory 4 are disposed in a data transfer path between the interface circuit 2 and the disk devices 6x or the disk controller 5, and a CPU 7 provides control, including control logic achieving control operations for controlling the overall operations, which will be described later. Furthermore, the cache controller 3 includes a direct memory access (DMA) controller 33 for controlling communication of actual data to and from the cache memory 4, which may be provided as a semiconductor memory or the like, and to and from the disk controller 5.

In this case, in each of the plural disk devices 6x, a storage area of the rotary storage medium 70 disposed therein is subdivided into an ordinary user area 6xb and a secondary cache data area 6xa. This data area 6xa is clearly discriminated from the user data area 6xb available for the user's read and write operations.

As for the following operations, the secondary cache data area 6xa takes precedence over the user data area 6xb according to a sequence of procedures. Namely, for example, in an operation to save cache data 4a which has overflowed from the cache memory 4 into a secondary cache data area 6xa3 and in an operation to read objective data from the secondary cache data storage area 6xa in the event of a miss hit of the cache memory 4, the pertinent data in the secondary cache data storage area 6xa takes precedence over user data 6xb1 stored in the user data area 6xb.

In the cache controller 3, there are provided a cache control table 32a to control the cache data stored in the cache memory (FIG. 3) and a secondary cache control table 32b to control the secondary cache data area 6xa3 kept in the secondary cache data storage area 6xa (FIG. 4). As for these tables 32a and 32b, when data is stored in an area of the secondary cache data storage area 6xa2, cache control table (data) 6xa1 and secondary cache control table (data) 6xa2 are simultaneously updated.

There can be considered various methods of determining the capacity of the storage area 6xa. The capacity is not necessarily required to be substantially the same as that of the cache memory. Namely, depending on the system configuration, the capacity may be set to an integral multiple of that of the cache memory 4. Conversely, the capacity of the cache memory 4 may be set to an integral multiple of that of the secondary cache data storage area 6xa. Alternatively, the capacity of the storage area 6xa may be set to a value independent of that of the cache memory 4.

FIG. 17 schematically shows an example of the configuration of the rotary storage medium 70 which may be used in this embodiment. On a recording surface of the medium 70 having a contour like a magnetic disk, there are arranged a plurality of concentric tracks as areas to store data and the like. In a case where there is disposed a plurality of recording surfaces rotating about an identical axis, a group of tracks each having the same radius are collectively controlled as a cylinder 70a. In the group of tracks belonging to the same cylinder 70a, access from one track to another can be accomplished without any seek operation (i.e. a radial displacement and a positioning) of the read/write head, not shown. Namely, the access can be conducted simply through an electrical operation. Consequently, in ordinary cases, a data write operation is executed preferentially in those tracks belonging to an identical cylinder 70a.

For example, as shown in the example of FIG. 17, one may allocate several continuous outer cylinders 70a and the remaining inner cylinders 70a to the secondary cache data storage area 6xa and the user data area 6xb, respectively.

Furthermore, as can be seen from the example of FIG. 18, it may also be possible to allocate several cylinders 70a in the central portion of the group of concentric cylinders 70a to the secondary cache data storage area 6xa and the other inner and outer cylinders to the user data area 6xb. In the case of FIG. 18, the seek distance of the head from a position in the secondary cache data storage area 6xa to a position in the user data area 6xb is relatively decreased.

In addition, as shown in the example of FIG. 19, the group of cylinders 70a arranged in a concentric fashion may be subdivided into a plurality of zones Z1 and Z2 so as to dispose a user data area 6xb and a secondary cache data storage area 6xa associated therewith in each zone.

Furthermore, as shown in the example of FIG. 20, in a case of a so-called constant density recording (CDR) scheme in which the bit recording density per unitary length is substantially fixed regardless of the radii of the tracks, namely, the longer the distance from the center to the pertinent track (cylinder) is, the more the data amount writable in the track (cylinder) is (in other words, the number of sectors 70b to store the unitary data amount is increased), a group of several consecutive outer cylinders 70a and a group of the inner cylinders are allocated to the secondary cache data storage area 6xa and the user data area 6xb, respectively. For the same capacity of the secondary cache data storage area 6xa, this configuration minimizes the number of cylinders 70a necessary to reserve the storage area 6xa, thereby further reducing the period of time required to access the area 6xa.

Description will next be given of an example of operation of the rotary storage device of the embodiment constituted as indicated in FIG. 1.

The CPU 7 references the cache control table (memory) 32a and the secondary cache control table (secondary cache) 32b for data of a logical block address (LBA) contained in an upper-level command request received in association with a read/write request from the host computer 1. Namely, the CPU 7 determines whether the data exists in the cache memory 4, whether the data is missing in the secondary cache data area 6xa3, or whether the data exists in neither. However, almost the entire confirmation job or a portion thereof may be accomplished by the cache controller 3.

When it is confirmed that the data exists in the cache memory 4, a write or rewrite operation of the data is carried out in the cache memory 4 or the secondary cache data storage area 6xa by the DMA controller 33.

As shown in the flowchart of FIG. 21, in a data read operation, when the data is missing in the cache memory 4 and exists in the secondary cache data area 6xa3 of the disk device 6x, the pertinent disk address of the area 6xa is accessed by the disk controller 5.

In a case where a relatively high hit rate is assumed in the area 6xa3 depending on the processing mode of the host computer 1 operating as the upper-level apparatus, the range of the seek operation is limited to the consecutive cylinders in the area 6xa3. Consequently, in ordinary cases, the period of time required for the read operation is considerably decreased as compared with the conventional read operation in which the write operation is conducted in a random fashion at actual addresses in the user data area 6xb.

When a hit occurs neither in the cache memory 4 nor in the secondary cache data area 6xa3, the pertinent disk address of the user data area 6xb is accessed by the disk controller 5. In this case, the seek operation is achieved according to a random address.

On the other hand, as can be seen from the flowchart of FIG. 22, in a data write operation, when the data is missing in the cache memory 4, the data is written in a free area in the cache memory 4. The command processing is terminated at this point of time.

When no free area is available in the cache memory 4, arbitrary data (i.e., most suitable data judged to be removed from the cache memory 4 according to an algorithm such as a least recently used (LRU) algorithm) is saved from the cache memory 4 into the secondary cache data area 6xa3 of the disk device 6x via the DMA controller 33 and the disk controller 5.

In this operation, the seek operation range is limited to the cylinders of the area 6xa3. In consequence, the period of time required for the write operation is remarkably reduced as compared with the conventional read operation in which the write operation is conducted in a random manner at actual addresses in the user data area 6xb.

In this operation, when no free area is available in the secondary cache data area 6xa3, the arbitrary secondary cache data 6xa4, for example, LRU data is saved from the secondary cache data storage area 6xa into the user area 6xb of the disk device 6x according to the pertinent address by the DMA controller 33 and the disk controller 5.

When it is necessary to save the contents of the cache memory 4 into the disk device 6x due to a power interruption or in association with processing of an upper-level apparatus, the cache table 4a, the cache control table 32a, and the secondary cache control table 32b are temporarily saved from the cache memory 4 into the secondary cache storage area 6xa through a sequential access operation by the DMA controller 33 and the disk controller 5. Since the range of this operation is limited to a group of successive cylinders 70a constituting the area 6xa, the period of time required for the saving operation is considerably minimized as compared with the conventional technology in which the access operation is conducted in a random fashion to the actual user data area 6xb.

The cache data once saved into the area 6xa is restored to the user data area 6xb according to the respective actual addresses at a point of time when a period of time specified by the system has elapsed without any reception of an access request.

To improve the cache hit rate, the following operations may be conducted.

1) At the power-on phase, the secondary cache data may be loaded in the cache memory 4 so that processing will be continuously executed at the time of a power interruption or when the power is turned on again, thereby improving the cache hit rate.

2) When the power is turned on again, if data to be frequently accessed thereafter is known, the data or auxiliary data associated therewith may be loaded in the cache memory 4, the secondary cache data storage area 6xa, or both thereof.

As a result, the cache hit rate is improved.

FIG. 3 shows an example of the cache memory 4 and the cache control table 32a in this embodiment, whereas FIG. 4 shows an example of the cache data area 6xa3 and the secondary cache control table 32b.

Rows (0 to R-1) and columns (0 to C-1) define at intersections therebetween frames or locations. The locations thus defined respectively in the cache memory 4, the secondary cache data area 6xa3, the cache control table 32a, and the secondary cache control table 32b correspond to each other.

In FIG. 3, in a location of the table 32a corresponding to the memory 4, there is stored a cache control flag 32a-1 (F1) of the pertinent cache data 4a. The flag 32a-1 includes an LBA (logical address of data) and two control flags, namely, a control flag C2 (=1 when the data 4a matches the data 6xa4), and a control flag CD (=1 when the data 4a matches the data 6xb1).

In FIG. 4, in a location of the secondary cache control table 32b corresponding to the secondary cache data area 6xa3, there is stored a secondary cache control flag 32b-1 (F2) of the pertinent secondary cache data 6xa4.

The flag 32b-1 includes an LBA (logical address of data) and two control flags, i.e., a control flag D2 (=1 when the data 6xb1 in the disk device 6x matches the data 6xa4) a control flag O2 (=1 when the data 6xa4 is overflowed the cache memory 4).

FIGS. 5 to 11 show an example of the general processing together with data stored in the cache memory 4 and the secondary cache data storage area 6xa and transitions of the cache control table 32a and the secondary cache control table 32b respectively related thereto.

In a state where initial data (aaa0) to initial data (hhh0) are beforehand written respectively in user area locations at addresses #a to #h, processing is executed as follows. Processing 1 FIG. 5: in a case where there is issued from a host computer, operating as an upper-level apparatus, an instruction to write data (aaa1), data (bbb1), and data (ccc1) respectively in locations at addresses #a, #b, and #c, a command termination report is set to the upper-level apparatus when the data is completely written in the cache memory 4.

In this operation, an LBA (logical address) and the control flags C2 and CD are set to the cache control table 32a corresponding to the data of the cache memory

At this point of time, the contents of the cache memory 4 are less old than the user data 6xb1 in the disk device 6x and hence the control flag CD is set to 0; whereas, the registration of the data has not been conducted to the secondary cache data storage area 6xa and hence the control flag C2 is set to 0. Processing 2 FIG. 6: When an instruction to read data from locations at addresses #a, #d, and #e is issued after the processing 1, since the latest data at #a exists in the cache memory 4, the data (aaa1) is sent from the cache memory 4 to the host computer 1. Since data items at #d and #e are missing in both of the cache memory 4 and the secondary cache data storage area 6xa, the data items are read from the user data area 6xb into the cache memory 4 and are thereafter transmitted to the host computer 1. As a result, the data in the cache memory 4 matches the user data 6xb1 and the control flag CD is consequently set to 1. Processing 3 FIG. 7: In a case where the contents of the cache memory 4 are saved in the secondary cache data storage area 6xa after the processing 2, since the contents of the memory 4 match those of the area 6xa, the control flag C2 is set to 2. For data associated with the control flag CD=1, since the control flag C2 is 1, the control flag D2 is set to 1. Processing 4 FIG. 8: After the processing 3, in a case where there is issued an instruction to write data (aaa2), data (fff1), and data (ggg1) in locations respectively at addresses #a, #f, and #g, the command termination is reported to the upper-level apparatus when the data is completely written in the cache memory 4.

The cache data 4a at #a is updated to the data (aaa2) and hence becomes different from the secondary cache data 6xa4; consequently, the control flag C2 is set to 0.

Since the data items (fff1) and (ggg1) respectively at the address #f and #g are new data items, the control flags CD and C2 are set to 0 and 2, respectively. Although the data at address #b (bbb1) overflows from the cache memory 4, since the data at the address #g is written in the cache memory 4, the data 5 bbb1) is kept in the secondary cache data storage area 6xa. Consequently, the control flag O2 is set to 1. Processing 5 FIG. 9: When an instruction to read data items from locations at addresses #a, #b, and #h is issued after the processing 4, since the latest data at #a exists in the cache memory 4, the data (aaa2) is sent from the memory 4 to the host computer 1.

The data at #b is missing in the cache memory 4, but exists in the secondary cache data storage area 6xa. Consequently, the data is transmitted therefrom via the cache memory 4 to the host computer 1. As a result, the data in the cache memory 4 matches that in the area 6xa, and hence the control flag C2 is set to 1. Since the overflowed data is resultantly restored in the cache memory 4, the control flag O2 is set to 0.

The data at #h is neither in the memory 4 nor in the area 6xa and hence is sent from the user data area 6xb via the cache memory 4 to the host computer 1. As a result, the data in the memory 4 matches the user data 6xb1 in the area 6xb, and hence the control flag CD is set to 1. Although the data at #c (ccc1) overflows from the memory 4 because the data at #b is written therein, the data at #c is kept in the area 6xa. Consequently, the control flag O2 is set to 1. Processing 6 FIG. 10: When the contents of the secondary cache data storage area 6xa are written in the user data area 6xb after the processing 5, since the data in the area 6xa matches that in the area 6xb, the control flag D is set to 1. For the data associated with the control flag C2=1, the control flag CD is set to 1 because the control flag D2 is 1. Processing 7 FIG. 11: When the contents of the cache memory 4 are in the user data area 6xb after the processing 5, the processing 6 is first executed and then the data is saved from the memory 4 into the secondary cache data storage area 6xa. In this state, the data written in the memory 4 up to this point of time has already been saved from the user data area 6xb into the area 6xa (at least the control flag CD=1 or C2=1 for each data). Consequently, the power may be turned off.

At an arbitrary point of time thereafter, there is selected from the secondary cache data 6xa4 in the area 6xa any data (of which the control flag CD=0 and the control flag D2=0) to update the user data area 6xb, which is then written in the area 6xb.

In operation, in a case where any data item in the cache memory 4 has been already saved, the control flags are established as C2=1, CD=1, D2=1, and O2=0.

In a case where the processing is re-started due to a power interruption during the system operation, the control flags are set as C2=0, CD=0, D2=1, and O2=1. In this state, when the contents of the secondary cache data storage area 6xa are loaded (through an up-load operation) into the cache memory 4, the control flags are set as C2=1, CD=1, D2=1, and O2=0.

FIGS. 12 to 16 show states of the cache control table 32a and the secondary cache control table 32b updated through the processing described above.

FIG. 12 shows the processing 1 of a write command when the cache memory 4 has empty areas.

FIG. 13 shows the processing 4 in a case where a data overflow occurs in the cache memory 4 due to a write command.

FIG. 14 shows the processing 5 of a read command.

FIG. 15 shows the processing 6 in a case where the contents of the secondary cache data storage area 6xa are saved into the user data area 6xb.

FIG. 16 shows the processing 7 in a case where the contents of the cache memory 4 are saved into the user data area 6xb.

These diagrams respectively show in the table format the states of cache control flags during the execution of processing, the effectiveness (latest state) of the data of the secondary cache data storage area 6xa and the user data area 6xb, the data update path through the processing, and the states of cache control flags after the processing.

As indicated above, according to the cache control method and the rotary storage device of this embodiment, the capacity of the cache memory 4, constituted by a recording media, such as a semiconductor memory of a high bit cost, is substantially expanded by the secondary cache data storage area 6xa disposed in a portion of the rotary storage medium 70 of a low bit cost, thereby increasing the cache hit rate at a low cost.

Moreover, since the read operation of the rotary storage medium 70 at the time of a miss hit of the cache memory 4 is executed for the secondary cache data storage area 6xa arranged in a group of particular consecutive cylinders, the seek time can be minimized.

That is, according to the prior art operation for accessing the disk device 6x to save data from the cache memory 4 into the disk device 6x, there is achieved a random write operation through substantially all of the areas of the rotary storage medium 70. In contrast thereto, according to the present invention, there is conducted a sequential write operation for the secondary cache data storage area 6xa configured with several particular successive cylinders, which consequently reduces the processing time and minimizes the battery backup time in the event of a power interruption.

In consequence, it is possible to simplify, for example, the facility of the backup power for the cache memory 4, which contributes to reduction of the production cost of the apparatus.

Furthermore, to access the secondary cache data storage area 6xa, there can be employed an access procedure which is quite suitable for the application program executed by the host computer, thereby increasing the hit rate in the access to the area 6xa.

For example, the hit rate can be improved as follows.

1) The cache control method of the invention is applied to an application having a higher possibility of accessing again data which has overflowed from the cache memory 4.

2) Data assumed to have a high access frequency is beforehand stored in the secondary cache data storage area 6xa.

In addition, depending on the application programs, when it is desired to obtain a high access speed even by sacrificing the data capacity thereof, there may be disposed a plurality of secondary cache data storage areas 6xa. Also, in this case, since the bit cost of the rotary storage medium 70, such as a magnetic disk, is lower than that of the cache memory 4, in the form of a semiconductor memory or the like, the expansion can be easily conducted without increasing the cost. Moreover, this does not lead to an increase in the installation space.

FIG. 2 shows an example of the construction of a rotary storage device in another embodiment according to the present invention. The embodiment differs from the first embodiment in that, for N disk devices 6x (x=1 to N) under control of the disk controller 5, the secondary cache data storage area 61a is provided in only one disk device 6x selected therefrom.

In FIG. 2, the internal configurations respectively of the storage area 61a and the cache controller 3 are the same as those of the first embodiment shown in FIG. 1.

Although not specifically shown, the N disk devices under control of the disk controller 5 may be subdivided into several groups such that in each group, the storage area 61a is provided in one of the disks belonging to the group.

Also in the second embodiment, there can be obtained an advantage similar to that of the first embodiment.

In the cache control method and the rotary storage device according to the present invention, the operation to save 16 megabyte of data from the cache memory into the secondary cache area is achieved through an I/O processing for the secondary cache area. The processing time T.sub.PI necessary for this I/O operation is represented as follows. ##EQU3##

For the expression above, using values of the respective items for a 5 inch disk device of the type generally used at present, the processing time T.sub.PI is obtained as follows. ##EQU4##

That is, as compared with T.sub.PC =23.8 ms .times.1000 of the conventional example, the I/O processing time is remarkably reduced to about one fifth according to the present invention.

Moreover, assume that the capacity of the cache memory is increased, for example, from 16 MB to 32 MB to improve the hit rate of the cache memory. In consideration of the present state of the art in which the ratio between the megabyte cost of the 16 MB DRAM and that of the ordinary magnetic disk medium is about 60 to one, the ratio with respect to any increase in the cost to improve the bit rate according to the present invention is about 1/60 when compared with the prior art.

Furthermore, the user area of the rotary storage medium which is sacrificed for this purpose is represented as follows.

32768 sectors 1/80 sectors/track 1/20 tracks/cylinder=about 20 cylinders. Namely, since the total number of cylinders of the disk is about 3000 cylinders, only about 0.67% is sacrificed.

According to an investigation of the present inventors, in the case where the disk subsystem including the rotary storage devices has the total capacity of ten gigabytes (GB), a simulation test has been conducted for the cache hit rate in an example of a bench mark including a relational data base (RDB). For a cache capacity of 16 MB (0.16% of the total capacity) and a cache capacity of 32 MB (0.32% of the total capacity), the cache hit rates are resultantly obtained as about 10% and about 20%, respectively. For the actual job, it is quite effective to improve the hit rate bs providing the secondary cache area in a portion of the rotary storage medium.

In the case of an application using the cache control method and the rotary storage device according to the present invention, in such processing as an online terminal processing of a bank or a clinical processing to write a clinical chart of a patient in a hospital, even when data overflows in the ordinary daytime operation from the cache memory due to random read and modify write operations of a large amount of small-sized data items associated with the overall data of the user area in the rotary storage media, I/O operations can be achieved through sequential write operations thanks to the secondary cache area disposed in the particular consecutive areas of the rotary storage media, thereby minimizing the seek time, the latency, and the response time. The data accumulated in the secondary cache area during the daytime operation is written in the user area in which the data is inherently to be stored, thereby avoiding any inconvenience in the job.

While the present invention devised by the inventors has been described with reference to particular illustrative embodiments, it is not to be restricted by those embodiments but only by the appended claims. It is to be appreciated that those skilled in the art can change or modify the embodiments without departing from the scope and spirit of the present invention.