Self-Refresh Method and Refresh Control Circuit of a Semiconductor Memory Device

The present invention relates to semiconductor memory devices, and more particularly to a self-refresh method and refresh control circuit for a semiconductor memory device function.

The refresh operation of memory cells should be continuously performed even in a stand-by mode so as to retain data stored in the memory cell, i.e., that of a Dynamic Random Access Memory (DRAM) device. A self-refresh mode is widely used for DRAMs. The self-refresh mode is of the type adapted to perform the refresh operation of the memory cell with the lapse of a predetermined time after going into an operation stand-by mode, even though a separate control signal is not applied from an external source to the memory device. Once the self-refresh mode starts, it is preferable to perform the refresh operation of all memory cells in order to keep data. Thus, the memory devices employing the self-refresh mode have their own refresh regulation time (i.e. the minimum time required in performing the self-refresh mode). Generally, the time required in refreshing data of all memory cells in the self-refresh mode approximates the time required in accessing data in all memory cells in a normal access mode. Preferably, the more the refresh regulation time approximates the time required in the normal access mode, that is, the shorter the refresh regulation time is, the more advantageous the memory device is, since more time can be assigned to the access operation.

In the widely used self-refresh mode, with the lapse of the predetermined time after going into a CBR (CAS before RAS) mode, sequential row addresses are internally generated until the CBR mode is completed and then word lines are activated, thereby refreshing data of the memory cells. FIG. 1 is a timing diagram showing an operation of such a self-refresh mode. Referring to FIG. 1, the memory device having N word lines and M bit lines performs the normal access mode according to row and column address signals X=0 Y=0, X=0 Y=1, X=0 Y=2, . . . X=N Y=M supplied externally. With the lapse of the predetermined time in the CBR mode, the normal access mode is converted to the self-refresh mode, thereby internally generating the sequential row addresses X=0, X=1, . . . X=N, so that the refresh operation of the memory cells is performed in the unit addressed by the word line. The memory cell requiring the longest time in completing the refresh operation in FIG. 1 will now be discussed. Assuming that time T1 is required in accessing data of all memory cells, the normal access mode is performed for nearly time T1 except that the memory cell designated by the last address defined as X=N Y=M, and thereafter the operation stand-by mode starts. Thereby, the self-refresh mode starts and then the refresh operation is performed for time T2 until internal row addresses of X=0, X=1, . . . X=N are generated. This indicates that the memory cell designated by the last address defined as X=N Y=M is refreshed with the lapse of time T1+T2. Accordingly, the refresh regulation time of the memory device having the timing diagram shown in FIG. 1 should be defined as time T1+T2 at least.

However, the memory device having the timing diagram shown in FIG. 1 has such a problem that the refresh regulation time becomes longer by time T1 than time T2 required in refreshing all memory cells. Since time T1 is generally set to be nearly equal to time T2, the refresh regulation time becomes twice as much as the necessary time.

In order to overcome the above problem, another conventional self-refresh method is shown in FIG. 2, which is capable of reducing the refresh regulation time by performing a burst refresh mode for a short time before and after the self-refresh mode. Referring to FIG. 2, after the normal access mode is performed for time T1, the burst refresh mode is performed in which the row address RAS is toggled at short intervals before going into the self-refresh mode, and thereby the word lines are sequentially activated for time T3 much shorter than time T1, so that all memory cells are refreshed. Thereafter, the normal self-refresh operation is performed for time T2. As CAS and RAS are disabled, the burst refresh mode is performed again after the self-refresh mode is completed, and then the normal access mode is performed. The refresh regulation time of the memory device having the refresh method shown in FIG. 2 is set to be the longer of T1+T3 or T2+T3. Since time T3 required in performing the burst refresh mode is set short enough to be ignored as compared to time T1 or T2, the refresh regulation time of this memory device can be defined as time T2 required in refreshing all memory cells. Thus, such a memory device has an advantage that the refresh regulation time can be shortened by half as compared to that of the memory device shown in FIG. 1.

However, in the method shown in FIG. 2, since RAS applied to the memory device should be toggled at short intervals in order to perform the burst refresh mode, the controller for driving the memory device must be able to perform the burst refresh mode.

It is therefore an object of the present invention to provide a self-refresh method and refresh control circuit of a semiconductor memory device, which can minimize a refresh regulation time.

It is another object of the present invention to provide the semiconductor memory device which has a function to internally perform a burst refresh mode before and/or after a self-refresh mode.

To accomplish the above objects, the present invention provides the self-refresh method and refresh control circuit, wherein the burst refresh mode is performed prior to the self-refresh mode. In the burst refresh mode, whether control signals applied from an external reach a predetermined condition or not is detected, and when a self-refresh starting signal is enabled, pulse rows of a short period are internally generated and then all word lines are sequentially activated, thereby performing the refresh of the memory cells.

In addition, the present invention provides the self-refresh method and refresh control circuit, wherein after the self-refresh mode is performed in response to the self-refresh starting signal, the burst refresh mode is performed when the self-refresh starting signal is disabled, and then a normal access mode is performed.

Furthermore, the present invention provides the self-refresh method and refresh control circuit, wherein when the self-refresh starting signal is enabled, the burst refresh mode is performed prior to the self-refresh mode, and when the enabled self-refresh starting signal is disabled, the burst refresh mode is performed again and then converted to the normal access mode. Accordingly, the memory device in which the burst refresh mode is performed by the refresh control circuit installed therein, can be embodied.

The above objects and other advantages of the present invention will become more apparent by describing the preferred embodiment of the present invention with reference to the attached drawings, in which:

FIG. 1 is a timing diagram illustrating a conventional self-refresh mode,

FIG. 2 is a timing diagram illustrating a conventional burst refresh mode,

FIG. 3 is a diagram of one preferred embodiment according to the present invention, showing a refresh control circuit designed to perform the burst refresh mode before and after the self refresh mode,

FIG. 4 is a detailed circuit diagram illustrating the self-refresh mode controller shown in FIG. 3,

FIG. 5 is a timing diagram illustrating an operation of the self-refresh mode controller shown in FIG. 4,

FIG. 6 is a timing diagram illustrating an operation of the refresh control circuit shown in FIG. 3,

FIG. 7 is a diagram of another preferred embodiment according to the present invention, showing the refresh control circuit designed to perform the burst refresh mode at the completion of the self-refresh mode, and

FIG. 8 is a timing diagram illustrating an operation of the refresh control circuit shown in FIG. 7.

FIG. 3 is a diagram illustrating one preferred embodiment according to the present invention, showing a refresh control circuit designed to perform a burst refresh mode before and after a self-refresh mode. The figure comprises a self-refresh mode detector 10 for receiving control signals RAS and CAS applied from an external source to a memory device and outputting a self-refresh starting signal .phi.SRAS with the lapse of a predetermined time after going into a CBR mode; a burst refresh mode controller 12 for detecting a trigger point of the self-refresh starting signal .phi.SRAS, i.e., the rising edge and falling edge of .phi.SRAS and outputting a burst refresh control signal .phi.BRE which is enabled to a logic high level; a counter CNT0 14 for outputting a continuous pulse row CK0 having a period of t1 in response to the enabled burst refresh control signal .phi.BRE; a counter CNTi 16 for counting the pulse row CK0 outputted from the counter CNT0 14, and isolating the operation of the burst refresh mode controller 12 when a predetermined number of pulses are generated, thereby disabling the burst refresh control signal .phi.BRE; a self-refresh mode controller 18 for detecting the point of time when the enabled burst refresh control signal .phi.BRE is disabled at the enable state of the self-refresh approach signal .phi.SRAS, to output a self-refresh control signal .phi.sref; a counter CNTs 20 for outputting a continuous pulse row CK1 having the period of t2 in response to the enabled self-refresh control signal .phi.sref; and a refresh master clock output circuit 22 for outputting one enabled pulse row of CK0 or CK1 to a master clock .phi.selfp for selecting the word line.

FIG. 4 is a detailed circuit diagram illustrating the self-refresh mode controller 18 shown in FIG. 3. In FIG. 4, the starting signal .phi.SRAS output from the self-refresh mode detector 10 is applied to an input terminal D of a D flip-flop 24, as well as to one input terminal of an XOR gate 28 via a signal delay circuit 26. The XOR gate 28 outputs the product obtained by exclusively ORing the delayed starting signal .phi.SRAS and the burst refresh control signal .phi.BRE to a clock terminal CK of the D flip-flop 24. The flip-flop 24 performs an input operation if a signal with a logic low level is applied to the clock terminal CK, thereby receiving the starting signal .phi.SRAS applied to the input terminal D thereof. Also the flip-flop 24 performs an output operation if a signal with a logic high level is applied to the clock terminal CK, thereby outputting the self-refresh control signal .phi.sref at a positive output terminal Q thereof.

FIG. 5 is a timing diagram illustrating the operation of the self-refresh mode controller 18 shown in FIG. 4. The points of time t0, t1, t2, t3 shown in FIG. 5 are the same as those in FIG. 6.

The operation of FIG. 4 will now be described in conjunction with FIG. 5. The starting signal .phi.SRAS delayed by .DELTA.T2 by the delay operation of the signal delay circuit 26 is applied to an output node A of the signal delay circuit 26. In order to prevent a logic malfunction, the delay time .DELTA.T2 must be shorter than the delay time .DELTA.T1 between .phi.SRAS and .phi.BRE. The output node B of the XOR gate 28 is changed to the logic high level at time ta delayed by .DELTA.T2 from time t0 when the starting signal .phi.SRAS is applied with the logic high level, so that the D flip-flop 24 performs the output operation. At this time, since the logic low level is latched in the D flip-flop 24, the self-refresh control signal .phi.sref output from the positive output terminal Q is maintained at the logic low level. If the burst refresh control signal .phi.BRE is enabled to the logic high level at time t1 delayed by .DELTA.T1 from time t0, the output node B is changed to the logic low level, and the D flip-flop 24 is thereby converted to the input mode, to receive and latch the starting signal .phi.SRAS therein. At time t2, as the enabled burst refresh control signal .phi.BRE is disabled to the logic low level, the node B is again changed to the logic high level, and the D flip-flop 24 is thereby converted to the output mode, to output the latched logic high level signal at the positive output terminal Q thereof. At time tb delayed by .DELTA.T2 from time t3 when the self-refresh starting signal .phi.SRAS is changed to the logic low level, the node B is changed to the logic low level, and the D flip-flop 24 is thereby converted to the input mode, to receive and latch the starting signal .phi.SRAS of the logic low level therein. Thereafter, at time tc delayed by .DELTA.T1 after the self-refresh starting signal .phi.SRAS is changed to the logic low level, as the disabled burst refresh control signal .phi.BRE of the logic low level is enabled to the logic high level, the node B is changed again to the logic high level, the D flip-flop 24 is thereby converted to the output mode, to output the latched logic low level signal at the output terminal Q thereof. At time td when the burst refresh control signal .phi.BRE is disabled to the logic low level, the node B is changed to the logic low level, the D flip-flop 24 is thereby converted to the input mode, to receive and latch the starting signal .phi.SRAS of the logic low level therein. In accordance with the above described process, the D flip-flop 24 outputs the self-refresh control signal .phi.sref shown in FIG. 5.

FIG. 6 is a timing diagram illustrating the operation of the refresh control circuit shown in FIG. 3. The operation of FIG. 3 will now be discussed with reference to FIG. 6. In accordance with the essential technical spirit of the present invention, once going into the self-refresh mode, the refresh control circuit shown in FIG. 3 sequentially performs the burst refresh mode, the self-refresh mode, and then the burst refresh mode. During the interval T1 between time t1 and time t2, the burst refresh mode is performed prior to the self-refresh mode, during the interval T2 between time t2 and time t3, the self-refresh mode is performed, and during the interval T3 between time t4 and time t5, the burst refresh mode is performed immediately after completing the self-refresh mode.

Referring to FIG. 6, with the lapse of the predetermined time after going into the CBR mode, the self-refresh mode detector 10 outputs the self-refresh starting signal .phi.SRAS which is enabled to the logic high level at time t0. As the self-refresh starting signal .phi.SRAS is changed to the logic high level, the burst refresh mode controller 12 is activated, to output the burst refresh control signal .phi.BRE of the logic high level. As the burst refresh control signal .phi.BRE is enabled to the logic high level, the counter CNT0 14 outputs the first pulse row CK0 having a first period at time t1. The first pulse row CK0 is output as the master clock .phi.selfp for sequentially driving the word lines via the master clock output circuit 22, thereby performing the burst refresh mode. It is well known to those skilled in the art that if the master clock .phi.selfp is output, the memory device performs the restoring operation with sequentially enabling the word lines, to refresh the memory cells. At this time, the period of the master clock .phi.selfp that controls the burst refresh mode is set to be relatively short as compared to that in the normal self-refresh mode. The counter CNTi 16 counts the pulse row CK0 output from the counter CNT0 14. Then, if the predetermined number (i.e. the number of all word lines) of pulses are generated, the counter CNTi 16 outputs the output signal CK2 of a narrow pulse width to the control terminal of the burst refresh mode controller 12. Thereby, the burst refresh control signal .phi.BRE which has been applied with the logic high level from the burst refresh mode controller 12, is changed to the logic low level at time t2. This results in isolating the operation of the counter CNT0 14, to isolate the generation of the pulse row CK0, thereby completing the burst refresh mode to be performed before the self-refresh mode.

At time t2, as the burst refresh control signal .phi.BRE is disabled to the logic low level, as shown in FIGS. 4 and 5, the self-refresh control signal .phi.sref output from the self-refresh mode controller 18 is enabled to the logic high level and the counter CNTs 20 thereby outputs the second pulse row CK1 of the second period. The second pulse row CK1 is thus output as the master clock .phi.selfp for sequentially driving the word lines via the refresh master clock output circuit 22, to perform the self-refresh mode. In this case, the master clock .phi.selfp controlling the self-refresh mode has a similar period to that in the normal access mode. The self-refresh mode is continuously performed while the starting signal .phi.SRAS is maintained at the logic high level. Thereby, all word lines are activated, and then sequentially activated again from the first word line.

As RAS and CAS are disabled to the logic high level in the self-refresh mode, the self-refresh starting signal .phi.SRAS is disabled to the logic low level at time t3. Thus, the burst refresh mode controller 12 detects the falling edge of the self-refresh starting signal .phi.SRAS, thereby enabling the burst refresh control signal .phi.BRE to the logic high level. As described above, the counter CNT0 14 outputs the first pulse row CK0 having the first period and the first pulse row CK0 is output as the master clock .phi.selfp via the refresh master clock output circuit 22, thereby performing the burst refresh mode. The process from the beginning of the burst refresh mode to the completion thereof is the same as described above. It is preferable to allow the memory cells corresponding to the word line selected last in the self-refresh mode to be sufficiently refreshed by delaying the burst refresh mode by the second period after performing the self-refresh mode and before beginning the burst refresh mode. In addition, it is possible to shorten the time required in performing the burst refresh mode by making the period of the master clock in the burst refresh mode relatively short as compared to that in the self-refresh mode.

According to one preferred embodiment shown in FIG. 3, once going into the self-refresh mode, the refresh control circuit installed within the memory device performs the burst refresh mode prior to the self-refresh mode, thereafter, performs the burst refresh mode again and then performs normal access mode. Thereby, the aforementioned problems can be solved.

FIG. 7 is a diagram of another preferred embodiment according to the present invention, showing the refresh control circuit designed to perform the burst refresh mode at the completion of the self refresh mode. FIG. 8 is a timing diagram illustrating the operation of the refresh control circuit shown in FIG. 7. FIG. 7 comprises a self-refresh mode detector 30 for receiving the control signals RAS and CAS applied from an external source to the memory device and outputting the self-refresh starting signal .phi.SRAS with the lapse of the predetermined time after going into the CBR mode; a self-refresh mode controller 32 for detecting whether the self-refresh starting signal .phi.SRAS is enabled or not, to output the self-refresh control signal .phi.sref; a counter CNTs 34 for outputting the continuous pulse row CK1 having the period of time t2 in response to the enabled self-refresh control signal .phi.serf; a burst refresh mode controller 36 for detecting the point of time when the self-refresh control signal .phi.sref is disabled, to output the burst refresh control signal .phi.BRE which is enabled to the logic high level; a counter CNT0 38 for outputting the continuous pulse row CK0 having the period of time t1 in response to the enabled burst refresh control signal .phi.BRE; a counter CNTi 40 for counting the pulse row CK0 output from the counter CNT0 38, and isolating the operation of the burst refresh mode controller 36 when the predetermined number of pulses are generated, to disable the burst refresh control signal .phi.BRE; and a refresh master clock output circuit 42 for outputting one enabled pulse row of CK0 or CK1 to the master clock .phi.selfp for selecting the word line.

The operation of FIG. 7 will now be discussed with reference to FIG. 8. With the lapse of the predetermined time after going into the CBR mode, the self-refresh mode detector 30 outputs the self-refresh starting signal .phi.SRAS of the logic high level, and the self-refresh control signal .phi.sref output from the self-refresh mode controller 32 is thus enabled to the logic high level. The counter CNTs 34 outputs the pulse row CK1 having the period of time t2 and the pulse row CK1 is output as the master clock .phi.selfp for sequentially driving the word lines via the refresh master clock output circuit 42, thereby performing the self-refresh mode. The self-refresh mode is continuously performed while the starting signal .phi.SRAS is maintained at the logic high level. Thereby, all word lines are activated, and then sequentially activated again from the first word line.

If the control signals RAS and CAS are changed to the logic high level in order to go into the normal access mode, the self-refresh starting signal .phi.SRAS is disabled to the logic low level and the self-refresh control signal .phi.sref is thereby changed to the logic low level. At this time, the burst refresh mode controller 36 is activated to output the enabled burst refresh control signal .phi.BRE at the logic high level. As the burst refresh control signal .phi.BRE is enabled to the logic high level, the counter CNT0 38 outputs the pulse row CK0 having the period of time t1. The pulse row CK0 is output as the master clock .phi.selfp for sequentially driving the word lines via the refresh master clock output circuit 42, thereby performing the burst refresh mode. The self-refresh and burst refresh modes will be readily understood by those skilled in the art with reference to the description of FIGS. 3 to 6.

According to another preferred embodiment of the present invention, the memory device can be provided in which the burst refresh mode is performed for a short time at the completion of the self-refresh and then is converted to the normal access mode.

As the third embodiment of the present invention, the method is also possible that after the self-refresh mode starts, the burst refresh mode is performed prior to the self-refresh mode and the self-refresh mode is converted to the normal access mode immediately after completing the self-refresh mode. Such an embodiment can be obtained by designing the burst refresh mode controller 12 of FIG. 3 to detect only the rising edge of the self-refresh starting signal .phi.SRAS, to enable the burst refresh control signal .phi.BRE.

In accordance with the present invention, it is possible to obtain the semiconductor memory device wherein after the self-refresh mode starts, the burst refresh mode is performed prior to the self-refresh mode; or the self-refresh mode is performed immediately after going into the self-refresh mode, and the burst refresh mode is performed at the completion of the self-refresh mode and then is converted to the normal access mode; or the burst refresh mode is performed before and after the self-refresh mode. Accordingly, it is possible to shorten the refresh regulation time and secure the stable refresh of the memory cells by utilizing the memory device according to the present invention.