Method for Producing Electroless Barrier Layer and Solder Bump on Chip

The present invention is related to a method for producing a barrier layer and a solder bump on a chip.

In the electronic industrial field, wire bonding, tape automated bonding (TAB) and flip chip techniques are used for bonding a chip on a circuit board. Among these techniques, flip chip technique will be the most popular in the future because the number of contacts in every chip may achieve 16000 in this technique which is more than that in the other two techniques.

In the flip chip technique, a solder bump on an aluminum pad is utilized to bond a chip on a board. However, the solder bump is difficult to be deposited on the aluminum pad because the surface of the aluminum pad is subject to oxidation and thus an oxide layer is usually formed thereon. In order to overcome this problem, a conventional method uses evaporation deposition or electroplating procedure to produce the solder bump. Before the evaporation deposition or electroplating procedure, several metal layers, e.g. Cr/Cu/Au or Ti/Ni/Au, have to be sputtered on the aluminum pad first. The chromium layer serves as an adhesive layer because of its good adhesion property with the passivation layer, the copper layer functions for moistening, and the gold layer is used to prevent the oxidation of copper and enhance the solderability.

The conventional method has the shortcomings listed below.

1. Both evaporation deposition and electroplating methods have to be executed in vacuum which results in a complicated process;

2. A mask is necessary for preventing the metal from being deposited or plated on the passivation layer; and

3. In the evaporation deposition process, the vapor pressure of lead is higher than that of tin so that lead vaporizes and deposits on the aluminum pad earlier than tin, and thus the component of solder will not be uniform; and

4. The solder bump obtained by the conventional method is flat and difficult to be bonded to the board. Therefore, the chip with the solder bump has to be heated in a reducing atmosphere to have the solder melt and molded to a proper shape for bonding. That will result in a more complicated process.

In addition to the method for depositing a solder bump, The selection of materials for an adhesive layer and/or diffusion barrier layer is important as well. The adhesivity to the aluminum pad, the reaction rate with aluminum or Pb-Sn alloy, and the atomic diffusivity of the adhesive layer and/or diffusion barrier layer should all be taken into account. In general, the grain boundary diffusion of a metal film is more significant than its volume diffusion at a low temperature so that the final device is subject to be rejected owing to the grain boundary diffusion. Therefore, a single crystal or an amorphous material is usually used to construct the diffusion barrier layer to avoid the grain boundary diffusion. As the electroless Ni-P is amorphous, it will not be deposited on the inert material, i.e. the substrate, so that a mask is not needed therefor, and moreover, it has a good adhesiveness to the aluminum pad. Therefore, an electroless Ni-P layer is a good choice for serving as a diffusion barrier layer, as disclosed in Ref. 1.

In 1988, Wong et al disclose a method for producing a barrier layer which is an electroless Ni-P layer and a solder bump which consists of 60% Sn and 40% Pb, as shown in Ref. 2. However, the melting point of the solder bump Wang et al produces is too low (about 188.degree. C.) to be extensively applied to the industry. In the electronic package technique, "chip to substrate" belongs to the first level package and "substrate to card" belongs to the second level package. The higher the package level, the lower should the melting point of the material be to prevent the bonded material from melting again. Therefore, a solder bump having a higher melting point should be chosen for this purpose. In addition, the process disclosed by Wang et al needs "double" zincating procedures to form a zinc layer before forming the electroless Ni-P so that the process is complicated. On the other hand, a flux suitable for the high melting point bump should be carefully selected. Rosin which is a combination of three isomers of diterpene acid, i.e. sylvic acid, d-pimaric acid and l-pimaric acid, is conventionally used as a flux in the electronic industry. The sylvic acid is easy to proceed rearrangement at about 300.degree. C. to form a mixture of n-eoabietic acid and pyroabietic acid which are chemically inert. Therefore, rosin is not suitable for manufacturing a high melting point bump.

1. M. Inaba, K. Yamakawa, and N. Iwase, "Solder Bump Formation Using Electroless Plating and Ultrasonic Soldering", IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. 13, No. 1, 119, March 1990.

2. K. Wang, K. Chi and A. Rangappan, "Application of Electroless Nickel Plating in the Semiconductor Microcircuit Industry", Plating and Surface Finishing, 70, July 1988.

An object of the present invention is to offer a method for producing a barrier layer and a solder bump on a chip by which a solder bump having a high melting point can be manufactured.

Another object of the present invention is to offer a method for producing a barrier layer and a solder bump on a chip which needs zincation only once to simplify the process.

Another object of the present invention is to offer a method for producing a barrier layer and a solder bump on a chip which chooses a flux suitable for manufacturing the high melting point solder bump.

In accordance with the present invention, a method for producing a barrier layer and a solder bump on a chip includes: a) providing a silicon chip with a bump base; b) forming a metal pad, e.g. an aluminum pad, on the bump base; c) having the metal pad contact with a solution containing about 120.about.150 g/l NaOH, 20.about.25 g/l ZnO, 1 g/l NaNO.sub.3 and 45.about.55 g/l C.sub.4 H.sub.4 KNaO.sub.6 .multidot.4H.sub.2 O to form thereon a zinc layer, and preferably further containing tartaric acid for reducing a dissolving rate of the metal pad.; d) having the zinc layer contact with a deposition solution to deposit thereon an electroless barrier layer, e.g. an electroless Ni-P layer; and e) dipping the resulting silicon chip into a molten solder bath to form a solder bump on the electroless barrier layer. The method may further include a step b') before the step c) of washing the first metal pad with an alkaline solution, e.g. about 5 wt % NaOH solution, to remove a fat accumulated thereon, and a step b") before the step c) of washing the first metal pad with an acid solution, e.g. about 50 vol % HNO.sub.3 solution, to remove an oxide formed thereon.

In accordance with another aspect of the present invention, the deposition solution for depositing the Ni-P layer may include about 30.about.35 g/l NiCl.sub.2 .multidot.6H.sub.2 O, 7.5.about.10 g/l NaH.sub.2 PO.sub.2 .multidot.H.sub.2 O, 72.about.80 g/l Na.sub.3 C.sub.6 H.sub.5 O.sub.7 .multidot.2H.sub.2 O and 45.about.50 g/l NH.sub.4 Cl, and has a pH value of 9.5.about.10.5 so that the electroless barrier layer contains 4% phosphorous atoms. It may also include about 16.about.18 g/l NaH.sub.2 PO.sub.2 .multidot.H.sub.2 O, 60.about.70 (NH.sub.4).sub.2 SO.sub.4, 55.about.65 g/l Na.sub.3 C.sub.6 H.sub.5 O.sub.7 .multidot.2H.sub.2 O and 26.about.30 g/l NiSO.sub.4 .multidot.6H.sub.2 O, and has a pH value of 8.5.about.9.5 so that the electroless barrier layer contains 6.5% phosphorous atoms. Also, it may include about 20.about.30 g/l NiCl.sub.2 .multidot.6H.sub.2 O, 25.about.30 g/l NaH.sub.2 PO.sub.2 .multidot.H.sub.2 O, and 16 g/l Na.sub.2 C.sub.4 H.sub.4 O.sub.4 .multidot.7H.sub.2 O, and has a pH value of 4.6.about.5 so that the electroless barrier layer contains 8.5% phosphorous atoms.

In accordance with another aspect of the present invention, the electroless barrier layer is about 2 .mu.m thick.

In accordance with another aspect of the present invention, the solder bump consists of 95% Pb and 5% Sn.

In accordance with another aspect of the present invention, the method may further include a step d') after the step d) of having the electroless barrier layer contact with a solution containing a gold ion to deposit thereon an electroless gold layer, and the gold layer is preferably about 0.2 .mu.m thick. The solution containing the gold ion includes about 2 g/l KAu(CN).sub.2, 75 g/l NH.sub.4 Cl, 50 g/l Na.sub.3 C.sub.6 H.sub.5 O.sub.7 .multidot.2H.sub.2 O and 10 g/l NaH.sub.2 PO.sub.2 .multidot.H.sub.2 O.

In accordance with another aspect of the present invention, the method preferably further includes a step d") before the step e) of dipping the resulting chip into a flux solution for about 5 seconds. The flux solution is obtained by dissolving about 10 g stearic acid and 10 g glutamic acid in 20 ml alcohol.

Therefore, a chip manufactured by the present method includes the silicon chip having thereon a circuit and the bump base; the metal pad depositing on the bump base; the zinc layer obtained by zincation and depositing on the metal pad for enhancing the electroless barrier layer to be deposited thereon; and the solder bump. The chip preferably further includes a gold layer on the solder bump for improving a solderability of the solder bump. A phosphorous atom- percentage of the electroless Ni-P layer is about 4%, 6.5% or 8.5%. The solder bump consists of 95% Pb and 5% Sn.

The present invention may best be understood through the following description with reference to the accompanying drawings, in which:

FIG. 1 is a side view showing a preferred embodiment of a solder bump according to the present invention;

FIG. 2 is an Auger Electron Spectrum showing a crosssection of a preferred embodiment of a solder bump heat-treated at 150.degree. C. for 1000 hours according to the present invention;

FIG. 3 is an Auger Electron Spectrum showing a crosssection of another preferred embodiment of a solder bump heat-treated at 150.degree. C. for 1000 hours according to the present invention;

FIG. 4 is an Auger Electron Spectrum showing a crosssection of another preferred embodiment of a solder bump heat-treated at 150.degree. C. for 1000 hours according to the present invention.

The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for the purpose of illustration and description only; it is not intended to be exhaustive or to be limited to the precise form disclosed.

Firstly, a silicon chip with a bump base is provided and an aluminum pad is formed on the bump base. The aluminum pad is washed with an about 5 wt % NaOH solution to remove a fat accumulated thereon, and then washed with an about 50 vol % HNO.sub.3 solution to remove an oxide formed thereon. The aluminum pad is caused to contact with a solution containing about 120.about.150 g/l NaOH, 20.about.025 g/l ZnO, 1 g/l NaNO.sub.3 and 45.about.55 g/l C.sub.4 H.sub.4 KNaO.sub.6 .multidot.4H.sub.2 O to form thereon a zinc layer, and preferably further containing tartaric acid for reducing a dissolving rate of the aluminum pad. Afterwards, the zinc layer is caused to contact with a deposition solution to deposit thereon an electroless Ni-P layer which serves as a diffusion barrier layer. The deposition solution for depositing the Ni-P layer may include about 30.about.35 g/l NiCl.sub.2 .multidot.6H.sub.2 O, 7.5.about.10 g/l NaH.sub.2 PO.sub.2 .multidot.H.sub.2 O, 72.about.80 g/l Na.sub.3 C.sub.6 H.sub.5 O.sub.7 .multidot.2H.sub.2 O and 45.about.50 g/l NH.sub.4 Cl, and has a pH value of 9.5.about.10.5 so that the electroless barrier layer contains 4% phosphorous atoms. It may also include about 16.about.18 g/l NaH.sub.2 PO.sub.2 .multidot.H.sub.2 O, 60.about.70 (NH.sub.4).sub.2 SO.sub.4, 55.about.65 g/l Na.sub.3 C.sub.6 H.sub.5 O.sub.7 .multidot.2H.sub.2 O and 26.about.30 g/l NiSO.sub.4 .multidot.6H.sub.2 O, and has a pH value of 8.5.about.9.5 so that the electroless barrier layer contains 6.5% phosphorous atoms. Also, it may include about 20.about.30 g/l NiCl.sub.2 .multidot.6H.sub.2 O, 25.about.30 g/l NaH.sub.2 PO.sub.2 .multidot.H.sub.2 O, and 16 g/l Na.sub.2 C.sub.4 H.sub.4 O.sub.4 .multidot.7H.sub.2 O, and has a pH value of 4.6.about.5 so that the electroless barrier layer contains 8.5% phosphorous atoms. The electroless barrier layer is then caused to contact with a solution containing a gold ion to deposit thereon an electroless gold layer, and the gold layer is preferably about 0.2 .mu.m thick. The solution containing the gold ion includes about 2 g/l KAu(CN).sub.2, 75 g/l NH.sub.4 Cl, 50 g/l Na.sub.3 C.sub.6 H.sub.5 O.sub.7 .multidot.2H.sub.2 O and 10 g/l NaH.sub.2 PO.sub.2 .multidot.H.sub.2 O. The resulting silicon chip is then dipped into a molten solder bath which consists of 95% Pb and 5% Sn to form a solder bump on the electroless barrier layer, wherein the temperature of the solder furnace is higher than the melting point of the solder by about 40.degree..about.80.degree. C. and the deposition rate of the solder is about 12.about.19 mm/sec. Of course, the chip with the electroless Ni-P layer and the gold layer is preferably dipped into a flux solution for about 5 seconds before it enters the solder furnace. The flux solution is obtained by dissolving about 10g stearic acid and 10 g glutamic acid in 20 ml alcohol. In this example, the electroless barrier layer is about 2 .mu.m thick.

Please refer to FIG. 1 which is a side view showing a preferred embodiment of a solder bump according to the present invention. It is obvious that the solder bump presents a semi-spherical shape without the treatment of reflow soldering. Introducing a protective atmosphere into the solder furnace during the process can avoid an impurity deposited on the surface of the solder bump.

Please refer to FIGS. 2, 3 and 4 which are respectively an Auger Electron Spectrum (AES) showing a crosssection of two preferred embodiment of a solder bump heat-treated at 150.degree. C. for 1000 hours according to the present invention. Scanning starts at a location about 5 .mu.m above the interface between the solder bump and the electroless Ni-P layer, goes through the electroless Ni-P layer, the aluminum pad and stops at the silicon chip. In FIG. 2, the phosphorous atom-percentage of the electroless Ni-P layer is 8.5 wt%. It is obvious that the aluminum pad and the solder bump are still isolated by the electroless Ni-P layer even though it has been treated at a temperature of 150.degree. C. for 1000 hours.

In FIG. 3, the phosphorous atom-percentage of the electroless Ni-P layer is 6.5 wt %. Likewise, it is also found that the aluminum pad and the solder bump are still isolated by the electroless Ni-P layer even though it has been treated at a temperature of 150.degree. C. for 1000 hours.

In FIG. 4, the phosphorous atom-percentage of the electroless Ni-P layer is 4 wt %. The AES analysis also shows that the aluminum pad and the solder bump are still isolated by the electroless Ni-P layer.

To sum up, the present invention is a simple process for manufacturing an electroless Ni-P and a solder bump on a chip.

While the invention has been described in terms of what are presently considered to be the most practical and preferred embodiments, it is to be understood that the invention need not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.