Data Processor Decoding and Executing a Train of Instructions of Variable Length at Increased Speed

1. Field of the Invention

The present invention relates to a data processor, more particularly, to a microprocessor which decodes and executes a train of instructions of variable length.

2. Description of the Related Art

A typical microprocessor includes an instruction buffer for storing prefetched instruction codes, and a decoder which receives a train of instructions of variable length fed from the instruction buffer and decodes them to produce control information for data processing (e.g., control information on pipeline control, microprogram addresses, or the like). To decode and execute the train of instructions of variable length, the decoder must receive valid data, i.e., valid instruction codes. To this end, the instruction buffer in the conventional processor predecodes the train of instructions, thereby always to supply the decoder with valid data. At this time, the instruction buffer determines an update quantity of the instruction to be next decoded by the decoder.

However, where the instruction buffer must predecode many bits from among the instruction codes to determine the update quantity of the instructions, the predecoding requires as long a time as that necessary for the decoding of instructions by the decoder. Accordingly, a drawback occurs in that the instruction buffer cannot quickly feed valid instruction codes to the decoder. This leads to a lowering in the data processing speed of the entire processor and thus is not preferable.

An object of the present invention is to provide a data processor which can increase its data processing speed as a whole.

According to the present invention, there is provided a data processor for decoding and executing a train of instructions of variable length, the data processor including: a first instruction control unit for temporarily storing a prefetched instruction code and sequentially outputting the instruction code with units of a predetermined number of bits; and a second instruction control unit, operatively connected to the first instruction control unit, for decoding an instruction code fed from the first instruction control unit, generating control information for data processing based on the decoding, and outputting data indicating an instruction update demand quantity to the first instruction control unit, wherein the first instruction control unit effects a judgement, based on the data indicating the update demand quantity, of whether it has output a valid instruction cede of a length exceeding the update demand quantity, and provides an indication of validity or invalidity of the decoded instruction code and controls updating of the instruction code based on a result of the judgement.

Other objects and features of the present invention will be described hereinafter in detail by way of preferred embodiments with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram illustrating a principle of a data processor according to the present invention;

FIG. 2 is a functional block diagram illustrating an entire arrangement of the microprocessor according to an embodiment of the present invention;

FIG. 3 is a block diagram illustrating a constitution of the instruction buffer shown in FIG. 2;

FIG. 4 is a block diagram illustrating a constitution of the decoder shown in FIG. 2;

FIG. 5 is a circuit diagram illustrating a constitution of the main part of the instruction buffer of FIG. 3;

FIG. 6 is a circuit diagram illustrating a constitution of the main part of the decoder of FIG. 4;

FIG. 7 is a timing chart illustrating an example of the operation of the embodiment of FIG. 2; and

FIGS. 8a to 8e are views illustrating instruction formats employed in the embodiment of FIG. 2.

FIG. 1 illustrates the principle of the data processor according to the present invention.

Referring to FIG. 1, the data processor according to the present invention, which decodes and executes a train of instructions of variable length, includes a first instruction control unit 1 for temporarily storing a prefetched instruction code D1 and sequentially outputting the instruction code in units of a predetermined number of bits, and a second instruction control unit 2 for decoding an instruction code D2 fed from the first instruction control unit, generating control information D3 for data processing based on the decoding, and outputting data D4 indicating instruction update demand quantity to the first instruction control unit 1.

Where the first instruction control unit judges, based on the data D4 indicating the update demand quantity, that it has output a valid instruction code 2 of a length exceeding the update demand quantity, it provides an indication (V) that the decoded instruction code is valid, and updates instruction codes. On the other hand, where the first instruction control unit judges that it has not output a valid instruction code of a length exceeding the update demand quantity, it provides an indication (INV) that the decoded instruction code is invalid, and causes the second instruction control unit to effect the decoding again on the identical stage.

In the above arrangement, the first instruction control unit 1 outputs an instruction code irrespective of whether the instruction code is valid or invalid. The second instruction control unit 2 in turn assumes that the instruction code D2 fed from the first instruction control unit 1 is valid, and outputs the update demand quantity D4. Based on the update demand quantity D4, the first instruction control unit 1 judge the validity or the invalidity of the decoding and controls updating of the instruction code.

Therefore, it becomes unnecessary to effect predecoding for determination of the update quantity, as performed in the prior art, and thus it becomes possible to reduce time necessary for the supply of instruction codes. This contributes to an improvement in data processing speed of the entire processor.

Next, a preferred embodiment of the present invention will be explained with reference to FIGS. 2 to 8e.

FIG. 2 illustrates an entire structure of the microprocessor as an embodiment of the present invention.

The microprocessor according to the present embodiment includes an instruction control unit IC having an instruction buffer 11, a decoder 12, a pipeline controller 13, and a microprogram 14; an instruction execution unit IE having an address generator 15, an operation unit 16, and a register file 17; a memory control unit MC having an instruction access controller 18 and an operand access controller 19; and a bus control unit BC having an address controller 20, a bus supervisory controller 21, and a data transmitting and receiving unit 22. The instruction control unit IC reads, decodes, and executes instructions. The structure and operations of the instruction execution unit IE, the memory control unit MC and the bus control unit BC are not directly related to the present invention and thus the explanation thereof is omitted.

Next, the structure of the instruction buffer 11 and decoder 12 in the instruction control unit IC will be explained with reference to FIGS. 3 and 4, respectively. Note, the instruction buffer 11 and decoder 12 correspond to the first instruction control unit 1 and second instruction control unit 2 shown in FIG. 1, respectively.

Referring to FIG. 3, the instruction buffer 11 includes a buffer memory 31 of 8 bytes (B).times.6 in capacity; an input buffer 33 interposed between an instruction cache 32 of the instruction access controller 18 and the buffer memory 31; a rotator 34 for rotating bits to bring a first bit of an instruction code, read out of the buffer memory 31, to a first bit of an iQ bus QB; an instruction write/read controller 35 for controlling write/read operations of instructions (codes) for the buffer memory 31; a validity judging unit 36 for judging the validity of a decoded instruction; an instruction prefetch controller 37 for controlling fetching of an instruction code from the instruction cache 32; and an error detector 38 for selecting an exception processing based on an output of the instruction prefetch controller 37.

The instruction buffer 11 prefetches instruction codes from the instruction cache 32 into the buffer memory 31 until the buffer memory 31 becomes full of instruction codes. The fetched codes are sequentially read out in units of 16 bits via the iQ bus QB to the decoder 12. When the decoding of each 16-bit unit is completed, the buffer memory 31 becomes "empty" and in turn a new prefetch operation is carried out. In the read operation from the buffer memory 31, the rotator 34 rotates an instruction code, read out of the buffer memory 31 in units of 16 bits, thereby bringing a first bit of an instruction code to be next decoded to a first bit position of the iQ bus QB.

The instruction code, of 16-bit units fed to the decoder 12 from the instruction buffer 11 via the iQ bus QB constitutes part of a train of instructions of variable length having formats, for example, as shown FIGS. 8a to 8e. Note, in FIGS. 8a to 8e, reference OPD denotes an operand designating part; reference EX an extended part; reference OP an instruction code part; reference R a register designating part; reference S an operand size designating part; reference #I an immediate value; and reference DISP a displacement part.

Next, referring to FIG. 4, the decoder 12 includes a first instruction decoding unit 41; a second instruction decoding unit 42; an addressing decoding unit 43; an update demand quantity decoding unit 44 for computing an update demand quantity of instruction codes; an added mode decoding unit 45; a decoding sequencer 46 for forming a current decoding stage of instruction codes and sequentially selecting outputs of each of the decoding units according to the decoding stage; a selector 47 for selecting one of the outputs of the first and second instruction decoding units 41 and 42 under the control of the decoding sequencer 46; a register input unit 48 for receiving data from the iQ bus QB; a register output unit 49 for passing an output of the register input unit 48 in response to an internal clock .phi. 3 fed from the decoding sequencer 46; latches 41a, 42a, 43a, 43b, 44a, and 45a disposed at the input sides of the respective correspondingly numbered decoding units and responsive to an internal clock .phi. 1 fed from the decoding sequencer 46; and latches 41b, 42b, 44b, and 45b disposed at the output sides of the respective, correspondingly numbered decoding units 41, 42, 43, 44 and 45 and responsive to the internal clock .phi. 3.

The decoder 12 receives a train of instructions of variable length (see FIGS. 8a to 8e) fed through the iQ bus QB, and decodes them on the basis of the 16-bit base length. Concretely, the decoder 12 decodes the type and addressing mode, or the like, of a supplied instruction, and generates control information such as pipeline control information, operand address computing information and microprogram addresses that are used for data processing. At the same time, the decoder 12 outputs data RQHW indicating update demand quantity of instruction codes to the instruction buffer 11.

Based on the update demand quantity data RQHW, the instruction buffer 11 effects a validity/invalidity judgement (DCOVALiD) of the decoding and controls updating of instruction codes.

FIG. 5 illustrates a structure of a main part of the instruction buffer 11, i.e., the validity judging unit 36.

In the illustration, references iQVO3 to iQVO0 denote signals indicating how many half-words (HWs) counted from an upper bit are valid among 64-bit data (63 to 0) output to the iQ bus. For example, where the upper two half-words (bits 63 to 32) are valid, the signals iQVO0 and iQVO1 are at level "H", and the signals iQVO2 and iQVO3 are at level "L". References RQHW4 to RQHW1 denote update demand quantity indication signals (instruction code demand signals) mentioned above. For example, when the decoder 12 demands two half-words to be updated, only the signal RQHW2 is at level "H", and the other signals are at level "L". Reference iQWAiT denotes a wait demand signal; references HW0 to HW4 denote signals indicating update quantity of instruction codes that must be updated by the decoding; and reference DC0VALiD denotes a signal indicating the validity or invalidity of the decoding.

The circuit of FIG. 5 includes AND gates 500 to 503 responding to the wait demand signal iQWAiT and the signals iQVO0 to iQVO3; latch circuits 510 to 513 responding to a signal .phi.3 (an inverted signal .phi.3X) to latch outputs of the AND gates 500 to 503; NAND gates 520 to 523 responding to output signals of the latch circuits 510 to 513 and instruction code demand signals RQHW1 to RQHW4; inverters 530 to 533 of input inverting type responding to outputs of the NAND gates 520 to 523 and providing the signals HW1 TO HW4; inverters 540 to 543 responding to outputs of the latch circuits 510 to 513; an AND gate 51 responding to an output of the inverter 543 and the instruction code demand signal RQHW4; an AND gate 52 responding to an output of the inverter 542 and the instruction code demand signal RQHW3; a NOR gate 53 responding to outputs of the AND gates 51 and 52; an AND gate 54 responding to an output of the inverter 541 and the instruction code demand signal RQHW2; a NOR gate 55 responding to an output of the AND gate 54 and an output of the inverter 540; an OR gate 56 of input inverting type responding to outputs of the NOR gates 53 and 55 to provide the signal HW0; and an inverter 57 responding to an output of the OR gate 56 to provide the signal DCOVALiD for judging the validity of decoded instruction codes.

As explained above, the instruction buffer 11 produces the information iQVO3 to iQVO0 indicating how many HWs, counted from the upper bit, are valid among data output to the iQ bus QB, based on valid bits of the respective buffer. Based on the produced information and the instruction code demand signals RQHW4 to RQHW1 fed from the decoder 12, the validity judging unit 36 in the instruction buffer 11 judges whether or not instruction codes must be updated. Concretely, where the instruction buffer 11 has output a valid instruction code of a length exceeding the update demand quantity, the instruction buffer 11 provides a validity judging signal DCOVALiD of "H" level, indicating that the decoded instruction code is valid, and effects updating of instruction codes. On the other hand, where the instruction buffer 11 has not output a valid instruction code of length exceeding the update demand quantity, it provides a validity judging signal DCOVALiD of "L" level indicating that the decoded instruction code is invalid. In this case, the decoder 12 effects the decoding again on the identical stage.

FIG. 6 illustrates a structure of a main part of the decoder 12 of FIG. 4. The illustration corresponds to the update demand quantity decoding unit 44, part of the decoding sequencer 46, and latches provided in the periphery thereof.

The circuit of FIG. 6 includes a programmable logic array (PLA) 600; a NAND gate 601 responding to a signal .phi. 1 and a decoding input latch enable signal DCiLE1; an inverter 602 of input inverting type responding to an output of the NAND gate 601; a latch circuit 603 for latching an instruction code from the iQ bus QB in response to the control signal .phi. 1 (an inverted signal .phi. 1X) and supplying the same to the PLA 600; a NAND gate 604 responding to the signal .phi. 1 and a decoding input latch enable signal DCiLE2; an inverter 605 of input inverting type responding to an output of the NAND gate 604; a latch circuit 606 for latching an instruction code from the iQ bus QB in response to the control signal .phi. 1 (inverted signal .phi. 1X) and supplying the same to the PLA 600; a NAND gate 611 responding to a signal .phi. 3 and a decoding output latch enable signal DCLE; an inverter 612 of input inverting type responding to an output of the NAND gate 611; latch circuits 613 to 616 for latching data from the PLA 600 in response to the signal .phi. 3 (inverted signal .phi. 3X) and providing the instruction code demand signals RQHW4 to RQHW 1; latch circuits 617 to 619 for latching data from the PLA 600 in response to the signal .phi. 3 (inverted signal .phi. 3X); a NAND gate 621 responding to the signal .phi. 1 and the signal DCOVALiD indicating the validity of decoded instruction codes; an inverter 622 of input inverting type responding to an output of the NAND gate 621; latch circuits 623 to 625 for latching outputs of the latch circuits 617 to 619 in response to the signal .phi. 1 (inverted signal .phi. 1X) and providing decoding signals DC1 to DC3; latch circuits 626 and 627 for latching outputs of the latch circuits 623 and 624 in response to the control signal .phi. 3 (inverted signal .phi. 3X); an inverter 630 responding to the validity judging signal DCOVALiD; an AND gate 631 responding to an output of the latch circuit 617 and the validity judging signal DCOVALiD; an AND gate 632 responding to an output of the latch circuit 626 and an output of the inverter 630; a NOR gate 633 responding to outputs of the AND gates 631 and 632; an inverter 634 of input inverting type for generating a decoding latch enable signal DCiLE1 in response to an output of the NOR gate 633; an AND gate 635 responding to an output of the latch circuit 618 and the validity judging signal DCOVALiD; an AND gate 636 responding to an output of the latch circuit 627 and an output of the inverter 630; a NOR gate 637 responding to outputs of the AND gates 635 and 636; and an inverter 638 of input inverting type for generating a decoding latch enable signal DCiLE2 in response to an output of the NOR gate 637.

Next, the operation of the microprocessor according to the present embodiment will be explained with reference to the timing chart of FIG. 7, citing an example of a MOV (move) instruction.

(a) Cycle 1

The decoder 12 latches data (instruction codes) from the iQ bus QB in response to the control signal .phi. 1, and decodes the same through the PLA 600. In the example of FIG. 7, a result of the decoding indicates that three half-words each comprising 16 bits can simultaneously be decoded. The decoder 12 asserts, therefore, the instruction code demand signal RQHW3 to request updating of instruction codes of three half-words. On the other hand, the instruction buffer 11 produces the information iQVO3 to iQVO0 indicating how many HWs, counted from the upper bit, are valid among the data output to the iQ bus QB, based on valid bits of the respective buffer. According to the produced information and the instruction code demand signals RQHW4 to RQHW1 fed from the decoder 12, the validity judging unit 36 (see FIG. 5) in the instruction buffer 11 judges whether or not instruction codes must be updated.

In this case, since the instruction buffer 11 has not output a valid instruction code of a length exceeding the update demand quantity, it negates the validity judging signal DCOVALiD, asserts the instruction code HW0, and outputs the instruction code from the identical location of the buffer to the iQ bus QB in the next cycle 2.

Since the validity judging signal DCOVALiD has been negated, the decoder 12 recognizes (detects) that the decoded instruction code is invalid, by means of the circuit of FIG. 6, and effects the decoding again on the identical stage.

(b) Cycle 2

A decoding processing similar to that of Cycle 1 is carried out. The instruction buffer 11 outputs instruction codes prefetched in the cycle 1 to the iQ bus QB (bits 31 to 0). As a result, valid codes of four half-words are ready, and the validity judging signal DCOVALiD is asserted. The instruction buffer 11 updates instruction codes of three half-words and the decoder 12 in turn transits its operation to the next decoding stage DC2.

(c) Cycle 3

The decoder 12 provides an update demand quantity of two half-words. There is, however, valid data of only one half-word, so that the validity judging signal DCOVALiD is negated.

(d) Cycle 4

There are two valid half-words. However, a wait demand signal iQWAiT is provided under the pipeline control, so that the signals iQVO1 to iQVO3 are thereby to negate the validity judging signal DCOVALiD.

(e) Cycle 5

Since the wait demand signal iQWAiT is negated, the validity judging signal DCOVALiD is asserted. The instruction buffer 11 updates instruction codes of two half-words and the decoder 12 in turn transits its operation to the next decoding stage DC1 (Cycle 6).

As explained above, according to the present embodiment, the instruction buffer 11 sequentially feeds instruction codes in units of a predetermined number of bits to the decoder 12, irrespective of the validity or invalidity of the instruction codes. The decoder 12 in turn assumes that the instruction codes fed from the instruction buffer 11 are Valid, and outputs update demand quantity to the instruction buffer 11. Based on the update demand quantity, the instruction buffer 11 judges the validity or the invalidity of the decoding and controls updating of the instruction code. Accordingly, it becomes unnecessary to effect predecoding for the determination of update quantity as required in the prior art and thus it becomes possible to reduce the time necessary for the supply of instruction codes. This results in an improvement in the data processing speed of the entire processor.

Although the present invention has been disclosed and described by way of one embodiment, it is apparent to those skilled in the art that other embodiments and modifications of the present invention are possible without departing from the spirit or essential features thereof.