Method and Apparatus for Managing Timing Requirement Specifications and Confirmations and Generating Timing Models and Constraints for a VLSI Circuit

1. In a computer system comprising a plurality of client designers designing a VLSI circuit using a top down specification approach and a bottom up confirmation process, an apparatus for managing timing specifications and measurements of said VLSI circuit, and generating timing models and timing constraints for said VLSI circuit, said apparatus comprising: a) computer-readable repository means for storing a pin timing information table, a pin characteristics table, a net table, a flow-through arc timing information table, and a hierarchy table said VLSI circuit being represented as an hierarchy of functional block instances of a plurality of functional blocks, each functional block having a plurality of pins, said pin instances further being connected to each other forming a plurality of nets; b) loading means coupled to said computer-readable repository means for receiving information to be stored in said tables of said computer-readable repository means as inputs, and loading said information into said tables of said computer-readable repository means; c) timing model generation means coupled to said computer-readable repository means for generating timing models of said functional blocks of said VLSI circuit using the information stored in said computer-readable repository means; and d) timing analysis and constraints generation means coupled to said computer-readable repository means, said loading means, and said timing model generation means for generating timing constraints of said functional block instances of said VLSI circuit using the information stored in said computer-readable repository means, using said generated timing models, and causing a plurality of timing analysis scripts to be executed.

2. The apparatus as set forth in claim 1, wherein, said pin timing information table includes timing specification and measurements of said pin instances, said pin characteristic table includes pin characteristics of said pin instances, said net table includes net compositions of said nets, said flow-through arc timing information table includes timing specifications and measurements of a plurality of flow-through arc instances, and said hierarchy table includes functional block instance hierarchical relationships.

3. The apparatus as set forth in claim 2, wherein, said pin timing information table further comprises a class attribute field for storing entries corresponding to each of said timing specifications and measurements of said pin instances, said entries distinguishing between the current and historical timing specifications and measurements of said pin instances; and said flow-through arc timing information table further comprises a class attribute field for storing entries corresponding to each of said timing specifications and measurements of said flow-through arc instances, said entries distinguishing between the current and historical flow-through arc timing specifications and measurements of said flow-through arc instances.

4. The apparatus as set forth in claim 2, wherein, said functional blocks of said VLSI circuit have no transparent latches at their boundaries, and said VLSI circuit has a single one phased clock; said pin timing information table comprises a functional block instance name, a pin name, a set up rise timing value, a set up fall timing value, a hold rise timing value, a hold fall timing value, and clock-to-output-q rise and fall timing values for each pin instance; said flow-through arc timing information table comprises a functional block instance name, a flow-through arc "from" pin name, a flow-through arc "to" pin name, a flow-through arc rise timing value, and a flow-through arc fall timing value for each flow-through arc instance; said pin characteristics table comprises a functional block instance name, a pin name, a pin type, and an ordered port position for each pin instance; said net table comprises a net name, a functional block instance name, and a pin name for each pin of a net; said hierarchy table comprises a functional block name, a functional block instance name, and a parent functional block instance name for each functional block instance.

5. The apparatus as set forth in claim 4, wherein, said pin timing information table further comprises a capacitance value, a driver resistance high value, and driver resistance low value for each of a subset of said pin instances of said VLSI circuit.

6. The apparatus as set forth in claim 2, wherein, said computer-readable repository means further comprises a pin timing constraint table for storing timing constraints of said pin instances, said pin timing constraint table being used by said timing analysis and constraints generation means for generating timing constraints for a functional block instance of said VLSI circuit.

7. The apparatus as set forth in claim 6 wherein said pin timing constraint table comprises a functional block instance name, a pin name, a set up rise timing value, a set up fall timing value, a hold rise timing value, a hold fall timing value, and clock-to-output-q rise and fall timing value for each pin instance.

8. The apparatus as set forth in claim 1, wherein, said timing model generation means generates timing models of said functional blocks by extracting pin timing information and pin characteristics associated with the functional blocks, joining said extracted information, and sorting said joined information by the pins' port positions.

9. The apparatus as set forth in claim 1, wherein, said timing analysis and constraints generation means comprises d.1) timing analysis means for running timing verifications and generating timing measurements for said functional block instances in response to net lists, timing models of said functional blocks, and said timing analysis scripts; and d.2) timing constraints generation means, coupled to said loading means, said computer-readable repository, and said timing analysis means, for generating said net lists, for causing said timing model generation means to generate said timing models of said functional blocks, for causing said timing analysis means to execute said timing analysis scripts thereby generating timing measurements of said functional block instances, for identifying nodes, of said functional block instances, that are subject to generation of said timing constraints by said timing constraints generation means, for causing said loading means to load said generated timing measurements into said computer-readable repository means, and for generating said timing constraints for said functional block instances in accordance to said functional blocks instances' pins' pin types.

10. The apparatus as set forth in claim 9, wherein, said timing analysis scripts comprise timing analysis instructions to timing analysis tools for loading said net lists and said timing models, running timing verifications, generating timing measurements, and identifying nodes, of said functional block instances, that are subject to generation of said timing constraints by said timing constraints generation means.

11. The apparatus as set forth in claim 1, wherein, said loading means propagates timing information from input pins of a net to other pins of the net.

12. In a computer system comprising a plurality of client designers designing a VLSI circuit using a top down specification approach and a bottom up confirmation process, a computer-implemented method for managing timing specifications and measurements of said VLSI circuit, and generating timing models and timing constraints for said VLSI circuit, said method comprising the steps: a) receiving information to be stored in a computer-readable repository as inputs, and loading said information into said computer-readable repository, said computer-readable repository having a pin timing information table, a flow-through arc timing information table, a pin characteristics table, a net table, and a hierarchy table; b) storing said information in said computer-readable repository, wherein said information includes pin timing specifications and measurements for storing in said pin timing information table, flow-through arc instances for storing in a flow-through arc timing information table, pin characteristics for storing in said pin characteristics table, net compositions for storing in said net table, and functional block instance hierarchical relationships of said VLSI circuit for storing in said hierarchy table, said VLSI circuit being represented as an hierarchy of functional block instances of a plurality of functional blocks, each functional block having a plurality of pins, said pin instances further being connected to each other forming a plurality of nets; c) generating a timing models file of said functional blocks of said VLSI circuit using the information stored in said computer-readable repository; and d) generating a timing constraint table of said functional block instances of said VLSI circuit using the information stored in said pin-timing information table, said flow-through arc timing information table, said pin characteristics table, said net table, and said hierarchy table, using said generated timing models file, and causing a plurality of timing analysis scripts to be executed.

13. The method as set forth in claim 12, wherein, said computer-readable repository further comprises a pin timing constraint table for storing timing constraints of said pin instances, said pin timing constraint table being used by a timing analysis and constraints generation means for generating said timing constraint table for a functional block instance of said VLSI circuit.

14. The method as set forth in claim 13 wherein said pin characteristics table comprises a functional block instance name, a pin name, a pin type, and an ordered port position for each pin instance.

15. The method as set forth in claim 12, wherein, said functional blocks of said VLSI circuit have no transparent latches at their boundaries, and said VLSI circuit has a single one phased clock; said pin timing information table comprises a functional block instance name, a pin name, a set up rise timing value, a set up fall timing value, a hold rise timing value, a hold fall timing value, and clock-to-output-q rise and fall timing values for each pin instance; said flow-through arc timing information table comprises a functional block instance name, a flow-through arc "from" pin name, a flow-through arc "to" pin name, a flow-through arc rise timing value, and a flow-through arc fall timing value for each flow-through arc instance; said net table comprises a net name, a functional block instance name, and a pin name for each pin of a net; said hierarchy table comprises a functional block name, a functional block instance name, and a parent functional block instance name for each functional block instance; said computer-readable repository means further comprises a pin timing constraint table including a functional block instance name, a pin name, a set up rise timing value, a set up fall timing value, a hold rise timing value, a hold fall timing value, and clock-to-output-q rise and fall timing values for each pin instance.

16. The method as set forth in claim 15, wherein, said pin timing information table further comprises a capacitance value, a driver resistance high value, and driver resistance low value for each of a subset of said pin instances of said VLSI circuit.

17. The method as set forth in claim 12, wherein, said pin timing information table further comprises a class attribute field for storing entries corresponding to each of said timing specifications and measurements of said pin instances, said entries distinguishing between the current and historical timing specifications and measurements; and said flow-through arc timing information table further comprises a class attribute field for storing entries corresponding to each of said flow-through arc instances, said entries distinguishing between the current and historical flow-through arc timing specifications and measurements of said flow-through arc instances.

18. The method as set forth in claim 12, wherein, said step c) comprises the steps of extracting pin timing information and pin characteristics associated with the functional blocks, joining said extracted information, and sorting said joined information by the pins' port positions.

19. The method as set forth in claim 12, wherein, said step d) comprises the steps of: d.1) generating net lists of said functional blocks; d.2) causing timing verifications to be run, causing timing measurements for said functional block instances to be generated, and causing identification of nodes that are subject to generation of said timing constraint table in response to the generation of the net lists, the generation of the timing models file of said functional blocks, and said timing analysis scripts; and d.3) causing said generated timing measurements to be loaded into said computer-readable repository; and d.4) generating said timing constraint table for said functional block instances in accordance to said functional blocks instances' pins' pin types.

20. The method as set forth in claim 19, wherein, said timing analysis scripts comprise timing analysis instructions to timing analysis tools for loading said net lists and said timing models file, running timing verifications, generating timing measurements, and identifying the nodes, of said functional block instances, that are subject to generation of said timing constraint tables.

21. The method as set forth in claim 12, wherein the loading of information into the computer-readable repository comprises propagating timing information from input pins of a net to other pins of the net.