US 5,579,573 AGrant
Method for Fabricating an Undercoated Chip Electrically Interconnected to a Substrate
Issue Date:1996-12-03
•16 Claims
•1 Drawing Sheets
Abstract
Method for fabricating an undercoated chip electrically interconnected to a substrate. The method includes the initial step of depositing a predetermined quantity of a liquid undercoat material onto the chip or the substrate. The method continues with the step of interconnecting the chip to the substrate so as to form an electrical interconnection bond therebetween. Finally, the method concludes with the step of heating, reflowing and curing the undercoat material during or after the step of electrically interconnecting the chip to the substrate.
Metadata
Assignee
- Ford Motor Company
Inventors
- Jay D. Baker
- Cuong V. Pham
- Robert E. Belke, Jr.
Application Information
Application Number:US 3208125
Filing Date:1994-10-11
Priority Date:1994-10-11
Art Unit:326
Classifications
IPC:
H05K 334H05K 338H01L 2150
Field of Search:
29174204216228427428437832;840;841259;263192.3520;35175;180.1;180.21;180.22;226;248.1;254;262.296901211
Patent Drawings (1 sheets)
Description
Technical Field
This invention relates to fabricating an undercoated chip. In particular, this invention relates to pre-dispensing an undercoat material onto a chip or a substrate prior to electrical interconnection between the chip and the substrate.
Background Art
The process of undercoating a chip significantly increases the reliability of the chip when mounted to a printed wiring board interconnected substrate. Conventional techniques for applying undercoat material include dispensing the undercoat material after the electrical interconnection is made between the chip and the substrate. The dispensed undercoat is then cured in a separate process step.
Chip attach methods using C4 solder ball technology are well known in the art. Using conventional techniques, chips with C4 solder balls are aligned with a relief area (dimple, cavity, or the like) or connection pads on a substrate and pressed into place.
The techniques used for sealing the chips attached to the substrate include injecting sealant material around the periphery of the chip/substrate interface or completely coating the chip and the substrate assembly with sealing material, as well as allowing sealant to flow between the substrate and chip, around the solder balls. Injecting sealant around the periphery does not provide a continuous layer of sealing material and leaves some C4 joints exposed under the chip.
One known method of applying undercoat material to a chip prior to electrical interconnection is disclosed in U.S. Pat. No. 5,279,711 ('711). The '711 reference discloses a method of simultaneously forming a C4 solder connection and sealing the chip/substrate electrical interface utilizing a thin thermoplastic or thermoset material bonded to the top of the substrate prior to the attachment of a chip.
However, the '711 reference discloses a method of attaching and sealing a chip and a substrate in which the substrate includes cavities of a diameter and depth that take into account the statistical variance in the dimensions of C4 solder balls. The method of applying the layer of sealing material to the substrate includes offset printing techniques using a master template having projections with dimensions such that the sealant/adhesive material is applied on the substrate surface while bridging the cavities where the sealant/adhesive materials must not be applied. The material, therefore, is applied on the substrate where the cavities are not located.
The known prior art fails to disclose a method of applying a sealant/adhesive material to a chip prior to electrical interconnection with a substrate which does not require definition of the adhesive surface prior to applying the material to the chip or substrate. In addition, the known prior art fails to disclose a method of applying a sealant/adhesive material to a chip not having C4 solder balls prior to electrical interconnection with a substrate.
Therefore, a need exists for a method and system of applying adhesive/sealant material to a chip or substrate prior to the electrical interconnection therebetween which is quick, reliable, less expensive, and conducive to high volume electronics manufacture in a wide variety of chip/substrate applications.
Disclosure of the Invention
It is a general object of the present invention to provide a method for fabricating an undercoated chip electrically interconnected to a substrate.
It is another object of the present invention to provide a method of depositing an undercoat material to a chip or substrate prior to the electrical interconnection therebetween.
It is a further object of the present invention to provide a method of depositing an undercoat material to a chip or substrate prior to the electrical interconnection therebetween which is quick, reliable, less expensive, and conducive to high volume electronics manufacture in a wide variety of chip/substrate applications.
It is yet another object of the present invention to provide a method of depositing an undercoat material to a plurality of chips arranged in an array on an undiced wafer or a diced and stretched wafer prior to attaching the chips to the substrate.
In carrying out the above objects and other objects, features, and advantages of the present invention, a method is provided for applying an undercoat material to a chip or substrate prior to the electrical interconnection therebetween.
The method includes the initial step of depositing the liquid undercoat material to the chip or substrate. The chips may be arranged in an array on an undiced wafer or diced and arranged for mass production. The liquid undercoat material may be deposited in a preform shape or may be deposited onto the entire bonding surface of the chip or the substrate.
In keeping with the invention, the chip is interconnected to the substrate so as to form an electrical interconnection bond therebetween. This is accomplished utilizing mass diffusion bonding.
Finally, the electrically interconnected chip/substrate pair is subjected to elevated temperatures sufficient to reflow and cure the pre-dispensed undercoat material either during or after the electrical interconnection step.
The above objects and other objects, features, and advantages of the present invention, are readily apparent from the following detailed description of the best mode for carrying out the invention when taken in connection with the accompanying drawings.
Brief Description of the Drawings
The present invention will be apparent from the detailed description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a block diagram illustrating the general sequence of steps associated with the preferred embodiment of the present invention;
FIG. 2 is a perspective view of a plurality of chips arranged in an array on an undiced wafer;
FIG. 3 is a perspective view of a single chip with pre-dispensed undercoat material; and
FIG. 4 is a perspective view of a chip electrically interconnected with a substrate.
Best Modes for Carrying Out the Invention
Referring now to FIG. 1, the basic steps of the process are set forth in a block diagram. The other Figures are referenced in the block diagram where appropriate to permit easy understanding of the preferred order of the steps. It should be understood that some of the steps may be supplemented with additional steps.
The method begins with the step of depositing a predetermined quantity of a liquid undercoat material onto a chip or the substrate as shown by block 10. The chip may be, for example, active or passive electronic or microelectronic devices, such as integrated circuits, power transistors, capacitors, capacitor arrays, resistors, resistor arrays and networks, resonator crystals, diodes, optoelectric devices, laser chips, and other similar devices. In the integrated circuit case, the chip may be a flip-chip semiconductor device having bumped pads. The substrate is typically a printed wiring board.
The step of depositing the undercoat material is further illustrated in FIG. 2, in which the undercoat material 12 is pre-applied onto the individual chips 14 while the chips 14 are still arranged in an array on a wafer, The chip shown in FIG. 2 is an integrated circuit device having bumped pads 16. Alternatively, the pre-dispensing of the undercoat material 12 can be performed directly after the wafer sawing operation. In addition, the undercoat material 12 can be deposited onto the substrate rather than the chip 14.
The undercoat material 12 is deposited utilizing a solvent or a preform, such as a "hot melt" extrusion tip in the form of a "dot", to the chip in a location and volume so as not to interfere with the initial establishment of electrical contact with the substrate. Other suitable preforms include material that is cut from a ribbon spool or already formed in predetermined shapes for subsequent placement upon the chip or the substrate.
Suitable undercoat materials for the present invention include high temperature thermoplastic materials such as liquid crystal polyesters (e.g. Xydar.TM. or Vectra.TM.), poly(ether ether ketones) (e.g. ICI's PEEK), or the poly(aryl ether ketones) in either preform or extruded shape. Additional suitable thermoplastic materials include, for example, ABS-containing resinous materials (ABS/PC, ABS/polysulfone, ABS/PVC), acetals, acrylics, alkyds, allylic ethers, cellulosic esters, chlorinated polyalkylene ethers, cyanate/cyanamides, furans, polyalkylene ethers, polyamides (Nylons), polyarylene ethers, polybutadienes, polycarbonates, polyesters, polyfluorocarbons, polyimides, polyphenylenes, polyphenylene sulfides, polypropylenes, polystyrenes, polysulfones, polyurethanes, polyvinyl acetates, polyvinyl chlorides, polyvinyl chloride/vinylidine chlorides, polyetherimides, polyether ether imides, and the like and mixtures thereof. The thermoplastic material is formulated to have a sufficient linear Coefficient of Thermal Expansion (CTE) modification through appropriate filling.
The undercoating of the chip/substrate pair mechanically mitigates the substantial CTE differences between the chip (3.5 ppm/.degree.C.) and the substrate (12-15 ppm/.degree.C. in-plane) by maintaining local stiffness. Out-of-plane stresses are minimized by matching the CTE of the interconnection metallization. Therefore, commercially available undercoat materials are epoxy materials filled with sufficient low expansion fillers, e.g., silica or .beta.-eucryptite, to achieve a linear CTE that matches the interconnection materials. In the case of a solder interconnection (such as the IBM C4 process), the linear CTE of the appropriate undercoat material would be 23-24 ppm/.degree.C.
Thermosetting materials, such as high glass transition anhydride-cured epoxy compositions, would also be suitable for the present invention. Suitable thermoset materials include epoxies and modified epoxies, melamine-formaldehydes, urea formaldehydes, phelonic resins, poly(bis-maleimides), acetylene-terminated BPA resins, IPN polymers, triazine resins, and the like and mixtures thereof. The thermoset material would be dispensed in a liquid unpolymerized state onto the chip surface away from the electrical interconnects. However, a subsequent heating step is necessary to partially react the material into a "B-stageable" thermoplastic-like material, capable of reflowing and curing into a ternary matrix upon additional exposure to heat and pressure.
In an alternative embodiment of the present invention, the undercoat material 12 is applied to the entire bonding area of the chip 14 or the substrate, as illustrated in FIG. 3. The undercoat material 12 maybe applied using spray coating or adhesive spinning techniques.
An additional step is required, however, in which the undercoat material 12 is etched so as to remove the undercoat material 12 from an area that is necessary to form the electrical interconnection, e.g., the bumped pads. In addition to solder alloys, the bumps may be other monolithic binary or ternary metal systems, or intrinsicly or extrinsicly conductive polymers, such as silver-filled epoxies. The method of the present invention is not limited to chips having bumped pads, but also applies to chips having wire posts, mesa or plateau configurations, or other similar electrical interconnections. Any conventional RF plasma etching process, e.g., DC, RF, or microwave, may be utilized to remove the undercoat material from the electrical contact area.
The method of the present invention continues with the step of interconnecting the chip to the substrate so as to form an electrical interconnection bond between the chip 14 and the substrate 18 as shown by block 20 in FIG. 1. This is accomplished by mass diffusion bonding. For a chip having bumped pads, the electrical interconnection is accomplished utilizing a monolithic binary or ternary metal system. The electrically interconnected chip/substrate pair 22 is shown in FIG. 4.
Finally, the method of fabricating an undercoated chip concludes with the step of heating, reflowing and curing the undercoat material as shown by block 24. This step can be performed either during or after the step 20 of interconnecting the chip with the substrate.
If the undercoat material is cured after the electrical interconnection step, it can be performed at a dedicated station or during another process heat cycle such as a subsequent solder reflow step.
While the best modes for carrying out the invention have been described in detail, those familiar with the art to which this invention relates will recognize various alternative designs and embodiments for practicing the invention as defined by the following claims.
Claims
What is claimed is:
1. A method of fabricating an undercoated chip electrically interconnected to a substrate, the chip having a first and second surface and having electrical interconnections on the first surface, and the substrate having a first and second surface and having means for interconnecting on the first surface corresponding to the electrical interconnections, the method comprising: (a) depositing a predetermined quantity of an undercoat material having sufficient low expansion fillers to achieve a linear coefficient of thermal expansion (CTE) matching a CTE of the electrical interconnections onto the first surface of one of the chip and the substrate; (b) etching the undercoat material from the first surface of the one of the chip and the substrate until the electrical interconnections or the means for interconnecting are exposed; (c) connecting the electrical interconnections of the chip to the means for interconnecting of the substrate so as to form an electrical interconnection bond therebetween; and (d) heating, reflowing and curing the undercoat material during or after step (c).
2. The method of claim 1, wherein the chip is connected to the substrate by mass diffusion bonding.
3. The method of claim 1, wherein the undercoat material is a thermoplastic composition.
4. The method of claim 1, wherein the undercoat material is a B-stageable thermoset composition.
5. The method of claim 4, further comprising the step of subjecting the undercoat material to heat prior to the step of connecting the chip to the substrate.
6. The method of claim 1, wherein the chip is a flip-chip semiconductor device and the electrical interconnections are bumped pads.
7. The method of claim 6, wherein the bumped pads of the chip are connected to the substrate by a monolithic binary or a ternary metal system.
8. The method of claim 1 wherein the step of depositing the undercoat material is performed utilizing spinning or spray coating techniques.
9. The method of claim 1, wherein the undercoat material is etched utilizing plasma etching techniques.
10. The method of claim 1, wherein the chip is one of a plurality of chips arranged in an array on a wafer.
11. The method of claim 1, wherein the chip is an active electronic or microelectronic device.
12. The method of claim 1, wherein the chip is a passive electronic or microelectronic device.
13. A method of fabricating an undercoated chip electrically interconnected to a substrate, the chip having a first and second surface and having electrical interconnections on the first surface, and the substrate having a first and second surface and having means for interconnecting on the first surface corresponding to the electrical interconnections, the method comprising: (a) depositing a predetermined quantity of an undercoat material having sufficient low expansion fillers to achieve a linear coefficient of thermal expansion (CTE) matching a CTE of the electrical interconnections onto predetermined locations on the first surface of one of the chip and the substrate, the predetermined locations not interfering with the electrical interconnections or the means for interconnecting, respectively; (b) connecting the electrical interconnections of the chip to the means for interconnecting of the substrate so as to form an electrical interconnection bond therebetween; and (c) heating, reflowing and curing the undercoat material during or after step (c).
14. The method of claim 13, wherein the undercoat material is in a preform shape.
15. The method of claim 13, wherein the undercoat material is in an extruded shape.
16. The method of claim 13, wherein the step of depositing the undercoat material is performed utilizing a hot-melt extrusion tip.
Patent Citations (20)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4381602 | 1983-05-01 | McIver | |
| US4604644 | 1986-08-01 | Beckham et al. | |
| US4693770 | 1987-09-01 | Hatada | |
| US4928387 | 1990-05-01 | Mather et al. | |
| US4955132 | 1990-09-01 | Ozawa | |
| US4999699 | 1991-03-01 | Christie et al. | |
| US5037780 | 1991-08-01 | Fujimoto et al. | |
| US5086558 | 1992-02-01 | Grube et al. | |
| US5089440 | 1992-02-01 | Christie et al. | |
| US5121190 | 1992-06-01 | Hsiao et al. | |
| US5133495 | 1992-07-01 | Angulas et al. | |
| US5147084 | 1992-09-01 | Behun et al. | |
| US5279711 | 1994-01-01 | Frankeny et al. | |
| US5361491 | 1994-11-01 | Oomachi et al. | |
| US5365656 | 1994-11-01 | Dahringer et al. | |
| US5384952 | 1995-01-01 | Matsui | |
| US5386624 | 1995-02-01 | George et al. | |
| JPX56-35448 | 1981-04-01 | ||
| JPX62-45138 | 1987-02-01 | ||
| JPX21-65613 | 1990-06-01 |
Non-Patent Literature (2)
- "Gold Ball Bumps For Adhesive Flip Chip Assembly", R. Aschenbrenner et al, Technische Universitat Berlin, Germany, 1995.
- IBM Technical Disclosure Bulletin, vol. 10, No. 4, Sep. 1967, pp. 399-400.