US 5,578,855 AGrant
High-Voltage CMOS Transistors on a Standard CMOS Wafer
Issue Date:1996-11-26
•17 Claims
•2 Drawing Sheets
Abstract
A low-voltage 0.8-micron CMOS process is modified by implanting arsenic or phosphorus during epitaxy in a p-type substrate starting material to increase the depth of selected n-well areas for the purpose of producing high-voltage transistors on the same substrate in the same CMOS process. Implanting boron in a p-field extension area in a manner which minimizes the dopant in the adjacent field oxide achieves a similar result. That is, breakdown and punch-through voltages are increased. Together, these make CMOS transistors which operate at a higher voltage range than either innovation alone.
Metadata
Assignee
- National Semiconductor Corporation
Inventors
- Husam Gaffur
- Sukyoon Yoon
Application Information
Application Number:US 4291824
Filing Date:1995-04-26
Priority Date:1994-02-15
Art Unit:253
Classifications
IPC:
H01L 2976H01L 21265
Field of Search:
257437371;375;376;40827;40;56;62;228
Patent Drawings (2 sheets)
Description
Background of the Invention
1. Field of the Invention
The present invention relates to an apparatus of high-voltage (over 6 volts) transistors and diodes on the same substrate and made in the same process as ordinary 5-volt CMOS (Complementary Metal Oxide Semiconductor) circuits and to a process for making the apparatus. More particularly, but not by way of limitation, the present invention allows logic circuitry to be fabricated in existing CMOS processes, while allowing interfacing to high-voltage circuits on the same silicon substrate.
2. Discussion
High-voltage capability has important applications in consumer electronics, automotive and other markets where many existing devices such as motors, transducers and actuators operate on high voltages. The present invention allows the logic circuitry to operate on power-saving low voltage while allowing the entire device to be fabricated on a single silicon chip in an otherwise conventional CMOS process. For the purpose of this discussion, low voltage is a voltage of 6 volts and less, while high voltage is a voltage of over 6 volts.
Conventional CMOS logic integrated circuits (hereinafter CMOS chips) operate between 2.4 and 5 volts. The range of power supply voltages at which the chip can operate is known as the operating voltage range. Typically a given chip can simply be powered with any power supply selected between 1.2 and 5 volts and the logic will operate with a logic low of 0 volts and logic high of the selected power supply voltage. Typically for battery-operated devices and other devices where a minimum of power consumption is desirable, the lowest possible voltage is used. Although the use of this low voltage minimizes the power consumed, existing physical devices such as motors, transducers, and actuators operate advantageously at higher voltages. Moreover, the trend is toward CMOS chips that operate at even lower voltages while these other components stay at their fixed voltages, and may even operate more efficiently at higher voltages.
The areas in which high-voltage CMOS chips will be useful are numerous. Applications in LCD active matrix technology, linear amplifiers, voltage translators, switching regulators, computer interfaces including the ubiquitous RS-232 interface and in computer disk drive read/write circuits are in need of this innovation. Numerous other applications will suggest themselves when the device becomes commercially available and thereby well-known. In short, any application which involves operating voltages outside of the presently limited range will benefit from the device. Moreover, as the geometry of the CMOS chips continues to shrink in size, the operating voltage range will be in even lower voltages which will greatly increase the need for the present invention.
As an example, an automobile may have a microprocessor controller that drives a 12-volt motor. For the purpose of this example, assume the motor does a particular physical task and therefore requires the same power output of 120 Watts, regardless of supply voltage. If the motor draws 10 Amperes of current through connections that through age and neglect have a resistance of 0.1 ohms, the power consumed in these connections is 10 Watts. On a 24-volt system, a motor of the same locomotive power would draw only 5 Amperes, dissipating only 2.5 Watts as heat. Similarly on a 6-volt system, the power dissipated as heat would be 40 Watts, a substantial fraction of the motor's power of 120 Watts. The ratio of power wasted to power consumed for the 6, 12, and 24-volt systems is respectively, 33%, 8%, and 2%. This illustrates how a widely used system, the electrical system of automobiles, is unlikely to go to any lower voltage because of increasing inefficiency in the system as the voltage is decreased.
CMOS chips, on the other hand, have become more efficient at lower voltages. The 4000B series CMOS operates between 5 and 15 volts and has been widely used for over twenty years. However, it accomplishes its high-voltage range by using much larger transistors than are used in current CMOS submicron geometries. As device size was reduced and new CMOS series introduced, the operating voltage range dropped until today, as an example, the 4-bit National Semiconductor COP424C CMOS microcontroller draws 3.5 milliwatts when operated at 5 volts, but only 0.29 milliwatts at 2.4 volts. Unfortunately for the car manufacturers, the upper limit of the supply voltage for this microcontroller is only 6 volts. Moreover, as modern fabrication techniques reduced device size, the typical maximum operating voltage has decreased. Using a 6-volt controller on a 12-volt system presently requires surrounding the chip with various external interface transistors at additional cost.
The additional transistors, required for the purpose of interfacing to the high voltage circuitry, became necessary as the same CMOS device miniaturization that decreased voltage and power requirements also decreased the depth of the semiconductor wells thereby decreasing the punch-through and breakdown voltages, giving rise to the lowered maximum operating voltages. The punch-through voltage of a CMOS gate is the voltage applied across the source and drain which, in and of itself and without regard to the voltage on the gate, causes significant current flow through the source and drain. Because the current flows without regard for the voltage on the gate of the device, the device is no longer functional. Moreover, the power dissipated by the device in such a condition typically destroys the device. The punch-through voltage is therefore the measure of how great a voltage can be switched by a given transistor. The breakdown voltage is analogously defined as the voltage between the gate and drain or between the gate and source which causes significant current flow through the gate. Insomuch as a CMOS transistor has an insulated gate, this too represents a breakdown of the transistor's function.
In a diode, which has only one junction, only the breakdown voltage is defined. The breakdown voltage is the voltage which reverse-biases the diode and causes significant current to flow through the diode. Unless the current is limited by external means, catastrophic overheating and subsequent destruction of the diode occurs. Because the diode has only one junction, punch-through voltage is not defined for the diode. Consequently, throughout this application, where the term punch-through occurs, the term is understood as applying only to transistors and its application to diodes is a nullity.
The punch-through and breakdown voltages in an integrated circuit are functions of the physical three-dimensional geometry of the circuit. If the resultant electric field within a device exceeds certain bounds, catastrophic electrical breakdown occurs based on the electric field and the device geometry. The geometry is controlled by the extent to and rate at which various dopants diffuse into a given substrate. Such dopants include boron, phosphorus, and arsenic.
The relative diffusion rates of the various dopants are important factors in determining the final device geometry. Different dopants diffuse at different rates and because diffusability is a steep function of temperature, the depth of diffusion is not a linear function of the time for which and temperature to which the wafer is heated. Because of this nonlinearity, heating the wafer twice for the same cumulative time does not produce the same depth of diffusion as heating the wafer once. Therefore, although the various thermal cycle times are stated and are in fact done to accomplish a particular task, the effect on the diffusion of the dopant is also a key issue in the ultimate placement of the doped regions. Consequently, final device geometry depends to a large extent on the overall sequence of events comprising the manufacture of the chip.
A need exists for, and the present invention is directed toward, a process that overcomes these shortcomings of the current CMOS apparatus of the conventional low voltage CMOS process and allows high-voltage devices to be fabricated on existing low-voltage submicron CMOS production lines.
Summary of the Invention
In the present invention, a low-voltage 0.8-micron CMOS process is modified by implanting a selected dopant during epitaxy in a p-type substrate starting material to increase the depth of selected n-well areas for the purpose of producing high-voltage transistors on the same substrate in the same CMOS process.
The present invention is accomplished by growing an epitaxial layer on a selected substrate, and implanting a dopant type into the epitaxial layer at a selected time during growth of the epitaxial layer to produce an implant zone to increase the breakdown and punch-through voltages. Next, a negatively doped n-well region is produced within the epitaxial layer, and a layer of field oxide is grown at selected sites on the epitaxial layer. The next step is implanting source and drain regions within the n-well region with such regions separated by the field oxide for electrical insulation. Finally, a polysilicon gate is deposited between the source and drain regions.
In one embodiment of the present invention, the dopant type is arsenic which is implanted after completion of about 90 percent of the epitaxial layer. In another embodiment, the dopant type is phosphorus which is implanted after, or near, the completion of the growth of the epitaxial layer.
An object of the present invention is to provide high-voltage CMOS transistors and diodes on the same substrate and manufactured in the same process as low-voltage CMOS transistors.
Another object of the present invention is to eliminate at the circuit board level, extra interface integrated circuits (ICs) by providing for translation to high-voltage on a low-voltage CMOS IC.
Yet another object of the present invention is to enable the high-voltage transistors needed to interface with liquid crystal and other displays and line drivers for RS-232 and other interface to be manufactured in the same process and in the same substrate as low-voltage CMOS transistors.
Another object is to provide such advantages in other interface circuits such as those found in disc drives.
Other objects, features and advantages of the present invention will become apparent from the following detailed description when read together with the drawings and appended claims.
Brief Description of Drawings
FIG. 1 depicts a transistor made according to the present invention.
FIG. 2 is an arsenic implant in an epitaxial layer.
FIG. 3 shows exposed twin well pad oxide before removal of photoresist.
FIG. 4 depicts a step of local oxidation of silicon wherein boron is implanted.
FIG. 5 depicts the completion of local oxidation of silicon after the boron implant is made.
Detailed Description
Referring now to the drawings and more particularly to FIG. 1, shown therein is a cross-section of a high voltage PMOS transistor 10 manufactured from a low-voltage CMOS process modified in accordance with the present invention.
As with conventional CMOS transistors, the transistor 10 shown in FIG. 1 contains an n-well 16 supporting a source region 30, a drain region 32, a polysilicon gate 34, and field oxide regions 20, 22, 24 and 26. Metallized contact 36 provides electrical access to an n-well contact region 28 and metallized contacts 38 and 40 provide access to the source and drain regions 30, 32 respectively. As can also be seen in FIG. 1, transistors selected to possess the aforementioned high voltage characteristics are additionally provided with a buried layer 12 in a first epitaxial layer 14 over a substrate 11. The buried layer 12 comprises a heavily doped n+ region which is juxtaposed below the n-well 16 which is located in a second epitaxial layer 15 above the first epitaxial layer 14. Additionally, a p-field extension region 18 is provided within the n-well 16 below the drain region 32.
The buried layer 12 and the p-field extension region 18 each operate separately and independently to raise the breakdown and punch-through voltage thresholds of the transistor 10 which increases the operating voltage range of the transistor 10. The buried layer 12 serves to provide an improved conduction path for current to flow between the source region 30 and the drain region 32 during operation of the device. The p-field extension region 18 effectively improves the cross-sectional area of a conductive path between the source and drain regions 30,32, reducing constraints upon an electric field generated during operation of the device in the region adjacent to the drain region 32. Further, the combined operation of the buried layer 12 and the p-field extension region 18 significantly increase the breakdown and punch-through voltage threshold of the transistor 10 over and above the increase achieved by either the buried layer 12 or the p-field extension region 18 alone.
The high voltage PMOS transistor 10 may be fabricated using the method described below in conjunction with FIGS. 2-5. Referring to FIG. 2, shown therein is a p-type substrate 11 having a crystallographic orientation of <100> and on which is grown the aforementioned first epitaxial layer 14, which comprises a layer of silicon about 22 .mu.m in thickness grown or deposited expitaxially on the substrate 11. The first epitaxial layer 14 is provided with a thin layer of oxide 46 which is formed over the epitaxial layer 14 during the epitaxial process and has a thickness of about 120 .ANG.. A mask 48 is applied to the layer of oxide 46, exposing those locations where the high voltage transistors 10 are to be formed and enabling the implanting of an n-type impurity into the epitaxial layer 14 to form the buried layer 12. In the preferred embodiment, arsenic is implanted at this step in the process at an energy of 160 KeV and driven in at 1000 degrees Celsius for about 21 minutes, resulting in a concentration of 10.sup.13 to 10.sup.14 atoms/cm.sup.2 in the buried layer 12. It should be noted, however, that concentrations above this range may also yield desirable results.
Referring to FIG. 3, the mask 48 and the layer of oxide 46 are removed and a second epitaxial layer 15 is subsequently grown or deposited over the first epitaxial layer 14. This second epitaxial layer 15 is grown or deposited until it achieves a thickness of about 1.8 .mu.m, after which a pad oxide 50 is grown over the second epitaxial layer 15, the pad oxide 50 having a thickness of about 450 .ANG..
It should be noted that in an alternative embodiment, phosphorus may be used instead of arsenic as the n-type impurity for the above described buried layer 12. In such a case, the buried layer 12 is not formed until after the second epitaxial layer 15 and the pad oxide 50 have been completed. The alternative phosphorus buried layer process steps comprise masking the pad oxide 50, implanting phosphorus at an energy of from 140 KeV to 200 KeV and driving in at an elevated temperature for about 11 hours to achieve a resulting concentration of about 10.sup.16 to 10.sup.17 atoms/cm.sup.2 in the first epitaxial layer 14. The remaining process steps are the same whether arsenic or phosphorus is used in forming the buried layer 12.
A layer of silicon nitride 52 is deposited on the pad oxide 50 to a depth of about 1350 .ANG. and photoresist 54 is then applied to expose the layer of silicon nitride 52 over locations that will subsequently become n-wells 16. The exposed portions of the layer of silicon nitride 52 are removed using a suitable etchant process and phosphorus having an energy of 140 KeV is implanted to achieve a concentration of about 4.5.times.10.sup.12 atoms/cm.sup.2 to form the n-well 16. FIG. 3 depicts the relevant part of the silicon wafer at this step in the process.
The photoresist 54 is stripped and the remaining portions of the layer of silicon nitride 52 are used in the local oxidation of silicon (LOCOS), wherein oxide (not shown in FIG. 3) is grown to a depth of about 5000 .ANG. during exposure to 1200 degrees Celsius dry heat. The remaining portions of the layer of silicon nitride 52 are then removed and p-wells 42 are formed in the second epitaxial layer 15 by the implantation of BF.sub.2 at an energy of 150 KeV to achieve a concentration of 2.7.times.10.sup.12 atoms/cm.sup.2.
The oxide is selectively etched back such that oxide with a thickness of about 2400 .ANG. remains over the n-well 16 and oxide with a thickness of about 1850 .ANG. remains over the p-well 42. The n-well 16 and the p-well 42 are then driven in by heating the wafer to 1150 degrees Celsius for sufficient time to increase the depth of the n-well 16 to about 1.8 .mu.m and the depth of the p-well 42 to about 2.0 .mu.m. The difference in these two depths is largely attributable to the differences in the diffusion rates of the respective dopants.
Referring now to FIG. 4, the following additional process steps are performed. 200 .ANG. pad oxide 50, 1850 .ANG. composite nitride 52, and photoresist 52 are formed as follows: the 200 .ANG. of pad oxide 50 and the 1850 .ANG. composite nitride 52 are deposited in the locations shown. A layer of photoresist 54 is spun on and exposed using a mask to achieve the pattern shown in FIG. 4 and the photoresist 54 is developed. Next, the nitride 52 is etched and the photoresist is cleaned, after which the pad oxide 50 etched and about 3250.ANG. of field oxide 56 is grown. Another layer of photoresist 54 is spun on and exposed to provide p-field extension mask through which BF.sub.2 is implanted at an energy of 140 KeV to achieve a concentration of 5.5.times.10.sup.13 atoms/cm.sup.2. The photoresist 54 is removed and additional field oxide is grown to achieve a thickness of about 6500.ANG., which is shown as field oxide 56 A in FIG. 5.
The remaining steps in the process required to complete the transistor 10, as shown in FIG. 1, are similar to those used in conventional CMOS technology. The composite nitride 52 and the composite oxide 50 are removed and a 200 .ANG. gate oxidation and a voltage threshold implant are performed. The polysilicon gate 34, as shown in FIG. 1, is formed by depositing 4000 .ANG. of polysilicon. Resist is then spun on the front side of the wafer and the polysilicon is etched in a plasma process and the backside oxide is removed by a buffered etchant. The polysilicon is doped by phosphorus to a concentration of about 10.sup.20 to 10.sup.21 atoms/cm.sup.2, deglazed, and etched by conventional processes, resulting in the gate 34 shown in FIG. 1. Seal oxidation to seal the poly at the sides and to protect the surface of the silicon is then formed with a thickness of 80 .ANG. by exposing the wafer to 900 degrees Celsius dry heat for about 50 minutes.
The n-well contact region 28 (an n+ diffusion area) is formed, followed by the source and drain regions 30,32 (which are p+ diffusion areas). A drain contact (not particularly shown) is formed using conventional LDD techniques and a LDD blocking mask (not shown), allowing the implanting of phosphorus at an energy of 50 KeV to a dose of 2.3.times.10.sup.13 atoms/cm.sup.2. At this point the ohmic contact has an n-doping. Next, 2000 .ANG. spacers are formed by oxidation of the silicon. The spacers are then etched back for the purpose of completing the LDD. The n+ blocking mask is then used to expose only n+ ohmic contact to arsenic ions implanted at an energy of 40 KeV to a concentration of 3.0.times.10.sup.15 atoms/cm.sup.2. The resist is removed and poly oxidation (not shown) is performed to a depth of 150 .ANG.. Another mask is used to expose the two areas that become the source and drain regions 30 and 32 which are doped with BF.sub.2 at an energy of 45 KeV to a dose of 4.5.times.10.sup.15 atoms/cm.sup.2, after which the resist is removed.
The next major step in the process is dielectric deposition. First, 500 .ANG. of undoped plasma oxide is deposited, then BPSG is deposited to a depth of 6000 .ANG.. The BPSG is reflowed by reheating to a temperature of 900 degrees Celsius for a time suitable to achieve the desired profile. Cap deposition is formed by oxidizing to a depth of 2000 .ANG..
The final step in the process is to form the metallic contacts 36, 38 and 40. Contact cuts are made using the contact mask, followed by a layer of titanium being deposited to a depth of 1000 .ANG.. Titanium nitride is formed to a depth of about 150 .ANG. and titanium silicide is formed to a thickness of 300 .ANG.. Tungsten is then deposited to a depth of 7500 .ANG.. The combination of these metal layers is then masked and etched to form the metallic contacts 36, 38 and 40, completing the formation of the silicon structure as shown in FIG. 1.
Having concluded a description of the method of the present invention, it is important to note that in addition to the formation of a high voltage transistor 10 as hereinabove described, a high voltage diode may also be formed and used in the manner provided by using the metallic contact 40, as shown in FIG. 1, as an anode connection and the metallic contact 36 as a cathode connection. The operation of the buried layer 12 and the p-field extension region 18 serve to increase the operating voltage range of such a diode in the same manner as for the transistor 10.
The above description makes clear that the present invention is well adapted to carry out the objects and to attain the ends and advantages mentioned herein as well as those inherent in the invention. While presently preferred embodiments of the invention have been described for purposes of this disclosure, it should be understood that numerous changes may be made which will readily suggest themselves to those skilled in the art and which are encompassed within the spirit of the invention disclosed and as defined in the appended claims.
Claims
What is claimed is:
1. A method for forming a high voltage CMOS device, comprising: providing a p-type substrate; forming a lightly doped p-type first epitaxial layer on the p-type substrate; implanting an n-type impurity to form a heavily doped n+ buried layer within the first epitaxial layer; forming a lightly doped p-type second epitaxial layer over the first epitaxial layer; implanting an n-type impurity to form a lightly doped n-well in the second epitaxial layer; and implanting a p-type impurity to form a p-field extension region in the n-well.
2. The method of claim 1, wherein the step of implanting an n-type impurity to form a heavily doped n+ buried layer further comprises the step of implanting arsenic at an energy of about 160 KeV to achieve a concentration of about 10.sup.13 to 10.sup.14 atoms/cm.sup.2 in the buried layer.
3. The method of claim 1, wherein the step of implanting an n-type impurity to form a heavily doped n+ buried layer further comprises the step of implanting phosphorus at an energy of about 140 to 200 KeV to achieve a concentration of about 10.sup.16 to 10.sup.17 atoms/cm.sup.2 in the buried layer.
4. The method of claim 1, wherein the first epitaxial layer has a thickness of about 22 .mu.m and the second epitaxial layer has a thickness of about 1.8 .mu.m.
5. The method of claim 2, further comprising the steps of: forming a thin layer of oxide over the first epitaxial layer; selectively masking the thin layer of oxide so a selected portion of the oxide defining the heavily doped n+ buried layer is exposed; implanting the arsenic through the selected portion of the oxide to form the heavily doped n+ buried layer in the first epitaxial layer; removing the mask and the layer of oxide; forming the second epitaxial layer and a first pad oxide on the second epitaxial layer; forming a layer of silicon nitride over the first pad oxide; selectively removing the layer of silicon nitride in a selected site defining the n-well; implanting phosphorus to form the n-well, the phosphorus having an energy of about 140 KeV and provided at a sufficient dosage to achieve a concentration of about 4.5.times.10.sup.12 atoms/cm.sup.2 ; forming oxide using LOCOS; removing the layer of silicon nitride; etching back the oxide and driving in the n-well by heating to 1150 degrees celsius to drive in the phosphorus to increase the depth of the n-well to substantially the depth of the second epitaxial layer; forming a second pad oxide, a composite nitride, and a mask to expose a selected site defining a p-field extension region within the n-well; and implanting BF.sub.2 to form the p-field extension region, the BF.sub.2 provided with an energy of about 140 KeV to achieve a concentration of about 5.5.times.10.sup.13 atoms/cm.sup.2.
6. A method for providing a CMOS device having an increased operating voltage range and increased breakdown and punch-through voltage thresholds, the method comprising: forming a lightly doped p-type first epitaxial layer over a selected surface of a p-type substrate; implanting arsenic into the first epitaxial layer to produce a heavily doped N+ buried layer within the first epitaxial layer; forming a lightly doped p-type second epitaxial layer over the first epitaxial layer and over the buried layer therein; implanting phosphorus in a selected region of the second epitaxial layer to form an n-well region within the second epitaxial layer and above the buried layer in the first epitaxial layer; forming a field oxide layer at selected sites over the second epitaxial layer and the n-well region therein; and implanting BF.sub.2 at selected sites within the n-well to form a source region and a drain region; forming a polysilicon gate over the n-well region and between the source region and the drain region; implanting BF.sub.2 to form a p-field extension region surrounding the drain region so that diffusion of the BF.sub.2 beyond the p-field extension region is minimized to increase the breakdown and punch-through voltage thresholds.
7. The method of claim 6, wherein the arsenic is implanted an energy of about 160 KeV to achieve a concentration of about 10.sup.13 to 10.sup.14 atoms/cm.sup.2 in the buried layer.
8. The method of claim 6, wherein the phosphorus is implanted at an energy of about 140 to 200 KeV to achieve a concentration of about 10.sup.16 to 10.sup.17 atoms/cm.sup.2 in the buried layer.
9. The method of claim 6, wherein the BF.sub.2 is implanted at an energy of about 140 KeV to achieve a concentration of about 5.5.times.10.sup.13 atoms/cm.sup.2.
10. A CMOS device having an increased operating voltage range, comprising: a p-type substrate having a surface; a lightly doped p-type first epitaxial layer on the surface; a lightly doped p-type second epitaxial layer on the first epitaxial layer; an n-well within the second epitaxial layer; a source region within the n-well; a drain region within the n-well; conduction means, within the first epitaxial layer, for increasing capacity for current to pass between the source region and the drain region during operation of the device; and extension means, within the second epitaxial layer, for reducing constraints upon an electric field surrounding the drain region generated during operation of the device to increase breakdown and punch-through voltage thresholds of the device.
11. The CMOS device of claim 10, wherein the conduction means comprises a heavily doped n+ buried layer within the first epitaxial layer, the buried layer formed from implanted arsenic at an energy of about 160 KeV to achieve a concentration of about 10.sup.13 to 10.sup.14 atoms/cm.sup.2 in the buried layer.
12. The CMOS device of claim 10, wherein the conduction means comprises a heavily doped n+ buried layer within the first epitaxial layer, the buried layer formed from implanted phosphorus at an energy of about 140 to 200 KeV to achieve a concentration of about 10.sup.16 to 10.sup.17 atoms/cm.sup.2 in the buried layer.
13. The CMOS device of claim 10, wherein the extension means comprises a p-field extension region formed from implanted BF.sub.2 at an energy of about 140 KeV to achieve a concentration of about 5.5.times.10.sup.13 atoms/cm.sup.2.
14. A CMOS device having an increased operating voltage range, comprising: a p-type substrate; a first epitaxial layer on the p-type substrate, the first epitaxial layer comprising lightly doped p-type material; a buried layer within the first epitaxial layer, the buried layer comprising an n-type impurity at a sufficient concentration to provide a heavily doped n+ region; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer comprising lightly doped p-type material and further including: an n-well having a drain region; and a p-field extension region surrounding the drain region.
15. The CMOS device of claim 14, wherein the buried layer comprises arsenic implanted at an energy of about 160 KeV to achieve a concentration of about 10.sup.13 to 10.sup.14 atoms/cm.sup.2.
16. The CMOS device of claim 14, wherein the buried layer comprises phosphorus implanted at an energy of about 140 to 200 KeV to achieve a concentration of about 10.sup.16 to 10.sup.17 atoms/cm.sup.2.
17. The CMOS device of claim 14, wherein the p-field extension region comprises BF.sub.2 implanted at an energy of about 140 KeV to achieve a concentration of about 5.5.times.10.sup.13 atoms/cm.sup.2.
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