Digital Absolute Position Encoders

This invention relates generally to digital absolute position encoders, and more particularly to encoders of such type which are adapted to provide a "unit-distance", cyclic code, such as a Gray code.

As is known in the art, it is frequently desired to determine the position of one member with respect to a second member. One way to obtain such relative position is to place a code on one of the members and a detector on the other member. One such arrangement is described in an article entitled "Absolute Encoders Provide Precise Position Information" by Gregg Stokely published in the April 1994 issue of PCIM on pages 40-49. As described therein, if system needs are to measure travel of a screw, for example, in 0,001-inch increments over 25 inches, then a linear encoder of 25,000 words is required. Likewise, with an angle encoder, if angles over 360 degrees are to be measured to 0.1 degrees, then 3600 words are required. Thus, in the general case, if a span to be measured is L, and such span, L, is to be measured to within a resolution cell, C, the number of words to be encoded is L/C. With digital encoders, the words are typically binary word signals having n bits. Thus, the number of binary word signals is typically 2.sup.n, where n is an integer, and the resolution cell, C, is L/2.sup.n.

As described in the above referenced article, each position, or resolution cell, on one of the members is identified by a unique digital code, or binary word. No two positions have the same binary word so that the exact position of one member relative to the other member is always known. This feature of an absolute encoder, as distinguished from an incremental encoder, is important in those cases where power is turned off and there is relative motion during the time such power is off. With an absolute position encoder, the exact position of one member relative to the other is always precisely determined once power to the system is reapplied, even if the relative position of the members had changed when the power was off. True position is always available from the absolute encoder without the need to continuously monitor the encoder as in the case of an incremental encoder. This unique capability makes absolute encoders the preferred sensor for applications that require a true indication of position at all times due to machine or operator safety concerns or where the system cannot be easily returned to a reference or home position for "zeroing".

Conventional digital position encoders employ optical sensors to detect a pattern of binary indicia; typically opaque and transparent segments on multiple tracks. These segments or indicia, can be holes in a material or a photographically painted set of lines on glass or plastic. It is common to use a natural binary code or a Gray code pattern, as described in the above referenced article. The natural binary and Gray code pattern each require "n" tracks and "n" sensors to resolve the 2.sup.n unique binary word signals. That is, at each position, or cell, a unique one of the 2.sup.n binary word signals is encoded; each bit of the n bits of each word signal being encoded as a binary indicium on a corresponding one of the n tracks. A natural binary code assigns the power of 2 to the code tracks. For example, the least significant bit track represents 2.sup.0 while the most significant bit track represents 2.sup.n. One well-documented problem with this natural binary code is that at certain transitions from one word signal to the next, many bits of the word signal change logic states. One example is the transition from (7).sub.10 (i.e., (0111).sub.2) to (8).sub.10 (i.e., (1000).sub.2), where the subscript 10 indicates base 10 and the subscript 2 indicates base 2. Note, in this example, all bits change logic state. This can be problematic if sampling data since there can be a skew between transitions of each bit, and a sample could be taken in the midst of the change. The Gray code pattern has the important property that only one bit changes from one word signal to the next. A code that exhibits this property is sometimes referred to as "unit-distance code", and the use of this type of code will generally ensure that a sampled system will have an ambiguity of, at most, one least significant bit. Further, a code which only has one bit change when going from the end of the span to the beginning of the span is sometimes referred to as a "cyclic" code. Such code is useful with a closed geometric span, such as a circle. The Gray code is a "unit-distance", "cyclic" code.

In accordance with the present invention, a digital absolute encoder is provided for determining absolute position of a first member with respect to a second member. The absolute position is determined within a cell resolution of L/2.sup.n, where n is an integer and L is a predetermined span. One of the members has a plurality of, m, tracks of binary indicia distributed over the predetermined span, L, where m is an integer less than n. The other member has a plurality of binary indicia detectors for detecting the binary, or logic, state of the binary indicia.

With such an arrangement, an encoder is provided having a "cyclic", "unit-distance code", yet uses fewer tracks than that used with the above-described Gray code. Further, this encoder has a reduced number of transitions than that required on the track used with the above described Gray code. Both of these features simplify the design and fabrication for a given encoder resolution.

In accordance with another feature of the invention, an encoder is provided for determining absolute position of a first member with respect to a second member, such absolute position being determined to within a resolution of L/2.sup.n where n is an integer and L is a predetermined span The span may be a linear span, arcuate, circular, or other curved span. The encoder has a plurality of, m, tracks of binary state indicia disposed in a predetermined pattern on, and distributed over, the predetermined span, L, of the first member, where m is an integer less than n. The second member has disposed thereon a plurality of binary state detectors. The detectors are disposed on, and at predetermined positions of, the second member. The detectors are adapted to detect a portion of the binary state indicia in predetermined orientation with such detectors. Circuitry is provided to convert the logic states of the portion of the binary state indicia in predetermined orientation with the detectors into a corresponding one of 2.sup.n numbers to indicate the relative position of the members.

In accordance with another feature of the invention, an encoder is provided having a first encoder section for determining the main portion of the position of a first member with respect to a second member and a second encoder for determining a vernier portion of such position.

In accordance with still another feature of the invention, an encoder is provided having a plurality of tracks of binary state indicia disposed in a predetermined pattern on, and distributed over, the first member. The second member is adapted to move relative to the first member has disposed thereon a plurality of sets of binary state detectors. Each set of detectors is adapted to detect the binary state indicia of a corresponding one of the tracks of binary indicia. A bearing is provided to enable relative movement between the first and second members. One portion of the tracks and the set of detectors corresponding thereto is disposed on one side of the bearing and another portion of the tracks and the set of detectors corresponding thereto is disposed on another side of the bearing with the one portion of the tracks and the set of detectors corresponding thereto separated from the another portion of the tracks and the set of detectors corresponding thereto by a surface parallel to the path of relative movement between the first and second members and perpendicular to the plane of the tracks.

Other features, objects and advantages will become apparent from the following detailed description when read in connection with the drawing, in which:

FIG. 1 is an exploded isometric drawing of an encoder according to the invention;

FIG. 2 is a diagrammatical sketch showing the relationship of a binary indicia code used on one member of the encoder of FIG. 1 and detectors used on another partially cutaway member at one relative position of the members;

FIG. 2A is a diagrammatical sketch of another embodiment of an encoder according to the invention;

FIGS. 3A and 3B, together, in the arrangement shown in FIG. 3, is a truth table for the encoder of FIG. 1;

FIGS. 4A, 4B, and 4C, together illustrate the difference between encoder in accordance with the prior art, as shown in FIGS. 4A and 4B; and, an encoder according to the invention, as shown in FIG. 4C;

FIG. 5 is a diagrammatical sketch showing an encoder according to the invention; FIG. 5A being an enlarged portion of FIG. 5, such enlarged portion being enclosed by a circular arrow indicated by 5A--5A;

FIG. 6 is a block diagram of a processor used with the encoder of FIG. 5;

FIG. 7 is a contracted plan view of an encoder according to the invention;

FIG. 8A through FIG. ST, together, in the arrangement shown in FIG. 8, is a truth table for the encoder of FIG. 7; and

FIG. 9 is a cross-sectional view of a linear actuator having the encoder of FIG. 7.

Referring now to FIGS. 1 and 2, an encoder 10 is shown for determining absolute position of a first member 12 with respect to a second member 14. The absolute position is determined to within a resolution cell of L/2.sup.n, where n is an integer and L is a predetermined span, here a linear length. It should be understood, however, that the span may be a circular or arcuate span, in which case L would be in angular measure.

The first member 12 of the encoder 10 has a plurality of, m, (here m=2) tracks 16, 18 of binary state indicia 20.sub.1 -20.sub.44, and 22.sub.1 -22.sub.44, respectively, disposed in a predetermined pattern on the first member 12. Here, the binary indicia 20.sub.1 -20.sub.16 of track 16 represents logical 0 state, binary indicia 20.sub.17 -20.sub.32 of such track 16 represent a logical 1 state, and binary indicia 20.sub.33 -20.sub.44 represent a logical 0 state. (It should be noted that the binary indicia which represent the logical i state have been indicated in the drawing with an "x" for convenience in understanding the invention, i.e., for ease in reading; it being understood that the "x" does not actually appear on the encoder). Here, binary indicia 22.sub.1 -22.sub.4, 22.sub.9 -22.sub.12, 22.sub.17 -22.sub.20, 22.sub.25 -22.sub.28, 22.sub.33 -22.sub.36, 22.sub.41 -22.sub.44 of track 18 represent a logical 0 state, and binary indicia 22.sub.5 -22.sub.8, 22.sub.13 -22.sub.16, 22.sub.21 -22.sub.24, 22.sub.29 -22.sub.32, 22.sub.37 -22.sub.40 of such track 18 represent a logical 1 state.

The binary indicia 20.sub.1 -20.sub.32, and 22.sub.1 -22.sub.32 are distributed over the predetermined span, L, of, the first member 12. Here the length L is divided into 32 segments, or resolution cells. Thus, here n is equal to 5 (i.e ,2.sup.5 =32) and 32 different positions are detectable; here, position 0 to position 31. If a natural binary or Gray code were used as described above, the number of tracks, m, would be equal to n. That is, the first member 12 would have 5 tracks. Here, however, m is an integer less than n. Thus, here the encoder 10 may be smaller in size than the above described natural or Gray code encoders.

The second member 14 has disposed thereon a plurality of, m, (here 2) sets 23, 25 of binary state detectors 24.sub.1 -24.sub.4, 26.sub.1 -26.sub.3, respectively, as shown. Each one of the sets 23, 25 of detectors 24.sub.1 -24.sub.4, 26.sub.1 -26.sub.3 being adapted to detect the binary indicia in a corresponding one of the m tracks, 16, 18, respectively, as shown. Thus, here the first set 23 of detectors 24.sub.1 -24.sub.4 is disposed in vertical alignment, or registration with, track 16, and the second set 25 of detectors 26.sub.1 -26.sub.3 is disposed in vertical alignment, or registration with, track 18. The detectors 24.sub.1 -24.sub.4, 26.sub.1 -2.sub.3 are disposed on the second member 14 at predetermined positions thereof to detect a portion of the binary state indicia in predetermined orientation with such detectors. Thus, here the first and second members 12, 14 are disposed in the X-Y plane, displaced from one another by a suitable distance along the Z-axis by a suitable bearing, not shown, and are adapted for relative movement along the Y axis by means of such bearing, not shown. When the first and second members 12, 14 are in the position shown in FIG. 1, detectors 24.sub.4 -24.sub.1 and 26.sub.3 -26.sub.1 are disposed over, i.e., in vertical registration with, binary indicia 20.sub.19, 20.sub.23, 20.sub.27, 20.sub.31, 22.sub.20, 22.sub.21, 22.sub.22, as shown. It should also be noted that both sets 23, 25 of binary state detectors 24.sub.1 -24.sub.4, 26.sub.1 -26.sub.3 include more than one detector disposed for detecting the binary indicia in each one of the tracks 16, 18. Further, the pattern of binary indicia of the first one of the m tracks, here track 16, comprises a set of consecutive binary indicia, here binary indicia 20.sub. -2016, represent a first logic state, here logical state 0. A succeeding, second set of binary indicia, here binary indicia 20.sub.17 -20.sub.32, represent the complement of the first logic state, i.e., binary indicia 20.sub.17 -20.sub.32 represent the logic state 1. The pattern of binary indicia of a second one of the m tracks, here track 18, comprises a first set of consecutive binary indicia, here binary indicia 22.sub.1 -22.sub.4, representing a first logic state, here logical state 0; a succeeding, second set, here binary indicia 22.sub.5 -22.sub.8, representing the complementary logical state, here logical state 1; a succeeding, third set, here binary indicia 22.sub.9 -22.sub.12, representing the first logic state, here logical state 0; and so forth along the track 18. The first and third sets of the binary indicia 22.sub.1 -22.sub.4 and 22.sub.9 -22.sub.12, respectively, of the second track 18 have a center-to-center separation of s resolution cells, here four cells. The detectors 24.sub.1 -24.sub.4 used to detect the binary states of binary indicia of the first track 16 also have a separation of s cells, here four cells. The detectors 26.sub.1 -26.sub.3 used to detect the binary indicia in the second track 18 are adjacent one another (i.e., have a center-to-center separation of one resolution cell) and are therefore disposed for detecting adjacent ones of the binary indicia in the second track 18. Alternatively, they may be separated by the absolute magnitude of ps-1, where p is an even integer. (Here, 0 is considered an even integer.) Thus, for example while FIG. 2 shows an encoder 10 in position 0 with the detectors 26.sub.1 -26.sub.3 contiguous one another, i.e., p=0 and the detectors 26.sub.1 -26.sub.3 have a center-to-center separation of 1 resolution cell. In position 0, detectors 26.sub.1, 26.sub.2, and 22.sub.3 are disposed over binary indicia 22.sub.4, 22.sub.3, and 22.sub.2, respectively, as shown. FIG. 2A shows an encoder where the center-to-center separation between detectors 26'.sub.1 -26'.sub.3 is seven resolution cells; i.e., p=2 (ps-1=7, where as noted above s=4). In such case, tracks 16 and 18 are extended by five binary indicia 20.sub.45 -20.sub.49, 22.sub.45 -22.sub.49, respectively, as shown in FIG. 2A. Binary indicia 22.sub.33 -22.sub.36, and binary indicia 22.sub.41 -22.sub.44, represent a logical 0, binary indicia 22.sub.37 -22.sub.40 represent a logical 1 state. Added binary indicia 2245-2248 represent a logical 1 state and binary indicia 20.sub.45 -20.sub.49, 22.sub.49 represent a logical 0 state. Also, in position 0 shown in FIG. 2A detector 26'.sub.1 is disposed over binary indicia 22.sub.4, detector 26'.sub.2 is disposed over binary indicia 22.sub.11 and detector 26'.sub.3 is disposed over binary indicia 22.sub.18, as shown. Alternatively, the center-to-center separation between adjacently ordered (i.e., successively positioned) detectors may be ps+1. In such case, with s=4 and p=2, the detectors 26'.sub.1, 26'.sub.2, 26'.sub.3 are separated by 9 binary indicia; and, in position 0, detectors 26'.sub.1, 26'.sub.2, and 26'.sub.3 are disposed over binary indicia 22.sub.20, 22.sub.11 and 22.sub.2, respectively.

Here, the binary indicia are represented by the magnetic state. The detectors are here conventional Hall effect cells. Thus, with a Hall effect cell, a voltage may be detected when such Hall effect cell detects a representative magnetic state. Binary indicia may be represented by other means representing two distinct states. For example, there may be optical, capacitive, resistive, inductive or other suitable representations. The output signals produced by the detectors 24.sub.1 -24.sub.4, 26.sub.1 -26.sub.3 are fed to a combinational logic section 28. The combinational logic section 28 includes a plurality of logic gates, not shown, to convert the signals produced by the detectors into an n=5 bit binary word signal G.sub.4 G.sub.3 G.sub.2 G.sub.1 G.sub.0 representative of the absolute position of the one of the two members 12, 14 with respect to the other member that is a corresponding one of decimal numbers. That is, here the absolute position of member 12 with respect to member 14 as such members move one relative to the other along the Y axis. More particularly, the combinational logic section 28 here combines the logical signals produced by the detectors 24.sub.1 -24.sub.4, 26.sub.1 -26.sub.3 in accordance with the following equation:

G.sub.0 =A.sym.C

G.sub.1 =B

G.sub.2 =E.sym.G

G.sub.3 =F

G.sub.4 =D

where:

A, B, C, D and E are the logic signals produced by detectors 26.sub.3, 26.sub.2, 26.sub.1, 24.sub.4, 24.sub.3, 24.sub.2, and 24.sub.1, respectively; the binary word signal produced by the combinational logic network 28 is (G.sub.4 G.sub.3 G.sub.2 G.sub.1 G.sub.0)2, where G.sub.0 is the least significant bit of the binary word signal; and

.sym.represents exclusive OR.

For purpose of explanation, it is assumed that the first member 12 is stationary and the second member 14 moves from left to right in FIG. 1, and the vertical alignment between the detectors and the binary indicia is that shown in FIG. 2, for an initial position 0, where the detectors are represented as cross-hatched circles and the binary indicia are represented as squares. That is, here the members 12, 14 are considered as being in the first position or resolution cell (i.e., position 0) of the 32 positions or resolution cells adapted for detection by the encoder 10. The following Table shows the logic signals produced by the detectors 26.sub.3 -26.sub.1, 24.sub.4 -24.sub.1 ("Detector Output Signals") for each of the 32 positions ("Position": 0-31) and the bits of the binary word signal, G4G3G2GiGO, produced by the combinational logic network 28 ("Comb. Log. Out") for each of the 32 positions thereby encoding decimal numbers corresponding to the 32 positions into corresponding binary word signals:

The output binary word signal is a "cyclic", "unit-distance-code", here in Gray code format. The truth table for encoder 10 is shown in FIGS. 3, 3A and 3B. It is first noted that the detectors 26.sub.3,26.sub.2,26.sub.1,24.sub.4,24.sub.3,24.sub.2,24.sub.1 produce a seven bit digital word signals ABCDEFG. It is next noted that only one bit in such word signals ABCDEFG changes from one position to the next position. Further, in going from position 31 to position 0 only one bit changes. Thus, the digital word signals produced by detectors 26.sub.3,26.sub.2,26.sub.1,24.sub.4,24.sub.3,24.sub.2,24.sub.1 is a"cyclic" "unit-distance-code" Further, it should be noted that only n=5 bits are required for the 2.sup.n (i.e. 32) positions and the ABCDEFG digital word signals produced by detectors 26.sub.3,26.sub.2,26.sub.1,24.sub.4,24.sub.3,24.sub.2,24.sub.1 is an 2.sup.n bit digital word signals (i.e., q=7>n=5). Thus, the digital word signal produced by detectors 26.sub.3,26.sub.2,26.sub.1,24.sub.4,24.sub.3,24.sub.2,24.sub.1 is an "excess binary code" a digital word signal, or code, having more than are required for the 32 positions, that is q>n). Finally, it should be noted that the q bit digital word signals, or code, produced by the detectors 26.sub.3,26.sub.2,26.sub.1,24.sub.4,24.sub.3,24.sub.2,24.sub.1 is decoded by the combinational logic section 28 into a n=5 bit Gray code format, as noted above.

Referring now to FIGS. 4A-4C, the difference between 32 position absolute encoders is evident: an absolute position encoder using a conventional, natural binary code according to the prior art is shown in FIG. 4A, such encoder showing 5 detectors ABCDE for producing an n=5 bit digital word signal from m=n=5 tracks of binary indicia disposed in the zero position; an absolute position encoder using a conventional, Gray code according to the prior art is shown in FIG. 4B, such encoder showing 5 detectors ABCDE for producing an n=5 bit digital word signal from m=n=5 tracks of binary indicia disposed in the zero position; and, the absolute position encoder 10 according to the invention is shown in FIG. 4C, such encoder showing 7 detectors ABCDEFG for producing a q=7 bit digital word signal, where q>n from m=2<n=5 tracks of binary indicia disposed in the zero position. It is first noted that each of the three encoders produces, after combinational logic processes signals ABCDE, from the encoders in FIGS. 4A and 4B and the signals ABCDEFG from the encoder in FIG. 4C, the same Gray code signal G.sub.4 G.sub.3 G.sub.2 G.sub.1 G.sub.0 in accordance with the logic equations shown aside the encoder. Finally, it should be noted that the number of tracks according to the invention has been reduced in comparison to the prior art; i.e., from five tracks to two tracks. Next the number of logic transitions has been reduced with the invention; i.e., with the natural binary code (FIG. 4A) detector A experiences a transition at each position and with the Gray code (FIG. 4B), detector A experiences a transition every two positions. With the present invention (FIG. 4C), detectors A, B, or C (i.e., detectors 263, 262, 261 experience a transition only every four positions.

Referring now to FIG. 5, an encoder 10' is shown with a vernier for resolving each one of the 32 main resolution cells into a plurality of sub-cells. Here, each one of the 32 main cells is resolved into 2.sup.11 =2048 sub-cells of resolution. Thus, the first member 12' has, in addition to tracks 16, 18 of binary indicia 20.sub.1 -20.sub.44, and 22.sub.1 -22.sub.44, described above in connection with encoder 10, an additional, third track 60, of binary indicia, as shown. Track 60 includes a series of alternating opaque and transparent binary indicia 60.sub.1 -60.sub.65,536 positioned aside of track 18, as shown, along the predetermined span, L, described above in connection with encoder 10, FIG. 1; that is along the 32 positions to be detected. Thus, binary indicia 60.sub.1, 60.sub.3, 60.sub.5, 60.sub.7, . . . 60.sub.65,535 (i.e., the indicia having an odd numbered subscript notion) are, here, opaque and represent a logical 0; while indicia 60.sub.2, 60.sub.4, 60.sub.6 . . . 60.sub.65,536 (i.e., the indicia having an even numbered subscript notion) are, here, transparent and represent a logical 1. The second member 14', which is disposed above member 12' as shown and described above in connection with FIGS. 1 and 2, has, in addition to detectors 24.sub.1 -24.sub.4 and 26.sub.1 -26.sub.3, a pair of light detectors 65.sub.1, 65.sub.2 disposed above the third track 60 of binary indicia 60.sub.1 -60.sub.65,536 for detecting the logic state of the underlying binary indicia. The encoder 10' is represented in FIG. 5 as being in the zero position, as described above in connection with encoder 10 (FIG. 1). A light source, not shown, is mechanically connected to member 14' and is disposed beneath the binary indicia 60.sub.1 -60.sub.65,536 in a conventional manner so that the detectors 65.sub.1, 65.sub.2 can detect the logic state represented by the binary indicia 60.sub.1 -60.sub.65,536. Referring also to FIG. 5A, in the zero position, detector 65.sub.1 is disposed above the entire lower half of binary indicia 60.sub.1 while the left half of detector 65.sub.2 is above the right half of the upper half of binary indicia 60.sub.1 and the right half of detector 65.sub.2 is disposed above the left half of the upper half of binary indicia 60.sub.2. Thus, the detectors 65.sub.1, 65.sub.2 are disposed in conventional spatial quadrature with the binary indicia 60.sub.1 -60.sub.65,536. Thus, the binary indicia 60.sub.1 -60.sub.65,536 along with the pair of detectors 65.sub.1, 65.sub.2 provide a conventional quadrature incremental encoder 63 (FIG. 6).

The outputs G.sub.0 -G.sub.4 of the combinational logic section 28 are fed, along with the outputs from detectors 65.sub.65 -65.sub.2 to a processor 68. More particularly, the outputs from detectors 65.sub.1, 65.sub.2 are fed to processor 68 via lines 70.sub.1, 70.sub.2, respectively, as shown. Referring also to FIG. 6, the processor 68 is shown to include an absolute position encoder cell transition detector, 75, here an Intel microprocessor, for detecting when one of the absolute position of the main, 32 resolution cells has increased, or decreased by one. That is, the seven bit digital word signal ABCDEFG, described above in connection with FIG. 1, provides an indication of absolute position in one of 32 main positions. When the position of member 12' changes from member 14' by one of the 32 resolution cells, a detection signal is produced by absolute position encoder transition detector 75 on either line 75.sub.1 or 75.sub.2. A signal is produced on line 75.sub.1 when detector 75 detects that the main position has increased from its previous position; and, a signal is produced on line 75.sub.2 when detector 75 indicates that the main position has decreased in position. That is, for example, assume that the detectors 22.sub.1 -22.sub.3, 24.sub.1 -24.sub.4 produce signals ABCDEFG indicating an absolute position of 10. Let it be assumed that member 14' moves, here to the right, so that the detectors 22.sub.1 -22.sub.3, 24.sub.1 -24.sub.4 produce signals ABCDEFG indicating an absolute position of 11. In such case a signal is produced on line 75.sub.1. If, on the other hand, member 14' moved, here to the left, so that the detectors 22.sub.1 -22.sub.3, 24.sub.1 -24.sub.4 produce signals ABCDEFG indicating an absolute position of 9, in such case a signal is produced on line 752. The signal produced on lines 75.sub.1, 75.sub.2 are fed to the "clear" and "set" inputs, respectively, of up-down counter 77'. Here, up-down counter 77' is an eleven bit counter. Thus, up-down counter 77' produces as the contents thereof an eleven bit digital word signal and has 11 output lines, one for each bit of its contents to produce an eleven bit digital word signal B.sub.0 -B.sub.10, where B.sub.0 is the least significant bit (LSB) and B.sub.10 is the most significant bit (MSB). Also fed to the decoder/up-down counter 77 are the signals produced by detectors 65.sub.1, 65.sub.2 via lines 70.sub.1, 70.sub.2, respectively, as shown. As the members 12', 14' move one with respect to the other pulses from detectors 65.sub.1, 65.sub.2 on each of lines 70.sub.1, 70.sub.2 as such detectors pass over the binary indicia 60.sub.1 -60.sub.65,536 in registration therewith. The decoder/up-down counter 77 counts up, or down, the number of pulses produced by the detectors on line 70.sub.1, 70.sub.2. More particularly, when the member 14' moves to the right, as shown in FIG. 5, the signal on line 70.sub.2 from detector 65.sub.2, FIG. 5A, leads the signal on line 70.sub.1, as shown in FIG. 6. In such case, the signal on line 70.sub.1 is a logical 0 when the signal on line 70.sub.2 rises from a logical 0 to a logical 1. Line 70.sub.1 is fed to a non-inverted input of AND gate A and an inverted input of AND gate B. Line 70.sub.2 is fed to an inverted input of AND gate A and a non-inverted input of AND gate B. The output of AND gate A feeds a rising edge triggered monostable multivibrator A and the output of AND gate B feeds a rising edge triggered monostable multivibrator B. Therefore, the monostable B produces a count-up signal to the up-down when the signal on line 70.sub.2 leads the signal on line 70.sub.1 (i.e., the member 14' moves toward the right end of member 12' FIG. and, on the other hand, the monostable A produces a count-down signal to the up-down when the signal on line 70.sub.1 leads the signal on line 70.sub.2 (i.e., the member 14' moves toward the left end of member 12'). Further, when a signal is produced on line 75.sub.1, all 11 bits of the contents in counter 77 are cleared to logical 0; when a signal is produced on line 75.sub.2 all 11 bits of the contents of counter are set to a logical 1.

It follows then, that, when, in the example above, member 14' moves, here to the right from main resolution cell 10 to main resolution cell 11, the detectors 22.sub.1 -22.sub.3, 24.sub.1 -24.sub.4 produce signals ABCDEFG indicating an absolute position of 11 (an increase in position from position 10); the signal produced on line 75.sub.1 clears the contents of decoder/counter 77, B.sub.0 -B.sub.10, to logical 0. Therefore, as member 14' continues to move further to the right, pulses are produced on lines 70.sub.1, 70.sub.2 as the detectors 65.sub.1, 65.sub.2 pass over the binary indicia along side of binary indicia 22.sub.11 (FIG. 5) are counted up by the up-down 77' (i.e., the contents of up-down counter 77' increment by one in response to each pulse). The counted pulses (i.e., the contents of up-down counter 77') thereby indicate, to within a resolution of 20.sub.48 sub-resolution cells, the position of member 12' relative to member 14' from main resolution cell 11; that is, the up-down counter 77' provides an indication of how far member 14' has moved to the right of main position cell 11.

The contents of up-down counter 77' provide the 11 least significant bits of the digital word signal produced by processor 68, i.e., bits B.sub.0 -B.sub.10, as indicated. The signals on lines G.sub.0 -G.sub.4 are converted from Gray code to binary code in Gray code to binary code converter 79 to provide the five most significant bits B.sub.11 -B.sub.15, i.e., the main scale of the determined position, as indicated. Thus, processor 68 produces a 16 bit digital word signal B.sub.15 -B.sub.0 ; where B.sub.15 is the MSB and B.sub.0 is the LSB. The digital word signal represented by B.sub.15 -B.sub.0 is greater than 10; indicating that the position of member 12' relative to member 14' is greater, or beyond, main position 10. (It should be noted that while the five MSBs provide an indication of the absolute position of one member 12' to member 14' the 11 LSBs provide an indication of how far one of the members 12', 14' has moved relative to the other member after a cell transition has been detected by the detector 75. That is, the vernier is provided by a relative, or incremental position encoder).

As the member 14' continues to move to the right so far that it reaches main resolution cell 12, a signal is produced on line 75.sub.1 again to clear the contents of up-down counter 77' to logical 0 and the process is repeated.

Likewise, when, in the example above, member 14' moves, here to the left from main resolution cell 10 to main resolution cell 9, the detectors 22.sub.1 -22.sub.3, 24.sub.1 -24.sub.4 produce signals ABCDEFG indicating an absolute position of 9 (a decrease in position from position 10 to position 9); the signal produced on line 75.sub.2 sets the contents of up/down counter 77', B.sub.0 -B.sub.10, to logical i Therefore, as member 14' continues to move further to the left, pulses are produced on lines 70.sub.1, 70.sub.2 as the detectors 65.sub.1, 65.sub.2 pass over the binary indicia along side of binary indicia 22.sub.11 (FIG. 5). The up-down counter 77' counts down from its maximum count (i.e. represented by its 11 bit contents having been set to logical 1), so that such pulses thereby indicate, to within a resolution of 20.sub.48 sub-resolution cells, the position of member 12' relative to member 14' from main resolution cell 11; that is, the up-down counter 77' provides an indication of how far member 14' has moved to the left of main position cell 9.

As noted above, the contents of up-down counter 77' provide the 11 least significant bits of the digital word signal produced by processor 68, i.e., bits B.sub.0 -B.sub.10, as indicated. The signals on lines G.sub.0 -G.sub.4 after being converted in converter 79 to provide the five most significant bits B.sub.11 -B.sub.15, as indicated. Thus, processor 68 (FIG. 6) produces a 16 bit digital word signal B.sub.15 -B.sub.0 ; where B.sub.15 is the MSB and B.sub.0 is the LSB. Thus, the digital word signal represented by B.sub.15 -B.sub.0 is greater than 9 by the amount not counted down by the up/down counter 77'. That is, the digital word signal represented by G.sub.4 -G.sub.0 (or B.sub.15 -B.sub.0 after being converted) plus the contents of up-down counter 77', B.sub.0 -B.sub.10. Thus, here, in this example, the digital word signal B.sub.15 -B.sub.0 indicates that the position of member 12' relative to member 14 is greater, or beyond, main position 9.

As the member 14' continues to move to the left so far that it reaches main resolution cell 8, a signal is produced on line 75.sub.2 again to set the contents of up-down counter 77' to logical 1, and the process is repeated.

Referring now to FIG. 7, an encoder 10" is shown for determining absolute position of a first member 12" with respect to a second member 14" to a resolution cell of L/512. Thus, here n=9. That is, encoder 10" is adapted to detect 512 positions; here, positions 0 to 511. As shown in FIG. 7, the encoder 10" is in the initial position; here position 0 Thus, here the first and second members 12" 4" are disposed in the X-Y plane, displaced from one another by a suitable distance along the Z-axis by a suitable bearing 50 (FIG. 9), and are adapted for relative movement along the Y axis by means of such bearing 50.

Referring again to FIG. 7, the first member 12" has m=3 tracks; here, tracks 30, 32, and 34 of binary indicia. Track 30 has binary indicia 42.sub.1 -42.sub.704 ; track 32 has binary indicia 46.sub.1 -46.sub.704 ; and track 34 has binary indicia 42.sub.1 -42.sub.704. The second member 14" has eighteen detectors arranged in three sets 35, 37, 39 of detectors; here, detectors 36.sub.1 -36.sub.4, 38.sub.1 -38.sub.7, and 40.sub.1 -40.sub.7, respectively, as shown. Each of the sets 35, 37, 39 of detectors 36.sub.1 -36.sub.4, 38.sub.1 -38.sub.7, and 40.sub.1 -40.sub.7 is adapted to detect the binary indicia 42.sub.1 -42.sub.704, 44.sub.1 -44.sub.704, 46.sub.1 -46.sub.704, respectively, in a corresponding one of the three tracks 30, 32, 34, respectively, as shown. The signals produced by detectors 40.sub.7 -40.sub.1 are A, B, C, D, E, F, and G, respectively, as indicated. The signals produced by detectors 38.sub.7 -38.sub.1 are H, I, J, K, L, M, and N, respectively, as indicated. The signals produced by detectors 36.sub.4 -36.sub.1 are O, P, Q, and R, respectively, as indicated. Thus, detectors 40.sub.7 -40.sub.1, 38.sub.7 -38.sub.1, 36.sub.4 -36.sub.1 produce a q=18 bit digital word signals ABCDEFGHIJKLMNOPQR- Such digital word signals, ABCDEFGHIJKLMNOPQR digital word signals, is a "cyclic", "unit-distance-code". Also because q=18>n=9, such digital word signals, ABCDEFGHIJKLMNOPQR, is an "excess-binary-code". The digital word signals ABCDEFGHIJKLMNOPQR produced by the detectors are decoded by a combinational logic section 28" to convert the signals into an n=9 bit binary word signal, G.sub.8 G.sub.7 G.sub.6 G.sub.5 G.sub.4 G.sub.3 G.sub.2 G.sub.1 G.sub. 0; where G.sub.0 is the least significant bit. The combinational logic section 28" combines the signals as follows:

G.sub.0 =A.sym.C.sym.E.sym.G

G.sub.1 =B.sym.F

G.sub.2 =D

G.sub.3 =H.sym.J.sym.L.sym.N

G.sub.4 =I.sym.M

G.sub.5 =K

G.sub.6 =P.sym.R

G.sub.7 =Q

G.sub.8 =0

It should be noted that the detectors 40.sub.1 -40.sub.7 need not be disposed contiguous one another (i.e., have a center-to-center separation of 0 resolution cells); but may be separated as was discussed above in connection with detectors 26.sub.1 -26.sub.3 (FIG. 2) and detectors 26.sub.1 -26.sub.3 in FIG. A. It is noted that the the center-to-center separation, s, of the detectors 38.sub.1 -38.sub.7 above track 32 is, here 8 binary indicia or resolution cells. Thus, for p=2, ps-1=15; and, the detectors above track 32 may have a center-to-center separation of 15 resolution cells . Thus, in position 0, detectors 40.sub.1 -40.sub.7 may be disposed over binary indicia 46.sub.8, 46.sub.23, 46.sub.38, 46.sub.53, 46.sub.68, and 46.sub.83, respectively. Further, the binary indicia along track 34 must, in such arrangement, be changed from logical 0 to logical 1: binary indicia 44.sub.577 -44.sub.640 ; 46.sub.521 -46.sub.528 ; 46.sub.537 -46.sub.544 ; 46.sub.553 -46.sub.560 ; 46.sub.569 -46.sub.576 ; 46.sub.585 -46.sub.592 ; 46.sub.601 -46.sub.608 ; 46.sub.617 -46.sub.624 ; 46.sub.633 -46.sub.640 ; 46.sub.649 -46.sub.656 ; 46.sub.665 -46.sub.672 ; 46.sub.681 -46.sub.688 ; and, 46.sub.697 -46.sub.704.

It is noted that while an n=9 bit digital word signal is provided for each of the 512 positions, or resolution cells, only m=3 tracks are used in the encoder 10". The truth table for encoder 10" is shown in FIG. 8, and FIGS. 8A through FIG. ST. Here, the track segments providing the binary indicia are high-energy Neodymium. The encoder 10" is adapted for use in a wide range of applications. One such application is in a linear actuator of the type described in U.S. Pat. No. 4,981,309, inventors Thomas A. Froeschle, Robert L. Marcesca and James A. Parison, issued Jan. 1, 1991, assigned to the same assignee as the present invention, the contents being incorporated herein by reference.

Referring to FIG. 9, a cross-section of such linear actuator having the encoder 10" is shown; such cross-section being in the X-Z plane. One member 12" has tracks 30, 32, 4 of binary indicia affixed thereto in slots 52, 54, 56, respectively, formed in member 12". The other member 14" has sets 35, 37, 39 of detectors affixed thereto. The members 12", 14" are adapted to move one with respect to the other by a bearing 50, as shown. It should be noted that set 35 of detectors is disposed in registration with track 30 of binary indicia; set 37 of detectors is disposed in registration with track 32 of binary indicia; and, set 39 of detectors is disposed in registration with track 34 of binary indicia. It should further be noted that set 39 of detectors and track 34 of binary indicia are disposed on one side, here the left side, of the bearing 50; while set 37 of detectors and track 32 of binary indicia together with set 35 of detectors and track 30 of binary indicia are disposed on the other side, here the right side, of the bearing 50. It is noted that a fourth slot 58 is provided in member 12" for insertion of a fourth track of binary indicia if greater resolution is desired. In such case, a fourth set of detectors would be mounted to the other member 14" in registration with the fourth track of binary indicia. The arrangement of having the tracks of binary indicia and its corresponding set of binary indicia detectors on different sides of the bearing 50 results in a compact encoder.

Other embodiments are within the claims. For example, while the pattern of binary indicia has been shown as a spatial pattern, the pattern may be a temporal pattern, as where the 2.sup.n positions are time sequential numbers and instead of being affixed to positions along tracks, may be stored in stages of a shift register or other memory with the storage stages being selectively coupled to binary detectors.