Background of the Invention
1. Field of the Invention
The present invention relates to the field of transconductance amplifiers.
2. Prior Art
A transconductance element is a basic building block frequently used to generate many analog functions. Many transconductance circuits are well known in the prior art. Conventional transconductance circuit topologies utilize a high gain amplifier in a negative feedback circuit to control a transconductance element. However these topologies take up more die area and are usually of slower speed than the present invention.
Brief Summary of the Invention
A simple high speed precision transconductance amplifier circuit having a low offset. The circuit uses as an input stage two substantially identical transistors of a first conductivity type connected in series so as to have the same current there through, neglecting base currents. A second stage uses two substantially identical transistors of a second conductivity type connected in series, with the output of the amplifier being a current mirrored from the second stage. The offset is maintained low by maintaining the V.sub.BE of the transistors in the two stages substantially identical by connecting together the base and collector of one of the transistors in one stage and coupling the resulting V.sub.BE of the transistor so coupled to one of the transistors of opposite conductivity type in the other stage. Various embodiments and variations are disclosed.
Brief Description of the Drawings
FIG. 1 presents a simple transconductance circuit.
FIG. 2 show an improvement to the circuit of FIG. 1 to reduce the offset characteristic of the circuit of FIG. 1.
FIG. 3 presents a transconductance circuit incorporating a way to match the V.sub.BE of PNP and NPN transistors, regardless of the process variations or the operating condition of the circuit.
FIG. 4 presents a modified and improved version of the circuit of FIG. 3.
FIG. 5 presents the circuit of FIG. 4 used as a unity gain buffer.
FIG. 6 presents a modification of FIG. 4 to provide an output current source rather than the output current sink of FIG. 4.
FIG. 7 presents the circuit of FIG. 4 modified to reference the input to the high input power connection.
Detailed Description of the Invention
The requirement of an ideal transconductance circuit is to generate an output current ##EQU1## Also the input impedance of an ideal circuit should be very high. A simple transconductance circuit is shown in FIG. 1 wherein: ##EQU2##
In this circuit, the V.sub.BE of Q.sub.1 creates an offset. Also the circuit is non-linear due to the dependence of V.sub.BE on the operating current, especially when the input voltage is close to ground. A circuit to reduce the offset is shown in FIG. 2, wherein: ##EQU3##
The difference in the V.sub.BE of the PNP transistor Q.sub.1 and the NPN transistor Q.sub.2 is smaller than the V.sub.BE of Q.sub.1 in FIG. 1, which reduces the offset and improves the linearity. For the two transistors: ##EQU4## where: ##EQU5## I.sub.c1 =collector current of transistor Q.sub.1 I.sub.c2 =collector current of transistor Q.sub.2
I.sub.s1 =saturation current of transistor Q.sub.1
I.sub.s2 =saturation current of transistor Q.sub.2
The circuit of FIG. 2 has a lower offset than that of FIG. 1. However the I.sub.s of a PNP and of an NPN are not related to each other and vary independently with process variations. Furthermore, the collector current of Q.sub.2 varies with the input voltage, whereas the collector current of Q.sub.1 is fixed. Therefore the offset of the circuit is still fairly large due to the variation in process parameters, and the circuit still has a non-linearity due to the variation in V.sub.BE2 with input voltage.
What is required is some means of controlling the V.sub.BE of Q.sub.1 to match the V.sub.BE of Q.sub.2, regardless of the process variations or the operating condition of the circuit. The circuit to accomplish this is shown in FIG. 3, and forms the basis for this invention. In the circuit shown in FIG. 3, Q.sub.3, Q.sub.4 and Q.sub.5 are identical devices. (Alternatively, Q.sub.5 may be a larger device, but should operate at the same current density as Q.sub.3 and Q.sub.4.) Q.sub.1 and Q.sub.2 are also identical devices and R.sub.1 =R.sub.2. In the analysis that follows, base currents and output impedance effects of the transistors are ignored.
Since Q.sub.3, Q.sub.4 and Q.sub.5 are identical and R.sub.1 =R.sub.2, a replica of the output current flows through Q.sub.4 and thus through Q.sub.3 in series therewith. Also V.sub.BE3 =V.sub.BE4 =V.sub.BE5 because of the identical transistors and equal currents.
Q.sub.1 is biased from a PNP transistor Q.sub.2 whose base-emitter is connected across the emitter-base of diode connected transistor Q.sub.3 and is thus equal thereto. Because Q.sub.1 and Q.sub.2 are identical devices and the two transistors are connected in series so as to have the same current therethrough, the V.sub.BE of Q.sub.1 is equal to and tracks the V.sub.BE of Q.sub.3.
Thus the offset and non-linearity due to unequal V.sub.BE s, is to a first order approximation, eliminated.
The circuit has been linearized by the addition of positive feedback. The loop gain is less than unity because of R.sub.1. Also since the loop gain in less than unity, the circuit does not need to be frequency compensated, which makes high speed operation possible. However, the circuit of FIG. 3 has some drawbacks.
1) The operating current in the input follower Q.sub.1 depends both on the input voltage and the ratio of the currents of the PNP and NPN transistors. The ratio of the currents is not controlled in typical processes, which leads to a significant variability in the operating current of Q.sub.1.
2) The output impedance of Q.sub.2 will cause an error.
3) The .varies. loss of Q.sub.5 causes an error.
4) The circuit has a stable operating point with zero current regardless of the input voltage, i.e. it needs a start-up circuit.
The circuit of FIG. 3 can be modified as shown in FIG. 4 to solve the above problems. In this Figure, R.sub.5 is added to limit the current in Q.sub.2 and increase its output impedance. Matching resistor R.sub.6 is added in the emitter of Q.sub.1. The alpha-loss of Q.sub.2 is compensated by R.sub.7 (R.sub.5 =R.sub.6 =R.sub.7). The current in Q.sub.1 and R.sub.6 is diminished by the base currents of Q.sub.4 and Q.sub.5. R.sub.4, which equals 2 * R.sub.5, compensates for this effect. The alpha-loss of Q.sub.5 is compensated by the addition of R.sub.3, which equals R.sub.2. Finally, start-up is ensured by the base current of Q.sub.6. I.sub.bias is a small current, typically less than 5 micro amps. These modifications substantially improve the performance of the circuit. (In a typical implementation, R.sub.3 and R.sub.4 will be combined into a single resistance in this and the other embodiments disclosed.)
The basic transconductance circuit is a versatile building block for many applications. An example of the above circuit as a unity gain buffer wherein R.sub.4 =R.sub.5 =R.sub.6 =R.sub.7 is shown in FIG. 5. In the embodiment shown in FIG. 4, the output is an output current sink. If an output current source is desired, the sink current of FIG. 4 may be mirrored, as shown in FIG. 6, through Q.sub.7 to the collector of Q.sub.8 to provide the current source output, equal to the sink output of FIG. 4 if Q.sub.7 and Q.sub.8 are identical transistors and R.sub.8 =R.sub.9, or ratioed to a different current scale factor if the areas of transistors Q.sub.7 and Q.sub.8 and conductances of resistors R.sub.8 and R.sub.9 are each correspondingly ratioed.
The inputs for the circuits of FIG. 3 through FIG. 6 are referenced to the ground or low terminal of the power supply. If it is desired to reference the same to Vcc or high terminal of the power supply, the circuits may be flipped by swapping NPN transistors for the PNP transistors and vice versa and reversing the power supply terminals (and the direction of any current sources in the circuit). As an example of this, FIG. 7 presents the circuit of FIG. 4 modified in this manner to reference the input to the high input power connection.
Similarly, the circuits of the present invention may also be realized in CMOS circuitry by replacing the NPN transistors with n-channel MOSFET devices and the PNP transistors with p-channel MOSFET devices. Thus, while the present invention has been disclosed and described with respect to certain preferred embodiments thereof, it will be understood to those skilled in the art that the present invention may be varied without departing from the spirit and scope of the invention.