Video Ram Method for Outputting Serial Data

The present invention relates to a video RAM as a dual port memory, and more particularly to a video RAM which is adaptable to a high speed system clock and a serial data output method thereof.

With the increased use of potable computers like a note book, the video RAMs are now very widely used in computers. A video RAM is a dual port memory which can be asynchronously utilized by adding the function of a data register which is capable of transferring data at a high speed to the function of a normal dynamic RAM. One conventional video RAM and its operation method are disclosed in U.S. patent application Ser. No. 4,498,155 entitled "Semiconductor Integrated Circuit Memory Device With Both Serial And Random Access Arrays" filed Feb. 5, 1985. Such a video RAM is designed to be able to connect a dynamic RAM port to a CPU and a high speed SAM port to an external system such as a CRT or a video camera, so that it has excellent system applicability and can have wide application. In order to diversify its functions and to store more information, highly integrated video RAM are continuing to be developed.

In a high performance graphic system, each device is required to operate in response to a high frequency in order to effectively perform the graphic interface between the computer and its user. Thus, the internal circuits in the video RAM should also operate in response to the high speed system clock supplied from the system. Such operation depends on whether the data transferred through a data I/O line within the video RAM can respond to the system clock.

FIG. 1 briefly shows the circuit elements related to data I/O lines in a conventional video RAM. FIG. 2 is an operational timing diagram of the FIG. 1 circuit. In FIG. 1, serial column gates 3 for transferring data is formed between a data register 2 and a serial data I/O line SIO. One serial column gate 3A has four serial column gate electrodes 4 commonly controlled by a serial column selection line SCSLi and another has four serial column gate electrodes 4 commonly controlled by a serial column selection line SCSLj. The serial data I/O line SIO is composed of one of the lines to receive data transferred from four serial column gates 3 in response to a single enabled of a serial column selection signal. The data on the serial data I/O line SIO is multiplexed through a multiplexer 6 and is amplified through a sense amplifier 8. The output of the sense amplifier is applied to a latch unit 10 which is controlled by the control signal .phi.PSOT, and the output of the latch unit 10 is applied to a latch output unit 12 which is controlled by the control signal .phi.SOT and then outputs data to externally.

Referring to the timing diagram of FIG. 2, the operational characteristic of the FIG. 1 circuit will now be described. The serial address is incremented at the falling edge of the serial clock SC. The corresponding serial column selection line is enabled on the basis of the serial address. With the enable of the serial column selection line, data stored in the data register 2 is outputted to the serial data I/O line SIO, and the sense amplifier 8 thus outputs the amplified signal SDO. Referring to FIG. 2, the signal SDO generated at the falling edge of the nth serial clock SC is latched at the falling edge of the (n+1)th serial clock SC by the control signal .phi.PSOT, and is then output as valid data at the rising edge of the (n+2)th serial clock SC external from the chip. Such a construction having a data I/O line as shown in FIG. 1 is designed to read out data from the memory cell through a single data I/O line. Additional time is required to sense data.

However, such construction consumes large amounts of time, as described hereinafter through the data I/O line because this depends on the minimum time required in developing the serial data I/O line from the activation of the serial column selection line SCSL. Also, additional time is required for precharging and equalizing the data I/O line is required in order to prepare next read cycle, because the precharge time depends on the time required in equalizing the amplified data I/O line. In addition, extra time is required for latching the valid data which depends on the time required in generating the signal SDO that is latched by the control signal .phi.PSOT. Since the FIG. 1 circuit is designed in consideration of the above-mentioned timing requirements, the time interval between respective serial clocks and the operation cycle is increased. This time consumption affects the operation cycle of the whole chip, and thus the cycle time is relatively increased as compared to the serial clock. This causes another in that it is difficult to transfer data at a high speed from the data register to the external display device.

It is therefore an object of the present invention to provide a video RAM which is capable of transferring data at a high speed from a data register to an external display device.

It is another object of the present invention to provide a video RAM which is capable of minimizing the operation cycle time determined by a serial clock.

It is another object of the present invention to provide a video RAM which is capable of reducing the period of each serial clock.

It is further another object of the present invention to provide a video RAM which is capable of minimizing the operation cycle time by outputting data stored in the data register while the serial data I/O line related to the next data is precharged.

It is still further another object of the present invention to provide a serial data output method of a video RAM which outputs data stored in the data register while the serial data I/O line related to the next data is precharged.

To achieve these objects, the present invention provides the video RAM which reduces the operation cycle time to be adaptable to the high speed serial clock.

The video RAM according to the present invention comprises two separate serial data I/O lines which are selected by different addresses.

In accordance with the present invention, the video RAM having a data register which outputs a serial data in response to the input of the serial address which is synchronized with a serial clock. This video RAM includes a first data I/O line for transferring data which is synchronized with the even serial address and then output from the data register. A second data I/O line transfers the data which is synchronized with the odd serial address and is then output from the data register.

In addition, in accordance with the present invention, the serial data output method of the video RAM having a data register which outputs a serial data in response to the input of the serial address which is synchronized with a serial clock includes a first step of transferring the data which is synchronized with the even serial address and then output from the data register to the first data I/O line. A second step of transfers the data which is synchronized with the odd serial address and then outputs it from the data register to the second data I/O line. A third step of synchronizes and latches the data transferred from the first step with the even serial address, a fourth step of synchronizing and latching the data transferred from the second step with the odd serial address, and a fifth step of synchronizes the serial data latched through the third and fourth steps with the serial clock and then externally outputs the synchronized serial data.

In the detailed description of the preferred embodiment of the present invention presented below, reference is made to the accompanying drawings, in which:

FIG. 1 is a schematic diagram showing a serial data output path of a conventional video RAM;

FIG. 2 is a timing diagram of FIG. 1;

FIG. 3 is a diagram showing a serial data output path of the video RAM according to the present invention; and

FIG. 4 is a timing diagram of FIG. 3.

FIG. 3 is a block circuit diagram showing the output path of the video RAM according to the present invention. As shown, the FIG. 3 circuit includes a data register 2, a serial data I/O line SIO having 8 lines for transferring data read out from the data register 2. One column gate 3 with four column gate 4A electrodes is formed between the serial data I/O line SIO and the data register 2 and is switching-controlled by the serial column selection lines SCSLodd which are selected by the odd address, for transferring data from the data register 2 to four serial data I/O lines selected by an odd address. Another column gate 3B has four column gate electrodes 4B formed between the serial data I/O line SIO and the data register 2 and is switching-controlled by the serial column selection lines SCSLeven which are selected by an even address, for transferring data from the data register 2 to four serial data I/O lines selected by the even address. Multiplexers 14 and 16 for multiplex eight serial data I/O lines responsive to the logic state("low/high") of CAB, an I/O line sense amplifier S/A 18 amplifiers the output signal of the multiplexer 14 which is connected to four serial data I/O lines selected by the even address, and an I/O line sense amplifier S/A 20 amplifies the output signal of the multiplexer 16 which is connected to four serial data I/O lines selected by the odd address. An even latch unit 22 latches the output signal SDOeven of the I/O line sense amplifier S/A 18 under the control of the signal .phi.PSOTeven, an odd latch unit 24 latches the output signal SDOodd of the I/O line sense amplifier S/A 20 under the control of the control signal .phi.PSOTodd, and a latch output unit 26 latches and externally outputs respective output signals of the even latch unit 22 and odd latch unit 24 in response to the control signal .phi.SOT. As shown in FIG. 3, the serial data I/O line SIO is composed of eight lines, four of which are selected by the address 8 and the other four of which by the address 8. Two of four serial data I/O lines selected by the address 8 and two of the other four serial data I/O lines selected by the address 8 are applied to the even multiplexer 14, and the remaining four serial data I/O lines SIO are applied to the odd multiplexer 16. In FIG. 3, a single data register 2 has two independent serial data I/O lines which are selected by different addresses. Due to their selective operation, the operation cycle time can be reduced and such will be described hereinafter.

FIG. 4 is a timing diagram showing the timing between respective control signals of FIG. 3. Referring to FIG. 4, the operational characteristics of the FIG. 3 circuit will now be described. The video RAM according to the present invention is capable of being synchronized with a high speed serial clock, thus outputting the serial data by performing independent sensing operations respectively for odd and even address data. As shown in FIGS. 3 and 4, the even latch unit 22 and odd latch unit 24 are respectively controlled by the signals .phi.PSOTeven and .phi.PSOTodd which are alternatively enabled every two periods of the serial clock SC, and respective output signals thereof are applied to the latch output unit 26 in response to the control of the signals .phi.PSOTeven and .phi.PSOTodd. Enabling of the control signal .phi.SOT is synchronized at the rising edge of each period of the serial clock SC and the data is externally output from the latch output unit 26. On the basis of such operation, while four of eight serial data I/O lines SIO perform a sensing operation to externally output data, the remaining four serial data I/O lines perform the precharge and equalization, and while the remaining four serial data I/O lines perform the sensing operation to externally output data, the former lines perform the precharge and equalization. As a result, it is possible to synchronize with the serial clock SC every period thereof and then to output serial data.

The serial data output method according to the present invention will now be described by comparing it to the conventional method. Referring to FIG. 2 which shows a timing diagram of the conventional video RAM, the serial column selection line SCSL must be precharged and equalized every cycle for a single serial address, as the corresponding serial data I/O line is accessed every cycle. However, referring to FIG. 4 showing the tinting diagram of the video RAM according to the present invention, since the serial I/O line SIO is selectively accessed corresponding to the even or odd address, the corresponding serial I/O line SIO precharges and equalizes the serial column selection line SCSL only during the corresponding cycle. With the FIG. 2 timing, the serial column selection line SCSL must be controlled with a self-pulse in order to perform the precharge and equalization However, in the FIG. 4 timing, the serial column selection line SCSL is controlled only by the address. The multiplexers 14 and 16 function to connect the corresponding serial I/O line to the I/O line sense amplifiers, depending upon the logic state of the serial address CAB. All control signals corresponding to even are operated when CA8 is in the logic "low" state, and all control signals corresponding to odd are operated when CA8 is in the logic "high" state.

As described above, the video RAM according to the present invention has independent serial data output paths for even and odd addresses, thus outputting serial data every period of the serial clock. Consequently, it is possible to reduce the operation cycle time of the video RAM and to transfer data to the CRT at a high speed. In addition, it is possible to reduce the time interval between respective periods of the system clock.

While this invention has been described with reference to illustrative embodiment, this description is not intended to be construed in a limiting sense and various modification of the illustrative embodiments will be apparent to one skilled in the art upon reference to this description.