US 5,568,092 AGrant
Attenuated Feedback Type Differential Amplifier
Issue Date:1996-10-22
•11 Claims
•8 Drawing Sheets
Abstract
A differential amplifier includes an input stage for receiving input signals, an output stage for generating output signals, and an attenuating circuit for attenuating the output signals and feeding attenuation signals back to the input stage. The input stage includes a current switch formed by two transistors connected commonly to a current source and each connected to two load amplifiers. The load amplifiers are controlled by the attenuation signal, to substantially reduce the amplification of the two transistors.
Metadata
Assignee
- NEC Corporation
Inventors
- Toshifumi Shimizu
- Hiroshi Narikawa
- Yoshiyuki Tamura
Application Information
Application Number:US 4495284
Filing Date:1995-05-24
Priority Date:1994-05-24
Art Unit:255
Classifications
IPC:
H03F 345
Field of Search:
330360260;31167;68
Patent Drawings (8 sheets)
Description
Background of the Invention
1. Field of the Invention
The present invention relates to a differential amplifier used for amplifying a read signal in a magnetic memory device, i.e., a hard disk, a semiconductor memory device, and the like.
1. Description of the Related Art
A differential amplifier for amplifying a read signal in a hard disk or a semiconductor memory device has to satisfy the following two requirements:
1) a differential input capacity is as small as possible; and
2) a noise level in an output signal is as small as possible.
For example, in a hard disk having an increased memory density, the frequency of a read signal is higher. Therefore, when the differential input capacity of the differential amplifier as a read amplifier is large, it is difficult to sense the read signal. Also, when the amplitude of the read signal is small, i.e., the S/N ratio thereof is small, a high noise level in the differential amplifier may invite a read error.
A first prior art differential amplifier includes an input stage for receiving and amplifying input signals, and an output stage formed by emitter followers for receiving amplified signals from the input stage to generate output signals. This will be explained later in detail. In the first prior art differential amplifier, however, the differential input capacity is still large, although the noise level of the output signals is small.
In a second prior art differential amplifier, the output signals of the output stage are fed back to the input stage (see: JP-A-HEI2-223209). This will be explained later in detail. In the second prior art differential amplifier, however, the noise level of the output signals is still large, although the differential input capacity is small.
Summary of the Invention
It is an object of the present invention to provide a differential amplifier having a differential small input capacity and a small noise level in output signals.
According to the present invention, a differential amplifier includes an input stage for receiving input signals, an output stage for generating output signals, and an attenuating circuit for attenuating the output signals and feeding attenuation signals back to the input stage. The input stage includes a current switch formed by two transistors connected commonly to a current source and each connected to two load amplifiers. The load amplifiers are controlled by the attenuation signals, to substantially reduce the differential input capacity. In this case, even when the amplification of the two transistors is substantially reduced, the amplification of the load amplifiers is adjustable to maintain the amplification of the entire differential amplifier at a high value. Also, since the amplification of the output stage formed by the emitter followers is small, the noise level in the output signals is reduced.
Brief Description of the Drawings
The present invention will be more clearly understood from the description as set forth below, with reference to the accompanying drawings, wherein:
FIG. 1 is a circuit diagram illustrating a first prior art differential amplifier;
FIG. 2 is a circuit diagram illustrating a second prior art differential amplifier;
FIG. 3 is a circuit diagram illustrating an embodiment of the differential amplifier according to the present invention;
FIG. 4 is a detailed circuit diagram of the differential amplifier of FIG. 3 having a first example of the attenuating circuit;
FIG. 5 is a detailed circuit diagram of the differential amplifier of FIG. 3 having a second example of the attenuating circuit;
FIG. 6 is a detailed circuit diagram of the differential amplifier of FIG. 3 having a third example of the attenuating circuit;
FIG. 7 is a detailed circuit diagram of the differential amplifier of FIG. 3 having a fourth example of the attenuating circuit; and
FIG. 8 is a detailed circuit diagram of the differential amplifier of FIG. 3 having a fifth example of the attenuating circuit.
Description of the Preferred Embodiment
Before the description of the prefered embodiment, prior art differential amplifiers will be explained with reference to FIGS. 1 and 2.
In FIG. 1, which illustrates the first prior art differential amplifier, reference numeral 1 designates an input stage for receiving and amplifying input signals V.sub.in and V.sub.in, and 2 designates an output stage for generating output signals V.sub.out and V.sub.out. Also, V.sub.CC designates a high power supply terminal and V.sub.EE designates a low power supply terminal.
The input stage 1 includes a differential stage, i.e., a current switch formed by a current source I.sub.1 connected to the power supply terminal V.sub.EE and two NPN type bipolar transistors Q.sub.1 and Q.sub.2 having emitters commonly connected to the current source I.sub.1. The bases of the transistors Q.sub.1 and Q.sub.2 receive the input signals V.sub.in and V.sub.in, respectively. The collectors of the transistors Q.sub.1 and Q.sub.2 are connected via NPN type bipolar transistors Q.sub.3 and Q.sub.4 and resistors R.sub.1 and R.sub.2 to the power supply terminal V.sub.CC. In this case, the transistors Q.sub.3 and Q.sub.4 are of a common-base type where a definite voltage V.sub.REF is applied to the bases thereof, and therefore, the transistors Q.sub.3 and Q.sub.4 serve as operating resistors. Thus, an amplification A.sub.0 of the transistors Q.sub.1 and Q.sub.2 at the collectors thereof is almost 1. In this case, a differential input capacity C.sub.in.spsb.1 can be represented by
where C.sub.CB is a capacity between the collector and base of each of the transistors Q.sub.1 and Q.sub.2 ; and
C.sub.EB is a capacity between the emitter and base of each of the transistors Q.sub.1 and Q.sub.2. Also, as stated above, since A.sub.0 =1, then the formula (1) is replaced by
Further, if C.sub.CB =C.sub.EB =10 pF, then, the formula (2) is replaced by
On the other hand, the output stage 2 includes emitter followers Q.sub.5 and Q.sub.6 connected to current sources I.sub.2 and I.sub.3, respectively. In this case, a noise level V.sub.NO.spsb.1 in the output signals V.sub.out and V.sub.out can be represented by ##EQU1##
where V.sub.N.spsb.1 is a noise level of the input stage 1;
V.sub.N.spsb.2 is a noise level of the output stage 2;
A.sub.1 is a differential amplification of the transistors Q.sub.3 and Q.sub.4 at their collectors; and
A.sub.2 is an amplification of each of the emitter followers Q.sub.5 and Q.sub.6.
A total amplification A.sub.TOT.spsb.1 of the differential amplifier of FIG. 1 is represented by
Therefore, the formula (4) is replaced by ##EQU2## Since the amplification A.sub.2 of the emitter followers Q.sub.5 and Q.sub.6 is 1, A.sub.TOT.spsb.1 =A.sub.1. Therefore, if A.sub.1 =30 and V.sub.N.spsb.1 =V.sub.N.spsb.2 =1.0 nV.sub.ems, then ##EQU3##
In FIG. 2, which illustrates a second prior art differential amplifier (see: JP-A-HEI2-223209), reference numeral 1' designates an input stage for receiving and amplifying input signals V.sub.in and V.sub.in, and 2' designates an output stage for generating output signals V.sub.out and V.sub.out. Each of the input stage 1' and the output stage 2'serves as one differential amplifier. In this case, the output signals V.sub.out and V.sub.out of the output stage 2' are fed back in opposite phase to the input stage 1'.
The input stage 1' includes a differential stage i.e., a current switch formed by a current source I.sub.1 connected to the power supply terminal V.sub.EE and two NPN type bipolar transistors Q.sub.1 and Q.sub.2 having emitters commonly connected to the current source I.sub.1. The bases of the transistors Q.sub.1 and Q.sub.2 receive the input signals V.sub.in and V.sub.in, respectively. The collectors of the transistors Q.sub.1 and Q.sub.2 are connected via resistors R.sub.1 and R.sub.2 and NPN type bipolar transistors Q.sub.3 and Q.sub.4 to the power supply terminal V.sub.CC.
On the other hand, the input stage 2' includes a differential stage, i.e., a current switch formed by a current source I.sub.2 connected to the power supply terminal V.sub.EE and two NPN type bipolar transistors Q.sub.5 and Q.sub.6 having emitters commonly connected to the current source I.sub.2. The bases of the transistors Q.sub.1 and Q.sub.2 receive the voltages at the collectors of the transistors Q.sub.2 and Q.sub.1, respectively. The collectors of the transistors Q.sub.5 and Q.sub.6 are connected via resistors R.sub.3 and R.sub.4, respectively, to the power supply terminal V.sub.CC.
The output signals V.sub.out and V.sub.out are fed back to the gates of the transistors Q.sub.4 and Q.sub.3, respectively.
In the differential amplifier of FIG. 2, a differential amplification A.sub.3F of the transistors Q.sub.1 and Q.sub.2 at the collectors thereof where a feed back is performed is represented by
where A.sub.3 is a differential amplification of the transistors Q.sub.1 and Q.sub.2 at the collectors thereof (A.sub.3 =1) where no feed back is performed; and
A.sub.4 is an amplification of the transistors Q.sub.5 and Q.sub.6.
In this case, the amplifications A.sub.3 and A.sub.4 are so determined as to satisfy the following condition:
For example, A.sub.3 =1 and A.sub.4 =3, then
Also, a differential input capacity C.sub.in.spsb.2 can be represented by
where C.sub.CB is a capacity between the collector and base of each of the transistors Q.sub.1 and Q.sub.2 ; and
C.sub.EB is a capacity between the emitter and base of each of the transistors Q.sub.1 and Q.sub.2. Also, if A.sub.3F =0.5 and C.sub.CB =C.sub.EB =10 pF, then, the formula (11) is replaced by
On the other hand, a noise level V.sub.NO.spsb.2 in the output signals V.sub.out and V.sub.out can be represented by ##EQU4##
where V.sub.N.spsb.3 is a noise level of the input stage 1';
V.sub.N.spsb.4 is a noise level of the output stage 2'; and
A.sub.4 is an amplification of each of the emitter followers Q.sub.5 and Q.sub.6.
A total amplification A.sub.TOT.spsb.2 of the differential amplifier of FIG. 2 is represented by
Therefore, the formula (13) is replaced by ##EQU5## A.sub.TOT.spsb.2 = A.sub.TOT.spsb.1 = 30, then ##EQU6## Also, if V.sub.N.spsb.1 = V.sub.n.spsb.2 = 1.0 nV.sub.rms, then
A.sub.TOT.spsb.2 = A.sub.TOT.spsb.1 = 30, then ##EQU7##
From the formulae (3) and (12),
Therefore, the diffential input capacity of the differential amplifier of FIG. 2 is smaller than that of the differential amplifier of FIG. 1. That is, in the differential amplifier of FIG. 1, the differential input capacity C.sub.in.spsb.1 depends upon the amplification A.sub.0 of the transistors Q.sub.1 and Q.sub.2 at their collectors (see formula (1)). Contrary to this, in the differential amplifier of FIG. 2, the differential input capacity C.sub.in.spsb.2 depends upon the differential amplification A.sub.3.sbsb.f of the transistors Q.sub.1 and Q.sub.2 at their collectors where a feedback is performed (see formula (11)). Since A.sub.0 =1 and A.sub.3.sbsb.F <1 (A.sub.3.sbsb.F =0.5), the differential input capacity is smaller in the differential amplifier of FIG. 2 than in the differential amplifier of FIG. 1.
Conversely, from the formulae (7) and (17),
Therefore, the noise level of the output signals of the differential amplifier of FIG. 2 is larger than that of the differential amplifier of FIG. 1. That is, in the differential amplifier of FIG. 1, the noise level V.sub.NO.spsb.1 depends upon the amplification of A.sub.2 of the output stage 2 (see formula (6)). Contrary to this, in the differential amplifier of FIG. 2, the noise level V.sub.NO.spsb.2 depends upon the amplification A.sub.4 (see formula (15)). In order to maintain the condition A.sub.TOT.spsb.1 =A.sub.TOT.spsb.2, the amplification A.sub.4 has to be larger, for example, A.sub.4 =60. Therefore, if A.sub.2 =1 and A.sub.4 >1 (A.sub.4 =60), the noise level is larger in the differential amplifier of FIG. 2 than in the differential amplifier of FIG. 1.
Thus, in the prior art, a small differential input capacity and a small output noise are not incompatible with each other.
In FIG. 3, which illustrates an embodiment of the present invention, reference numeral 1" designates an input stage for receiving and amplifying input signals V.sub.in and V.sub.in, 2" designates an output stage for generating output signals V.sub.out and V.sub.out, and 3 designates an attenuating circuit (or feedback circuit) for attenuating the output signals V.sub.out and V.sub.out and transmitting them in opposite phase to the input stage 1".
The input stage 1" includes a differential stage i.e., a current switch formed by a current source I.sub.1 connected to the power supply terminal V.sub.EE and two NPN type bipolar transistors Q.sub.1 and Q.sub.2 having emitters commonly connected to the current source I.sub.1. The bases of the transistors Q.sub.1 and Q.sub.2 receive the input signals V.sub.in and V.sub.in, respectively. The collectors of the transistors Q.sub.1 and Q.sub.2 are connected via NPN type bipolar transistors Q.sub.3 and Q.sub.4 and resistors R.sub.1 and R.sub.2 to the power supply terminal V.sub.CC. In this case, the transistors Q.sub.3 and Q.sub.4 are controlled by the attenuating circuit 3. The transistor Q.sub.3 and the resistor R.sub.1 form a load amplifier whose amplification A.sub.7 is determined by the value of the resistor R.sub.1. Similarly, the transistor Q.sub.4 and the resistor R.sub.2 form a load amplifier whose amplification A.sub.7 is determined by the value of the resistor R.sub.2.
The output stage 2" includes emitter followers Q.sub.5 and Q.sub.6 for generating the output signals V.sub.out and V.sub.out. The emitter followers Q.sub.5 and Q.sub.6 are controlled by the voltages at the collectors of the transistor Q.sub.3 and Q.sub.4 of the input stage 1".
The output signals V.sub.out and V.sub.out of the output stage 2" are fed back via the attenuating circuit 3 to the bases of the transistors Q.sub.4 and Q.sub.3.
In the differential amplifier of FIG. 3, a differential amplification A.sub.5.sbsb.F of the transistors Q.sub.1 and Q.sub.2 at the collectors thereof where a feed back is performed is represented by
where A.sub.5 is a differential amplification of the transistors Q.sub.1 and Q.sub.2 at the collectors thereof (A.sub.5 =1) where no feed back is performed; and
A.sub.6 is a differential feedback amplification of the attenuation circuit 3.
Note that the differential feedback amplification A.sub.6 is represented by
where A.sub.TOT.spsb.3 is a total differential amplification of the differential amplifier of FIG. 3;
1/n is an attenuation factor of the attenuating circuit 3;
A.sub.7 is a differential amplification of the transistors Q.sub.3 and Q.sub.4 ; and
A.sub.8 is a differential amplification of the transistors Q.sub.5 and Q.sub.6. Also, the differential amplification A.sub.5 is determined by a ratio of an operating resistor R.sub.eQ.spsb.1 =(kT/q)/I.sub.EQ.spsb.1 of the transistor Q.sub.1 to an operating resistor r.sub.eQ.spsb.2 =(kT/q)/I.sub.EQ.spsb.2 where k is a Boltzmann's coefficient, T is an absolute temperature, and q is a charge of an electron; in this case, I.sub.EQ.spsb.1 =I.sub.EQ.spsb.2, and as a result, A.sub.5 =1.
Therefore, the formula (20) is replaced by
Also, a differential input capacity C.sub.in.spsb.3 can be represented by
where C.sub.CB is a capacity between the collector and base of each of the transistors Q.sub.1 and Q.sub.2.
C.sub.EB is a capacity between the emitter and base of each of the transistors Q.sub.1 and Q.sub.2.
Also, if A.sub.5.sbsb.F =0.5 and C.sub.CB =C.sub.EB =10 pF, then, the formula (23) is replaced by
On the other hand, a noise level L.sub.NO.spsb.1 in the output signals V.sub.out and V.sub.out can be represented by ##EQU8##
where V.sub.N.spsb.5 is a noise level of the input stage 1"; and
V.sub.N.spsb.6 is a noise level of the output stage 2".
The total amplification A.sub.TOT.spsb.3 of the differential amplifier of FIG. 3 is represented by
Therefore, since A.sub.8 =1, the formula (25) is replaced by ##EQU9## If A.sub.TOT.spsb.3 =A.sub.TOT.spsb.2 =A.sub.TOT.spsb.1 =30 and V.sub.N.spsb.5 =V.sub.N.spsb.6 =1.0 nV.sub.rms, then ##EQU10##
Thus, in the embodiment as illustrated in FIG. 3, the differential input capacity is as small as that of the differential amplifier of FIG. 2, and also, the noise level is as small as that of the differeantial amplifier of FIG. 1.
Examples of the attenuating circuit 3 of FIG. 3 will be explained next with reference to FIGS. 4, 5, 6, 7 and 8.
A first example of the attenuating circuit 3 of FIG. 3 is illustrated in FIG. 4. That is, the attenuating circuit 3 includes a resistor R.sub.3 connected to the emitter follower Q.sub.5 of the output stage 2" and a diode D.sub.1 connected to the resistor R.sub.3, also includes a resistor R.sub.4 connected to the emitter follower Q.sub.6 of the output stage 2" and a diode D.sub.2 connected to the resistor R.sub.4. Further the attenuating circuit 3 includes a current source I.sub.2 connected commonly to the diodes D.sub.1 and D.sub.2. A voltage at a node between the resistor R.sub.3 and the anode of the diode D.sub.1 is fed back to the base of the transistor Q.sub.4 of the input stage 1". Similarly, a voltage at a node between the resistor R.sub.4 and the anode of the diode D.sub.2 is fed back to the base of the transistor Q.sub.3 of the input stage 1".
A feedback amplification A.sub.61 of the attenuating circuit 3 to the base of the transistor Q.sub.4 is represented by
where R.sub.D.spsb.1 is an operating resistance of the diode D.sub.1. Similarly, a feedback amplification A.sub.62 of the attenuating circuit 3 to the base of the transistor Q.sub.3 is represented by
where R.sub.D.spsb.2 is an operating resistance of the diode D.sub.2. If the resistance of the resistor R.sub.1 is the same as that of the resistor R.sub.2 and the junction area of the diode D.sub.1 is the same as that of the diode D.sub.2, then
If A.sub.TOT.spsb.3 =30 and A.sub.5.sbsb.F =0.5, then, from the formulae (22) and (26),
Also, if a current of the current source I.sub.2 is 1 mA, then
Therefore, from the formulae (29), (31) to (34),
A second example of the attenuating circuit 3 of FIG. 3 is illustrated in FIG. 5. In FIG. 5, resistors R.sub.5 and R.sub.6 are provided instead of the diodes D.sub.1 and D.sub.2, respectively, of FIG. 4. In this case, if the values of the resistors R.sub.5 and R.sub.6 are the same as the operating resistances of the diodes D.sub.1 and D.sub.2, respectively, i.e., R.sub.5 =R.sub.6 =52.0.OMEGA., the attenuating circuit 3 of FIG. 5 operates in the same way as the attenuating circuit 3 of FIG. 4.
A third example of the attenuating circuit 3 of FIG. 3 is illustrated in FIG. 6. In FIG. 6, diodes D.sub.3, .multidot..multidot..multidot., D.sub.m are provided instead of the current source I.sub.2 of FIG. 4. In this case, the attenuating circuit 3 of FIG. 6 can operate in the same way as the attenuating circuit 3 of FIG. 4.
A fourth example of the attenuating circuit 3 of FIG. 3 is illustrated in FIG. 7. In FIG. 7, diodes D.sub.3, .multidot..multidot..multidot., D.sub.m are provided instead of the current source I.sub.2 of FIG. 5. In this case, the attenuating circuit 3 of FIG. 7 can operate in the same way as the attenuating circuit 3 of FIG. 5.
A fifth example of the attenuating circuit 3 of FIG. 3 is illustrated in FIG. 8. That is, the attenuating circuit 3 includes a current source I.sub.2 between the emitter follower Q.sub.5 and the power supply terminal V.sub.EE and a current source I.sub.3 between the emitter follower Q.sub.6 and the power supply terminal V.sub.EE. Also, the attenuating circuit 3 includes three resistors R.sub.7, R.sub.8 and R.sub.9 in series between the emitter of the emitter follower Q.sub.5 and the emitter of the emitter follower Q.sub.6. A voltage at a node between the resistor R.sub.7 and the resistor R.sub.8 is fed back to the base of the transistor Q.sub.4 of the input stage 1". Similarly, a voltage at a node between the resistor R.sub.8 and the resistor R.sub.9 is fed back to the base of the transistor Q.sub.3 of the input stage 1".
A feedback amplification A.sub.61 ' of the attenuating circuit 3 to the base of the transistor Q.sub.4 is represented by
Similarly, a feedback amplification A.sub.62 ' of the attenuating circuit 3 to the base of the transistor Q.sub.3 is represented by
If the value of the resistor A.sub.7 is the same as that of the resistor R.sub.9, for example, if R.sub.7 =R.sub.9 =200.OMEGA., then
A.sub.TOT.spsb.3 =30 and A.sub.6 =3.0, then, from the formulae (35) (or (36)) and (37),
As explained hereinbefore, according to the present invention, a differential input capacity can be reduced, and simultaneously, a noise level in output signals can be reduced without reducing the entire differential amplification.
Claims
We claim:
1. A differential amplifier comprising: first and second power supply terminals; an input stage, connected between said first and second power supply terminals, for receiving first and second input signals and outputting first and second intermediate signals in response to said first and second input signals; an output stage, connected to said first power supply terminal and to said input stage, for receiving said first and second intermediate signals and outputting first and second output signals in response to said first and second intermediate signals; and an attenuating circuit, connected between said output stage and said second power supply terminal and to said input stage, for attenuating said first and second output signals to generate first and second attenuation signals in response to said first and second output signals and transmitting said first and second attenuation signals to said input stage, wherein said input stage includes a first current source connected to said second power supply terminal, first and second transistors having bases for receiving said first and second input signals, respectively, and emitters connected to said first current source, a third transistor having an emitter connected to a collector of said first transistor and a base for receiving said second attenuation signal, a fourth transistor having an emitter connected to a collector of said second transistor and a base for receiving said first attenuation signal, a first resistor connected between said first power supply terminal and a collector of said third transistor, and a second resistor connected between said first power supply terminal and a collector of said fourth transistor, wherein said output stage includes a first emitter follower for receiving said first intermediate signal to generate said first output signal, and a second emitter follower for receiving said second intermediate signal to generate said second output signal.
2. A differential amplifier as set forth in claim 1, wherein said attenuating circuit includes a third resistor connected to an output of said first emitter follower, a fourth resistor connected to an output of said second emitter follower, a second current source connected to said second power supply terminal, a first diode connected between said third resistor and said second current source, and a second diode connected between said fourth resistor and said second current source, a first node between said third resistor and said first diode generating said first attenuation signal, a second node between said fourth resistor and said second diode generating said second attenuation signal.
3. A differential amplifier as set forth in claim 1, wherein said attenuating circuit includes a third resistor connected to an output of said first emitter follower, a fourth resistor connected to an output of said second emitter follower, a second current source connected to said second power emitter follower, a second current source connected to said second power supply terminal, a fifth resistor connected between said third resistor and said second current source, and a sixth resistor connected between said fourth resistor and said second current source, a first node between said third resistor and said fifth resistor generating said first attenuation signal, a second node between said fourth resistor and said sixth resistor generating said second attenuation signal.
4. A differential amplifier as set forth in claim 1, wherein said attenuating circuit includes a third resistor connected to an output of said first emitter follower, a fourth resistor connected to an output of said second emitter follower, diode means connected to said second power supply terminal, a first diode connected between said third resistor and said diode means, and a second diode connected between said fourth resistor and said diode means, a first node between said third resistor and said first diode generating said first attenuation signal, a second node between said fourth resistor and said second diode generating said second attenuation signal.
5. A differential amplifier as set forth in claim 1, wherein said attenuating circuit includes a third resistor connected to an output of said first emitter follower, a fourth resistor connected to an output of said second emitter follower, diode means connected to said second power supply terminal, a fifth resistor connected between said third resistor and said diode means, and a sixth resistor connected between said fourth resistor and said diode means, a first node between said third resistor and said fifth resistor generating said first attenuation signal, a second node between said fourth resistor and said sixth resistor generating said second attenuation signal.
6. A differential amplifier as set forth in claim 1, wherein said attenuating circuit includes a second current source connected between an output of said first emitter follower and said second power supply terminal, and a third current source connected between an output of said second emitter follower and said second power supply terminal, third, fourth and fifth resistors connected between the output of said first emitter follower and the output of said second emitter follower, a first node between said third resistor and said fourth resistor generating said first attenuation signal, a second node between said fourth resistor and said fifth resistor generating said second attenuation signal.
7. A differential amplifier comprising: first and second power supply terminals; a current switch having a first current source connected to said second power supply terminal and first and second transistors connected commonly to said first current source, said first and second transistors being controlled by first and second input signals, respectively, a first load amplifier connected between said first power supply terminal and said first transistor and having an amplification larger than 1; a second load amplifier connected between said first power supply terminal and said second transistor and having an amplification larger than 1; a first emitter follower connected to said first power supply terminal and to said first load amplifier, said first emitter follower having an amplification of approximately 1 and generating a first output signal; a second emitter follower connected to said first power supply terminal and to said second load amplifier, said second emitter follower having an amplification of approximately 1 and generating a second output signal; and a feedback circuit, connected to said first and second emitter followers and said second power supply terminal, for attenuating said first and second output signals to generate first and second attenuation signals, said first and second attenuation signals being transmitted to said second and first load amplifiers, respectively, thus substantially reducing an amplification of said first and second transistors to less than 1, wherein said feedback circuit includes a first resistor connected to an output of said first emitter follower, a second resistor connected to an output of said second emitter follower, a second current source connected to said second power supply terminal, a first diode connected between said first resistor and said second current source, and a second diode connected between said second resistor and said second current source, a first node between said first resistor and said first diode generating said first attenuation signal, a second node between said second resistor and said second diode generating said second attenuation signal.
8. A differential amplifier comprising: first and second power supply terminals; a current switch having a first current source connected to said second power supply terminal and first and second transistors connected commonly to said first current source, said first and second transistors being controlled by first and second input signals, respectively, a first load amplifier connected between said first power supply terminal and said first transistor and having an amplification larger than 1; a second load amplifier connected between said first power supply terminal and said second transistor and having an amplification larger than 1; a first emitter follower connected to said first power supply terminal and to said first load amplifier, said first emitter follower having an amplification of approximately 1 and generating a first output signal; a second emitter follower connected to said first power supply terminal and to said second load amplifier, said second emitter follower having an amplification of approximately 1 and generating a second output signal; and a feedback circuit, connected to said first and second emitter followers and said second power supply terminal, for attenuating said first and second output signals to generate first and second attenuation signals, said first and second attenuation signals being transmitted to said second and first load amplifiers, respectively, thus substantially reducing an amplification of said first and second transistors to less than 1, wherein said feedback circuit includes a first resistor connected to an output of said first emitter follower, a second resistor connected to an output of said second emitter follower, diode means connected to said second power supply terminal, a first diode connected between said first resistor and said diode means, and a second diode connected between said second resistor and said diode means, a first node between said first resistor and said first diode generating said first attenuation signal, a second node between said second resistor and said second diode generating said second attenuation signal.
9. A differential amplifier comprising: first and second power supply terminals; a current switch having a first current source connected to said second power supply terminal and first and second transistors connected commonly to said first current source, said first and second transistors being controlled by first and second input signals, respectively, a first load amplifier connected between said first power supply terminal and said first transistor and having an amplification larger than 1; a second load amplifier connected between said first power supply terminal and said second transistor and having an amplification larger than 1; a first emitter follower connected to said first power supply terminal and to said first load amplifier, said first emitter follower having an amplification of approximately 1 and generating a first output signal; a second emitter follower connected to said first power supply terminal and to said second load amplifier, said second emitter follower having an amplification of approximately 1 and generating a second output signal; and a feedback circuit, connected to said first and second emitter followers and said second power supply terminal, for attenuating said first and second output signals to generate first and second attenuation signals, said first and second attenuation signals being transmitted to said second and first load amplifiers, respectively, thus substantially reducing an amplification of said first and second transistors to less than 1; wherein said feedback circuit includes a first resistor connected to an output of said first emitter follower, a second resistor connected to an output of said second emitter follower, a second current source connected to said second power supply terminal, a third resistor connected between said first resistor and said second current source, and a fourth resistor connected between said second resistor and said second current source, a first node between said first resistor and said third resistor generating said first attenuation signal, a second node between said second resistor and said fourth resistor generating said second attenuation signal.
10. A differential amplifier comprising: first and second power supply terminals; a current switch having a first current source connected to said second power supply terminal and first and second transistors connected commonly to said first current source, said first and second transistors being controlled by first and second input signals, respectively, a first load amplifier connected between said first power supply terminal and said first transistor and having an amplification larger than 1; a second load amplifier connected between said first power supply terminal and said first transistor and having an amplification larger than 1; a second load amplifier connected between said first power supply terminal and said second transistor and having an amplification larger than 1; a first emitter follower connected to said first power supply terminal and to said first load amplifier, said first emitter follower having an amplification of approximately 1 and generating a first output signal; a second emitter follower connected to said first power supply terminal and to said second load amplifier, said second emitter follower having an amplification of approximately 1 and generating a second output signal; and a feedback circuit, connected to said first and second emitter followers and said second power supply terminal, for attenuating said first and second output signals to generate first and second attenuation signals, said first and second attenuation signals being transmitted to said second and first load amplifiers, respectively, thus substantially reducing an amplification of said first and second transistors to less than 1, wherein said feedback circuit includes a first resistor connected to an output of said first emitter follower, a second resistor connected to an output of said second emitter follower, diode means connected to said second power supply terminal, a third resistor connected between said first resistor and said diode means, and a fourth resistor connected between said second resistor and said diode means, a first node between said first resistor and said third resistor generating said first attenuation signal, a second node between said second resistor and said fourth resistor generating said second attenuation signal.
11. A differential amplifier comprising: first and second power supply terminals; a current switch having a first current source connected to said second power supply terminal and first and second transistors connected commonly to said first current source, said first and second transistors being controlled by first and second input signals, respectively, a first load amplifier connected between said first power supply terminal and said first transistor and having an amplification larger than 1; a second load amplifier connected between said first power supply terminal and said second transistor and having an amplification larger than 1; a first emitter follower connected to said first power supply terminal and to said first load amplifier, said first emitter follower having an amplification of approximately 1 and generating a first output signal; a second emitter follower connected to said first power supply terminal and to said second load amplifier, said second emitter follower having an amplification of approximately 1 and generating a second output signal; and a feedback circuit, connected to said first and second emitter followers and said second power supply terminal, for attenuating said first and second output signals to generate first and second attenuation signals, said first and second attenuation signals being transmitted to said second and first load amplifiers, respectively, thus substantially reducing an amplification of said first and second transistors to less than 1, wherein said feedback circuit includes a second current source connected between an output of said first emitter follower and said second power supply terminal, and a third current source connected between an output of said second emitter follower and said second power supply terminal, and a third current source connected between an output of said second emitter follower and said second power supply terminal, first, second and third resistors connected between the output of said first emitter follower and the output of said second emitter follower, a first node between said first resistor and said second resistor generating said first attenuation signal, a second node between said second resistor and said third resistor generating said second attenuation signal.
Patent Citations (2)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3399357 | 1968-08-01 | Weilerstein | |
| JPX2-223209 | 1990-09-01 |