System and Method for Deinterleaving Digital Data

1. Field of the Invention

The present invention relates generally to cellular communication systems, and more particularly to deinterleaver circuits for use in cellular communication systems.

2. Related Art

North American Standard IS95 is a cellular telephone communication standard. Standard IS95 specifies the use of Code Division Multiple Access (CDMA), which is a form of modulation in which digital information is encoded and interleaved in an expanded bandwidth format (i.e., spread spectrum).

In a cellular communication environment, signal strength varies with location and movement of the mobile stations. Such variation in signal strength can result in high error rates, which can significantly adversely affect the quality of communication. Standard IS95 provides an error correction scheme based on convolutional encoding/decoding and interleaving/deinterleaving to minimize such signal interference and errors.

In a cellular communication system, a base station transmits a stream of data packets to a mobile station (i.e., a cellular telephone) as follows. The base station receives a digital data packet (a sequence of digitized audio data, for example) from a data source, such as a telephone network. The base station encodes and interleaves the data packet.

The interleaving process operates to reorder the data elements in the data packet. For example, assume that the data elements in a 5-element data packet are originally ordered as follows: D1, D2, D3, D4, D5. After interleaving, the data elements in the data packet may be reordered as follows: D2, D4, D1, D5, D3 (note that this particular reordering sequence is used only for illustrative purposes).

The base station transmits (i.e., broadcasts) the encoded and interleaved data packet to the mobile station. The mobile station deinterleaves and decodes the digital data to thereby obtain the original data packet.

The deinterleaving process operates to reorder the data elements in the interleaved data packet such that these data elements are ordered as they were in the original data packet. In the above example, the data elements in the interleaved data packet were ordered as follows: D2, D4, D1, D5, D3. After deinterleaving, the data elements in the deinterleaved data packet are reordered as follows: D1, D2, D3, D4, D5.

The deinterleaved and decoded data packet is then processed in a well known manner. For example, the data packet may be transferred to audio components of the mobile station.

The interleaving process (in conjunction with convolutional encoding) operates to lower burst error rates. A burst error is a grouping of errors that occur in a relatively short period of time, as opposed to errors that occur over a long time period. Burst errors are errors that affect consecutive bits in a transmitted data packet, as opposed to random errors that occur over the whole data stream.

The interleaving process spreads (in time) the effects of any potential burst errors. Specifically, the interleaved data packet transmitted from the base station to the mobile station may be subject to burst errors. However, such errors are spread in time after deinterleaving by the mobile station. By lowering the burst error rate, the ability for error correction using convolutional coding is enhanced.

FIG. 3 is a block diagram of a conventional mobile station 360. An antenna 314 receives the data packet transmitted by the base station, and stores this data packet in an input buffer 310, which forms part of a deinterleaver 354. A deinterleaving module 320 accesses the input buffer 310 and retrieves the data packet's data elements according to a deinterleaving sequence which is complementary to the interleaving sequence (i.e., the order in which the data elements were ordered during the interleaving process in the base station). These data elements are stored in an output buffer 330 in the order in which they were retrieved from the input buffer 310. A convolutional decoder 356 retrieves the deinterleaved data elements from the output buffer 330, and then decodes these data elements to obtain the original data packet. The decoded data packet is then transferred to audio components 358 (for example) for processing.

The interleaving and deinterleaving processes shall now be considered in greater detail by referring to the above example, where the data elements in the data packet were originally ordered as follows: D1, D2, D3, D4, D5, and the data elements in the interleaved data packet (that is, after interleaving in the base station) were reordered as follows: D2, D4, D1, D5, D3. Thus, the interleaving sequence specifies that the data element in position 1 of the original data packet is stored in position 3 of the interleaved data packet. The data element in position 2 of the original data packet is stored in position 1 of the interleaved data packet. The complete interleaving sequence is as shown in Table 1:

In this example, the deinterleaving sequence specifies that the data element in position 2 of the interleaved data packet is stored in position 1 of the deinterleaved data packet (that is, memory location 1 of the output buffer 330). The data element in position 4 of the interleaved data packet is stored in position 2 of the deinterleaved data packet (that is, memory location 2 of the output buffer 330). The complete deinterleaving sequence is as shown in Table 2:

Conventionally, the deinterleaving module 320 deinterleaves the data packet stored in the input buffer 310 using complex computation techniques. Such complex computation techniques involve a mathematical formula which may be implemented using a specialized circuitry or software implementation. Such circuitry is large in area and consumes great amounts of electrical current. Accordingly, deinterleaving using complex computation techniques places a burden on system resources, which are particularly limited in mobile stations.

Alternatively, the deinterleaving module 320 conventionally deinterleaves the data packet stored in the input buffer 310 using a look-up table, such as Table 2 shown above. The look-up table is implemented using specialized circuitry. Such circuitry is typically large in area. Accordingly, deinterleaving using a look-up table also places a burden on system resources.

The present invention overcomes the above described drawbacks. The present invention is directed to system and method for deinterleaving digital data. The present invention does not use complex computation techniques or a look-up table requiring large circuitry area and/or high current consumption to perform this deinterleaving function. The system provides for a deinterleaver which reorders elements of an interleaved digital data sequence to obtain an original digital data sequence. The deinterleaver comprises a data buffer for storing the interleaved digital data sequence; a decoder to generate a first address of a desired data element of the interleaved digital data sequence, the first address corresponding to a position of the desired data element in the original digital data sequence; an address twister to translate the first address to a second address corresponding to a position of the desired data element in the interleaved digital data sequence; and means for accessing the data buffer according to the second address to retrieve the desired data element of the original digital data sequence. This method of deinterleaving digital data is simple to implement and requires minimal circuitry area and current consumption.

Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements.

The present invention will be described with reference to the accompanying drawings, wherein:

FIG. 1 is a block diagram of a cellular communication system;

FIG. 2 is a block diagram of a base station and a mobile station;

FIG. 3 is a block diagram of a mobile station having a conventional deinterleaver;

FIG. 4 is a block diagram of a deinterleaver according to a preferred embodiment of the present invention; and

FIG. 5 illustrates an address twister according to a preferred embodiment of the present invention.

FIG. 1 is a block diagram of a cellular communication system 102 which includes a telephone network 140, a switching office 130, a plurality of cells 150, a plurality of base stations (cell sites) 110, and a plurality of mobile stations (wireless telephones, such as cellular telephones) 360. The telephone network 140 sends digital data packets (in streams of digitized audio data) to the switching office 130. The switching office 130 then routes the digital data packets to the base stations 110. Finally, the digital data packets are transmitted (broadcasted) from the base stations 110 to the mobile stations 360.

Communication from the mobile stations 360 to the telephone network 140 is done in a similar but reversed manner. Thus, the encoders, decoders, interleavers, and deinterleavers in the base stations 110 and the mobile stations 360 perform similar functions. Their respective circuitries, however, are different due to the different requirements, functionalities, and limitations between the base and mobile stations. These limitations include, for example, size and power requirements of the mobile stations 360. The present invention is directed to new deinterleavers and methods of deinterleaving to minimize IC (integrated chip) area and power consumption in the mobile stations 360.

Referring to FIG. 2, the base station 110 includes a convolutional encoder 304 and an interleaver 308. The mobile station 360 includes a deinterleaver 354, a convolution decoder 356, and audio components 358. The base and mobile stations communicate with each other as follows. The base station 110 receives data packets 302 from a telephone network 140 via a switching office 130. The data packets 302 are then encoded in the convolutional encoder 304 in a well known manner according to Standard IS95 to provide for error-correction. The encoded data packets 306 are then interleaved in the interleaver 308. This is done by reordering data elements of the encoded data packets 306. The interleaving process (in conjunction with convolutional encoding) operates to lower burst error rates. The base station 110 then broadcasts the interleaved data packet's data elements 309 to the mobile station 360 via transmitter 312.

The mobile station 360 receives the interleaved data elements 309 via receiver 314. The interleaved data elements 309 are deinterleaved by the deinterleaver 354 (such deinterleaving is discussed below). The deinterleaved data elements 315 are next sent to the convolutional decoder 356 for decoding. The convolutional decoder 356 decodes the deinterleaved data elements 315 to obtain the original data packets 302. The data packets 302 are then processed in a well known manner by audio components 358.

FIG. 4 is a block diagram of the mobile station 360 which includes a deinterleaver 410 according to a preferred embodiment of the present invention. Note that the convolutional decoder 356 is shown as being part of the deinterleaver 410, but it may alternatively be distinct from the deinterleaver 410. In FIG. 4, the interleaved data packet's data elements 309 from the base station 110 are received by the receiver 314. The interleaved data elements 309 are stored in an input buffer 310 of the deinterleaver 410. The interleaved data elements 309 stay in the input buffer 310 until retrieved by the convolutional decoder 356. The convolutional decoder 356 retrieves data from the input buffer 310 by generating addresses 340 that address such data. However, in the present invention, the convolutional decoder 356 is not aware of the interleaving operation performed by the interleaver in the base station 110. Consequently, the convolutional decoder 356 does not know that the data elements are stored in the input buffer 310 in an interleaved sequence. Accordingly, the addresses 340 generated by the decoder 356 correspond to the positions of the data elements 309 before they were interleaved by the interleaver in the base station 110. For example, the addresses 340 generated by the decoder are as follows: 1, 2, 3, 4, etc.

The present invention provides an address twister 420 which translates the addresses 340 generated by the decoder 356 into actual addresses 430 of the interleaved data elements 309 as these data elements are stored in the input buffer 310. This simplifies the design and operation of the deinterleaver. For example, suppose that the data elements in the data packet were originally ordered as follows: D1, D2, D3, D4, D5. Also suppose that the interleaver in the base station 110 interleaved these data elements according to the interleaving sequence shown in Table 1. According to the present invention, the address twister 420 translates the addresses 340 generated by the decoder 356 in accordance with that shown in Table 2. Thus, if the decoder 356 sends the address "1" to the twister 420, the twister 420 translates this address to "2". Similarly, if the decoder 356 sends addresses "2", "3", "4", and "5" to the twister 420, the twister 420 would translate these addresses to "4", "1", "5", and "3", respectively.

The sequence shown in Table 1 is provided by way of example only. Preferably, the interleaver 308 in the base station 110 and the deinterleaver 410 in the mobile station 360 operate according to the interleaving and deinterleaving sequences specified by IS95.

Tables 501 and 502 illustrate the deinterleaving sequence according to IS95. In Tables 501 and 502, the positions of the data elements are shown from 1-384. However, the actual positions of the data elements are normally 0-383. Therefore, to obtain the correct locations of the data elements in the input buffer 310 according to Tables 501 and 502, a "1" must be subtracted from the values shown. For example, the deinterleaving sequence according to Tables 501 and 502 specifies that position "1", shown as "2" as indicated by reference number 510 (2-1=1; see Table 502), of the interleaved data packet is stored in position "192", shown as "193" as indicated by reference number 520 (193-1=192; see Table 501), of the deinterleaved data packet (that is, memory location "192" of the input buffer 310). The data element in position "2", shown as "3" as indicated by reference number 530 (3-1=2), of the interleaved data packet is stored in position "96", shown as "97" as indicated by reference number 540 (97-1=96), of the deinterleaved data packet (that is, memory location "96" of the input buffer 310). The complete deinterleaving sequence is as shown in Tables 501 and 502 below.

The manner in which the address twister 420 translates the address 340 so as to deinterleave in accordance with IS95 shall now be described. The preferred implementation of the twister 420 is based on the following observation made by the inventor: if each address 340 generated by the decoder 356 is expressed as a nine bit binary value b.sub.8 -b.sub.0 (b.sub.0 is the LSB), then in order to generate the correct address for this data element as stored in the input buffer 310, it is necessary to assign different weighting values of the bits b.sub.8 through b.sub.0 (i.e., non-binary weighting values) as shown in Table 3. The weightings shown in Table 3 are specific to IS95. It should be understood that the present invention is adapted and intended to operate according to other interleaving/deinterleaving standards and/or definitions. The weightings for such other standards/definitions will be apparent to persons skilled in the relevant art based on the discussion contained herein.

For example, if data element "3" (with respect to the positioning of data elements in the original, non-interleaved data packet) is needed, the decoder 356 will generate address "3" (b.sub.0 =1, b.sub.1 =1, b.sub.2 -b.sub.8 =0). The address twister 420 assigns a weight of "192" to bit b.sub.0, instead of "1", and assigns a weight of "96" to bit b.sub.1, instead of "2". Thus, a new address is produced: 192+96="288". This is indeed the position at which data element "3" is stored in the input buffer 310 in accordance with IS95. This can be verified by the deinterleaving sequence of Tables 501 and 502, where the address "3" is shown as "4", as indicated by reference number 550 (4-1=3), and the new address "288" is shown as "289", as indicated by reference number 560 (288+1=289).

Implementation of the address twister 420 is also based on the inventor's observation that the required weightings can be decomposed as shown in the column called "decomposition" in Table 3. This is further described below.

FIG. 5 illustrates an address twister 420 of a preferred embodiment of the present invention. The twister 420 comprises a well known 8-bit binary adder 600 (which operates to add two 8-bit binary numbers) and a circuit 650 for adding an extra weighted value of "4". The twister 420, by assigning different weightings to addresses 340 (having bits b.sub.0 -b.sub.8), generates addresses 430 to retrieve the desired deinterleaved data elements 315 from the input buffer 310.

The 8-bit binary adder 600 provides for 16 inputs 610 and 9 outputs 611. The 16 inputs 610 correspond to 2 weighted inputs each of 1, 2, 4, 8, 16, 32, 64, and 128. The 9 outputs 611 carry the address 430 generated by the twister 420 for retrieving the deinterleaved data elements 315 from the input buffer 310. The address lines b.sub.8 -b.sub.0 340 from the convolutional decoder 356 are assigned to the inputs of the binary adder 600 as shown in FIG. 5. For example, address line b.sub.0 is assigned to one of the weighted input of 128 and one of the weighted input of 64. Thus, if data element "1" is needed, the decoder 356 will generate address "1" (b.sub.0 =1 and all others are 0). Since b.sub.0 is assigned to each of the weighted inputs of 128 and 64, the twister 420 will generate an address of 128+64="192", which is the location of the desired deinterleaved data element corresponding to the address "1" from the decoder 356 (see items 510 and 520 in Tables 501 and 502, respectively; recall that it is necessary to subtract "1" from items 510 and 520).

According to the "decomposition" of Table 3, however, an additional weight of "4" is needed to accommodate all the weighting values of the twister 420. Specifically, address lines b.sub.4, b.sub.5, and b.sub.8 each requires a weighted input of 4. Since the binary adder 600 provides for only 2 weighted inputs of 4, the circuit 650 is provided to realize the third weighted input of 4. The way that circuit 650 provides an additional weight of "4" is described below.

The assignments of the weighted inputs 610 of the binary adder 600 to the bits of the address 340 shall now be described in greater detail. A first weight of 1 is assigned to address line b.sub.6 and a second weight of 1 is grounded. A first weight of 2 is assigned to address line b.sub.7 and a second weight of 2, in combination with a first weight of 4, is assigned to address line b.sub.5 through the circuit 650. A second weight of 4, in combination with a first weight of 8, is assigned to address line b.sub.4. A third weight of 4 is assigned to address line b.sub.8 through the circuit 650. A second weight of 8, in combination with a first weight of 16, is assigned to address line b.sub.3 through the circuit 650. A second weight of 16, in combination with a first weight of 32, is assigned to address line b.sub.2. A second weight of 32, in combination with a first weight of 64, is assigned to address line b.sub.1 through the circuit 650. A second weight of 64, in combination with a first weight of 128, is assigned to address line b.sub.0. Finally, a second weight of 128 is assigned to address lines b.sub.1, b.sub.3, b.sub.8, and b.sub.5 through the circuit 650.

The circuit 650 includes five AND gates (661, 662, 663, 664, and 665) and five Exclusive-OR gates (671, 672, 673, 674, and 675) that are connected as shown in FIG. 5 to generate an additional weight of "4". For those skilled in the art of digital logic design, it will be apparent that the circuit 650 comprises five cascaded one bit adders (AND gates 661, 662, 663, 664, and 665) with each carry bit fed to the next stage and the sum bits fed to the 8-bit binary adder 600 with the exception of the last carry which is fed to the 8-bit binary adder's weighted input 128, as indicated by reference number 624. It will also be apparent that through circuit 650, b.sub.1 acts on the weighted inputs 64 and 32 (as indicated by reference numbers 622 and 620, respectively), b.sub.3 on weighted inputs 16 and 8 (as indicated by reference numbers 618 and 616, respectively), b.sub.8 on weighted input 4 (as indicated by reference number 614), and b.sub.5 on weighted inputs 4 and 2 (as indicated by reference numbers 614 and 612, respectively). For example, if data element "32" is needed, the decoder 356 will generate address "32" (b.sub.5 =1 and all others (b.sub.0 -b.sub.4, b.sub.6 -b.sub.8) are 0). The address twister 420 takes bit b.sub.5 with weight "2" (input 612). According to the circuit 650, since b.sub.5 =1 and b.sub.8 =0, these two address bits are exclusive-ORed in gate 671 to generate an additional weighted output of "4" (input 614). This weighted output of "4" is added with the weighted output of "2" and, thus, a new address is produced: 4+2="6". This is the position at which the data element corresponding to address "32" is stored in the input buffer 310. This can be verified by the deinterleaving sequence of Tables 501 and 502, where the address "32" is shown as "33", as indicated by reference number 570 (33-1=32), and the new address "6" is shown as "7", as indicated by reference number 580 (7-1=6). Note that the circuit 650 is connected in such a manner that since b.sub.1 and b.sub.3 are both "0" in the above example, they do not generate any additional weighted outputs for the new address.

In another example, if data element "266" is needed, the decoder 356 will generate address "266" (b.sub.1, b.sub.3, and b.sub.8 =1 and b.sub.0, b.sub.2, b.sub.4, b.sub.5, b.sub.6, and b.sub.7 =0). Since b.sub.5 =0, it does not generate any additional weighted inputs for the new address. Next, b.sub.5 ("0") and b.sub.8 ("1") are exclusive-ORed in gate 671 to generate a weighted output of "4" (input 614). b.sub.5 and b.sub.8 are then ANDed 661 to give an output of "0"; this output is exclusive-ORed in gate 672 with b.sub.3 ("1") to generate a weighted output of "8" (input 616). The output of the AND gate 661 ("0") and b.sub.3 ("1") are next ANDed in gate 662 to give an output of "0"; this output is exclusive-ORed in gate 673 with b.sub.3 to generate a weighted output of "16" (input 618). The output of the AND gate 662 ("0") and b.sub.3 ("1") are ANDed in gate 663 to give an output of "0"; this output is exclusive-ORed in gate 674 with b.sub.1 ("1") to generate a weighted output of "32" (input 620). Next, the output of the AND gate 663 ("0") and b.sub.1 ("1") are ANDed in gate 664 to give an output of "0"; this output is exclusive-ORed in gate 675 with b.sub.1 ("1") to generate a weighted output of "64" (input 622). Finally, the output of the AND gate 664 ("0") and b.sub.1 ("1") are ANDed in gate 665 to give an output of "0". Thus, a new address is produced by summing up all the weighted outputs: 4+8+16+32+64="124". This is the position at which the data element corresponding to address "266" is stored in the input buffer 310. This can be verified by the deinterleaving sequence of Tables 501 and 502, where the address "266" is shown as "267", as indicated by reference number 590 (267-1=266), and the new address "124" is shown as "125", as indicated by reference number 595 (125-1=124). Therefore, the binary adder 600 and the circuit 650 are used to realize the address twister 420 based on the required weightings as shown in the "decomposition" of Table 3.

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.