Clamp Circuit and Method for Detecting an Activation of Same

The present invention relates, in general, to using a clamp circuit to protect a semiconductor device, and more particularly, to detecting the status of the clamp circuit.

Power semiconductor devices are used in high power applications such as automotive electronics, machine automation, and the like. For example, a power semiconductor device such as a power metal oxide semiconductor field effect transistor (MOSFET) is frequently used to switch an inductive load. When the power MOSFET is switched off, the inductive energy stored in the inductive load generates a surge in the drain voltage of the power MOSFET. A drain-gate clamp is typically employed to protect the power MOSFET from an avalanche stress induced failure that may be caused by such a voltage surge. The clamp diode has an avalanche voltage slightly less than that of the power MOSFET. When the drain-source voltage of the power MOSFET rises above the avalanche voltage of the clamp diode, a current flows through the clamp diode. The current activates the power MOSFET by developing a voltage across a resistor placed between the gate and source electrodes of the power MOSFET. The power MOSFET is turned on and dissipates all of the inductive energy in a less stressful conduction mode. A blocking diode is usually placed in series with the drain-gate clamp diode to block current flow from the gate to the drain of the power MOSFET.

Activation of the clamp circuit when switching off the power MOSFET indicates that the inductive load is intact. A malfunctioning inductive load, such as an open load or a shorted load, does not store inductive energy and, therefore, cannot activate the clamp circuit. Therefore, detecting the activation of the clamp circuit provides a diagnosis of the state of the inductive load as well as the state of the clamp circuit.

One approach for inferring the clamp circuit activation is to detect when the power MOSFET drain voltage exceeds a predetermined value. The approach uses a voltage divider to scale the drain voltage of the power MOSFET. The scaled drain voltage is transmitted to a comparator and compared with a reference voltage. The comparator generates an output signal when the scaled drain voltage exceeds the reference voltage. This approach does not directly detect the activation of the clamp circuit, but detects whether the drain voltage of the power MOSFET reaches a predetermined value. It is possible to have a drain voltage sufficient to generate the output signal but insufficient to activate the clamp circuit. It is also possible for the clamp circuit to be activated by a drain voltage that is insufficient to generate the output signal., Furthermore, because this approach is sensitive to the supply voltage level, the reference voltage may need to be adjusted whenever the supply voltage changes. In addition, the voltage divider is directly connected to the drain of the power MOSFET, where the voltage may reach a very high value when switching off the power MOSFET. The voltage divider also increases the drain leakage current. In a battery application where the load remains connected to the battery, any drain leakage is undesirable.

Accordingly, it would be advantageous to have a method for detecting the activation of a clamp circuit. It would be of further advantage for the method to be simple and reliable, and for the clamp circuit to have minimum current leakage and be suitable for manufacture using conventional manufacturing techniques.

FIG. 1 illustrates a schematic diagram of a clamp circuit in accordance with a first embodiment of the present invention; and

FIG. 2 illustrates a schematic diagram of a clamp circuit in accordance with a second embodiment of the present invention.

Generally, the present invention provides a clamp circuit and a method for using the clamp circuit to protect a transistor from destructive voltages. In one embodiment, the present invention provides a method for detecting the activation of the clamp circuit when switching off the transistor which is coupled to an inductive load, thereby providing a diagnosis of the clamp circuit and the inductive load.

FIG. 1 illustrates a schematic diagram of a clamp circuit 10 in accordance with a first embodiment of the present invention. Clamp circuit 10 protects a power metal oxide semiconductor field effect transistor (MOSFET) 12 from destructive voltages. Power MOSFET 12 has a gate electrode coupled for receiving a control signal at a node 20 and a source electrode connected to a node 14. Node 14 is connected to, for example, a ground potential which serves as a reference potential. The gate electrode of power MOSFET 12 is further coupled to node 14 via a current switch 18. Although FIG. 1 illustrates current switch 18 as a series combination of a switch 17 and a current source 19, it should be understood that this is not a limitation of the present invention. Other suitable structures for current switch 18 include a single transistor, a switch in a series connection with a transistor, two transistors in a series connection, or the like. It should be understood that the present invention is not limited to providing protection for a power MOSFET as illustrated in FIG. 1. Power MOSFET 12 in clamp circuit 10 can be replaced by, for example, a bipolar transistor, an insulated gate bipolar transistor, a metal semiconductor field effect transistor, or the like. When interchanging bipolar transistors with field effect transistors, it should be noted that for a field effect transistor, a gate electrode serves as a control electrode of the transistor, and a source electrode and a drain electrode serve as current conducting electrodes; for a bipolar transistor, a base electrode serves as a control electrode of the transistor, and an emitter electrode and a collector electrode serve as current conducting electrodes.

Clamp circuit 10 also includes a clamping element 16 having a first clamping terminal connected to a drain electrode of power MOSFET 12 and a second clamping terminal coupled to the gate electrode of power MOSFET 12 via a current mirror 22 and a Zener diode 24. Clamping element 16 includes a blocking diode 15 and a Zener diode 11. Blocking diode 15 has an anode electrode serving as the first clamping terminal of clamping element 16 and a cathode electrode connected to a cathode electrode of Zener diode 11. An anode electrode of Zener diode 11 serves as the second clamping terminal of clamping element 16. It should be noted that the numbers of blocking diodes and Zener diodes in clamping element 16 and the number of Zener diodes represented by Zener diode 24 are not limited to those illustrated in FIG. 1. However, at least one blocking diode is needed to block current flowing from the gate electrode to the drain electrode of power MOSFET 12. The number of Zener diodes in clamping element 16 and the number of Zener diodes represented by Zener diode 24 determines the clamping voltage of clamp circuit 10. The diodes in clamping element 16 and the diodes represented by Zener diode 24 are oriented so that the current flows through a Zener diode from its cathode electrode to its anode electrode and through a blocking diode from its anode electrode to its cathode electrode when clamp circuit 10 is activated.

Current mirror 22 includes two p-channel insulated gate field effect transistors (FET) 21 and 23. A source electrode of FET 21 and a source electrode of FET 23 form a common terminal of current mirror 22 and are connected to the second clamping terminal of clamping element 16. A drain electrode of FET 21 serves as an input terminal of current mirror 22 and is connected to the gate electrode of power MOSFET 12 via Zener diode 24. A gate electrode of FET 21 and a gate electrode of FET 23 are connected to the drain electrode of FET 21. A drain electrode of FET 23 serves as an output terminal of current mirror 22 and is connected to node 14 via a reference current source 28. The input terminal of a current mirror is also referred as the reference terminal. It should be understood that the structure of current mirror 22 is not limited to that illustrated in FIG. 1. Current mirror 22 may be replaced by any current mirror having a current flowing into its common terminal. In addition, FETs 21 and 23 are not limited to being p-channel insulated gate field effect transistors. For example, FET 21 and FET 23 may be replaced by two PNP bipolar transistors. However, it should be noted that the type of FET 23 should be the same as the type of FET 21, i.e., if FET 21 is a p-channel insulated gate field effect transistor, so is FET 23.

Current source 28 is designed to generate a reference current proportional to the current generated by current source 19. This is achieved by deriving the reference current and the current in current source 19 from one biasing element. In one example, current source 19 and reference current source 28 are related to each other through a current mirror.

Clamp circuit 10 further includes a voltage detector 32 having an input terminal connected to the output terminal of current mirror 22 and an output terminal 40 coupled for transmitting an output signal. Voltage detector 32 is illustrated in FIG. 1 as including two inverters 31 and 33. This should not be interpreted as a limitation of the present invention. For example, voltage detector 32 can include a single inverter, a single buffer, or combinations thereof.

In operation, an inductive load 34 such as, for example, a solenoid, is connected to clamp circuit 10 at the drain electrode of power MOSFET 12. Inductive load 34 is also connected to a node 36, which in turn is coupled for receiving a potential such as, for example, a supply voltage, V.sub.DD. When a control signal places power MOSFET 12 in a non-conductive state and closes switch 17, the inductive energy stored in inductive load 34 is released and raises the drain voltage of power MOSFET. This phenomenon is also referred as an inductive fly-back. When the drain voltage of power MOSFET 12 reaches a clamping voltage, a clamping current flows through clamping element 16 and current mirror 22. The clamping current continues to rise until a switching current in Zener diode 24 exceeds the current generated by current source 19. As those skilled in the art are aware, current source 19 will develop a voltage across the gate and source electrodes of power MOSFET 12 and thereby switch power MOSFET 12 into a conductive state. Power MOSFET 12 remains in the conductive state until the inductive energy stored in inductive load 34 is dissipated.

For clamp circuit 10, the clamping voltage is the sum of the total avalanche voltage of the Zener diodes in clamping element 16 and Zener diode 24, the voltage across the blocking diode in clamping element 16, the voltage across the source and drain electrodes of FET 21, and the voltage across current switch 18. Activation of clamp circuit 10 occurs when the switching current in Zener diode 24 exceeds the current generated by current source 19 and switches power MOSFET 12 on.

Current mirror 22 generates an output current in the drain electrode of FET 23. The output current of current mirror 22 is proportional to the switching current, wherein the coefficient of proportionality is equal to the ratio of the channel width divided by the channel length (W/L) of FET 23 to W/L of FET 21. The reference current in reference current source 28 is designed to be proportional to the current in current source 19, where the coefficient of proportionality is the same as that of the output current of current mirror 22 to the switching current in the input terminal of current mirror 22. Thus, the output current of current mirror 22 exceeds the reference current when clamp circuit 10 is activated. In response to the output current of current mirror 22 exceeding the reference current, reference current source 28 develops a voltage at the input terminal of voltage detector 32, which in turn generates a logical high signal at output terminal 40 indicating the activation of clamp circuit 10.

FIG. 2 illustrates a schematic diagram of a clamp circuit 50 in accordance with a second embodiment of the present invention. Clamp circuit 50 protects a power MOSFET 52. Power MOSFET 52 has a gate electrode coupled for receiving a control signal at a node 60, a source electrode connected to a node 54, and a drain electrode coupled for receiving a load signal. Node 54 is connected, for example, to a ground potential which serves as a reference potential. The gate electrode of power MOSFET 52 is further coupled to node 54 via a current switch 58. Although FIG. 2 illustrates current switch 58 as a series combination of a switch 57 and a current source 59, it should be understood that this is not a limitation of the present invention. Other suitable structures for current switch 58 include a single transistor, a switch in a series connection with a transistor, two transistors in a series connection, or the like. It should also be understood that the present invention is not limited to providing protection for a power MOSFET as illustrated in FIG. 2. Power MOSFET 52 in clamp circuit 50 can be replaced by, for example, a bipolar transistor, an insulated gate bipolar transistor, a metal semiconductor field effect transistor, or the like.

Clamp circuit 50 also includes a clamping element 56 having a first clamping terminal connected to the drain electrode of power MOSFET 52 and a second clamping terminal coupled to a current mirror 66 via a Zener diode 64. Clamping element 56 includes a blocking diode 55 and a Zener diode 51. Blocking diode 55 has an anode electrode serving as the first clamping terminal of clamping element 56 and a cathode electrode connected to a cathode electrode of Zener diode 51. An anode electrode of Zener diode 51 serves as the second clamping terminal of clamping element 56. It should be noted that the numbers of blocking diodes and Zener diodes in clamping element 56 and the number of Zener diodes represented by Zener diode 64 are not limited to those illustrated in FIG. 2. The total number of Zener diodes determines the clamping voltage of clamp circuit 50. The Zener and blocking diodes in clamping element 56 and the diodes represented by Zener diode 64 are oriented so that the current flows through a Zener diode from its cathode electrode to its anode electrode and through a blocking diode from its anode electrode to its cathode electrode when clamp circuit 50 is activated.

Current mirror 66 includes two NPN bipolar transistors: a mirror transistor 65 and an image transistor 67. A collector electrode of transistor 65 serves as an input or reference terminal of current mirror 66 and is connected to an anode electrode of Zener diode 64. A base electrode of transistor 65 is also connected to the input terminal of current mirror 66. An emitter electrode of transistor 65 and an emitter electrode of transistor 67 are connected together to form a common terminal of current mirror 66, which common terminal is connected to the gate electrode of power MOSFET 52. A base electrode of transistor 67 is connected to the base electrode of transistor 65 and a collector electrode of transistor 67 serves as an output terminal of current mirror 66. It should be understood that the structure of current mirror 66 is not limited to that illustrated in FIG. 2. Current mirror 66 may be replaced by any current mirror having a current flowing out of its common terminal. In addition, transistors 65 and 67 are not limited to being NPN bipolar transistors. For example, transistors 65 and 67 may be replaced by two n-channel insulated gate field effect transistors. However, it should be noted that the type of transistor 65 should be the same as the type of transistor 67, i.e., if transistor 65 is an NPN bipolar transistor, so is transistor 67. When current mirror 66 includes two NPN bipolar transistors as illustrated in FIG. 2, the emitter-base PN junction in transistor 65 serves as a blocking diode. Therefore, blocking diode 55 in clamping element 56 is optional in FIG. 2.

Clamp circuit 50 further includes another current mirror 62. Current mirror 62 has the same structure as current mirror 22 shown in FIG. 1. Current mirror 62 includes two p-channel FETs 61 and 63. A source electrode of FET 61 and a source electrode of FET 63 serve as a common terminal of current mirror 62 and are connected to the second clamping terminal of clamping element 56. A drain electrode of FET 61 serves as an input terminal of current mirror 62 and is connected to the output terminal of current mirror 66. A gate electrode of FET 61 and a gate electrode of FET 63 are connected to the drain electrode of FET 61. A drain electrode of FET 63 serves as an output terminal of current mirror 62. The output terminal of current mirror 62 is connected to a voltage detector 72 and to node 54 via a reference current source 68.

Current source 68 is designed to generate a reference current proportional to the current generated by current source 59. This is achieved by deriving the reference current and the current in current source 59 from one biasing element. In one example, current source 59 and reference current source 68 are related to each other through a current mirror.

Voltage detector 72 has an input terminal connected to the output terminal of current mirror 62. An output terminal 80 of voltage detector 72 is coupled for transmitting an output signal. Voltage detector 72 is illustrated in FIG. 2 as including two inverters 71 and 73. This should not be interpreted as a limitation of the present invention. For example, voltage detector 72 can include a single inverter, a single buffer, or combinations thereof.

In operation, an inductive load 74 such as, for example, a solenoid, is connected to clamp circuit 50 at the drain electrode of power MOSFET 52. Inductive load 74 is also connected to a node 76, which in turn is coupled for receiving a potential such as, for example, a supply voltage, V.sub.DD. A load current flowing through inductive load 74 and power MOSFET 52 stores an inductive energy in inductive load 74. When a control signal places power MOSFET 52 in a non-conductive state and closes switch 57, the inductive energy stored in inductive load 74 is released and raises the drain voltage of power MOSFET 52. As the drain voltage of power MOSFET 52 reaches a clamping voltage, a clamping current flows through clamping element 56 and Zener diode 64. The clamping current continues to rise until a switching current in the common terminal of current mirror 66 exceeds the current in current source 59. As those skilled in the art are aware, current source 59 will develop a voltage across the gate and source electrodes of power MOSFET 52, and thereby switch power MOSFET 52 into a conductive state. Power MOSFET 52 remains in the conductive state until the inductive energy is dissipated.

For clamp circuit 50, the clamping voltage is the sum of the total avalanche voltage of the Zener diodes in clamping element 56 and Zener diode 64, the voltage across the blocking diode in clamping element 56, the voltage across the collector and emitter electrodes of transistor 65, and the voltage across current switch 58. The activation of clamp circuit 50 occurs when the switching current in the common terminal of current mirror 66 exceeds the current generated by current source 59 and switches power MOSFET 52 on.

Current mirrors 66 and 62 generate an output current in the drain electrode of FET 63. The output current is proportional to the clamping current in Zener diode 64, with the coefficient of proportionality equal to the ratio of W/L of FET 63 to W/L of FET 61 multiplied by the ratio of the emitter area of transistor 67 to that of transistor 65. Reference current source 68 is designed to generate a reference current proportional to the current in current source 59, where the coefficient of proportionality is the same as that of the output current of current mirror 62 in the drain electrode of FET 63 to the switching current in the common terminal of current mirror 66. Thus, the output current of current mirror 62 exceeds the reference current when clamp circuit 50 is activated. In response to the output current exceeding the reference current, reference current source 68 develops a voltage at the input terminal of voltage detector 72. Voltage detector 72 in turn generates a logical high digital signal at output terminal 80 indicating the activation of clamp circuit 10.

By now it should be appreciated that a clamp circuit for the protection of a power transistor and a method for detecting the activation of the clamp circuit have been provided. The method in accordance with the present invention uses a current mirror to sense a current in the Zener diode that is sufficient to switch on the power transistor, and thereby ensures that detection occurs when the clamp circuit is activated. The clamp circuit in accordance with the present invention does not require additional voltage or current supplies, and operates independently of the supply voltage. In contrast to the prior art methods for detecting the activation of a clamp circuit, the present invention does not increase the drain leakage current of the power transistor. To minimize the silicon area of the circuit, the p-channel MOSFET mirror in the clamp circuit can be built in a Zener diode stack epitaxy layer. The method is insensitive to the variation in the Zener diode clamp voltage that may be caused by process variation and temperature range variation. Therefore, the present invention provides a simple clamp circuit and reliable method for the diagnostic of the states of the clamp circuit and its inductive load.