System and Method for Performing Wake-Up Operations to a Memory

The present invention is directed to a system and method which ensure that the required number of refresh operations are performed to a memory during a wake-up period after powering on the memory by initializing the refresh count value. More particularly, the system and method compare the refresh count value to a predetermined threshold number and by initializing the refresh count value, the required number of refresh requests will be issued as high priority requests to ensure that the required number of refreshes is executed to the memory after powering on.

In conventional dynamic memory systems, the time that a node reliably stores a bit is referred to as the refresh period. The refresh period is based on the particular dynamic memory specifications. Since the charge stored on a dynamic node decays, it is necessary to sense and refresh the dynamic node within the refresh period. Therefore, dynamic memory systems are generally provided with a refresh circuit which generates a refresh request within the refresh period to ensure that the charge on the dynamic node does not decay and the bit remains reliably stored on the dynamic node.

An example of a known refresh operation for a dynamic memory system is illustrated in FIG. 1. A refresh circuit 10 generates refresh requests at predetermined intervals to the memory controller 20. The predetermined intervals are chosen to be within the refresh period to ensure that data on the dynamic node reliably remains. Conventionally, the predetermined intervals are about 15 .mu.sec. More specifically, the refresh circuit 10 generates an overflow signal at the end of the predetermined intervals. The generated overflow signals act as refresh requests which take priority before all of the other requests from an external processor (not shown). In these known systems, because the refresh requests take priority in the execution by the memory controller 20 before all of requests, the read latency is adversely affected due to the refreshes. For example, in the middle of a large block transfer, a read which conflicts with the refresh will be forced to wait until the refresh is completed because the refresh has priority. The amount of time necessary to complete the refresh is dependent upon the number of banks in the dynamic memory and thereby, the read latency becomes higher as the number of banks is increased.

FIG. 1 further illustrates a power unit 30 for powering on the memory controller 20. Upon powering on a dynamic memory, it is necessary to perform a wake-up operation where the dynamic memory does not operate for a certain amount of time and then a required number of refreshes are sequentially directed to the memory controller 20. Typically, the time period for which the dynamic memory does not receive requests is 200 .mu.sec and a number of refresh cycles is executed by the memory controller 20 for the wake-up operation. The required number of refresh cycles in the wake-up operation are executed so that the sense amplifiers of the dynamic memory are precharged. The required number of refreshes is set by the product's manufacturer and this number is typically 8 refresh cycles. However, in conventional memory controllers, it is usually assumed that the refresh cycles will occur during the reset interval but there is no circuitry for ensuring that the required number of refresh cycles will always occur.

To reduce the amount and complexity of circuitry used for the wake-up operation, it is desired to utilize other circuitry for more than one function for ensuring the required number of refresh cycles is performed. The embodiments of the present invention are directed to utilizing a refresh processor to ensure that the required number of refreshes are performed to a memory with simplified circuitry.

An object of the present invention is to provide a system and controller which ensure that the required number of refreshes are performed to a memory during a wake-up operation after powering on the memory by associating high priority requests with the required number of refreshes generated immediately after the reset interval.

Another object of the present invention is to provide a system and method which prioritize and issue refresh requests to the memory for ensuring that the required number of refreshes is issued to the memory after powering on.

These objects of the present invention are fulfilled by providing a system for powering up a memory, comprising a resetting unit for generating a reset interval in response to powering on the memory, and a refresh counter having a refresh count value which is set to an initialized refresh value upon completing the reset interval to ensure that a required number of refreshes are executed by the memory after powering on the memory. As a result, this system ensures that the required number of refreshes is performed to the memory during the wake-up period after powering on the memory without the use of complicated timing circuitry.

These objects of the present invention are also fulfilled by providing a method for powering on a memory comprising the steps of generating a reset interval in response to powering on the memory, and setting a refresh count value of a refresh counter to an initialized refresh value upon completing said refresh interval to ensure that a required number of refreshes is executed as high priority requests by the memory after powering on. This method processes the required number of refreshes issued immediately after the reset interval as high priority requests to ensure that the required number of refreshes are executed by the memory during the wake-up period in a simplified and reliable manner.

Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this derailed description.

The present invention will become more fully understood from the derailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the invention, wherein:

FIG. 1 illustrates a known system for powering on a memory device;

FIG. 2 illustrates a system for powering on a memory according to an embodiment of the present invention;

FIG. 3 illustrates a more detailed block diagram of the refresh processor illustrated in FIG. 2 for an embodiment of the present invention; and

FIGS. 4(a) and 4(b) illustrate flow charts of the wake-up operation performed after powering on the memory in an embodiment of the present invention.

A system for powering on a memory is shown in FIG. 2 according to an embodiment of the present invention. FIG. 2 illustrates a refresh circuit 100 for generating refresh requests, a refresh processor 110 for receiving the refresh requests from the refresh circuit 100 and issuing the refresh requests with a corresponding priority and a memory controller 120 which receives the refresh requests along with the corresponding priority from the refresh processor 110. The refresh processor 110 generates a high priority, which allows the refresh request to issue before all of the other pending requests to the memory controller 110, and a low priority request, which allows the refresh request to be issued to the memory controller 120 only when there are no other pending requests. The system also includes a power unit 130 for powering on the memory controller 120 and performing initial operations such as initiating the reset interval and the wake-up operation. The memory controller 120 may control a dynamic memory such as a DRAM, a VRAM, or a synchronous DRAM.

The normal operation of the refresh circuit 100 for generating refresh requests at predetermined intervals is similar to the refresh circuit in known DRAM systems. The refresh circuit 100 generates refresh requests at predetermined intervals by generating an overflow signal at the end of each predetermined interval, for example. The predetermined interval is conventionally 15 .mu.sec. The refresh processor 110 receives the refresh requests from the refresh circuit 100 and processes the refresh requests as either high or low priority requests based on the number of pending refresh requests to the memory controller 120. For example, if the number of pending refresh requests is three or more, a high priority request is issued, and if the number of pending refresh requests is less than three, a low priority request is issued. Finally, the memory controller 120 receives the refresh requests and the corresponding priority for possible execution of the refresh requests by the memory controller 120. The refresh requests issued as high priority requests are executed by the memory 120 before all other pending requests and the refresh requests issued as low priority requests are executed by the memory controller 120 only when there are no other pending requests. As a result, the overall forward progress of the refresh operation is guaranteed while the read latency to the memory controller 120 is lowered.

The power unit 130 performs the required wake-up operation after powering on the memory controller 120. The wake-up operation includes a period of time where the memory controller 120 is powered on but does not perform any operations and a time interval where a predetermined number of refresh cycles are executed by the memory controller 120. In a typical example, the initial period of time when the memory controller 120 is powered on doing nothing is 200 .mu.sec followed by 8 refresh cycles. The powering on operation also includes a reset interval which is typically 200 msec. Since the period of time for the reset interval is longer than the required part of the wake-up operation where the memory is powered on and doing nothing, this required part of the wake-up operation is met by the reset interval. After this reset interval, the required number of refresh cycles must be performed to complete the wake-up operation for the memory controller 120.

FIG. 3 shows a more detailed block diagram of the refresh processor 110. FIG. 3 illustrates the refresh processor 110 to include a counter 112, a comparator 114, and a priority issuing unit 116. The counter 112 receives the refresh requests from the refresh circuit 100 at the predetermined intervals and increments the counter 112 by one every time that a refresh request is received. The comparator 114 compares the value of the counter 112 with a predetermined threshold number to determine whether the refresh request should be issued as a high or low priority request. If the value of the counter 112 is determined to be greater than or equal to the predetermined threshold number by the comparator 114, the refresh request is sent to the memory controller 120 from the priority issuing unit 116 as a high priority request. However, if the counter value is determined to be less than the predetermined threshold number by the comparator 114, the priority issuing unit 116 issues the refresh request to the memory 120 as a low priority request. Also, the priority issuing unit 116 decrements the count value after a refresh is executed by the memory controller 120. The priority issuing unit 116 includes an execution detecting portion (not shown) for detecting whether the issued refresh request is executed by the memory controller 120. The refresh processor 110 issues the refresh requests to the memory controller 120 as high and low priority requests based on the number of pending refresh requests such that the high priority refresh requests are executed by the memory 120 before all other pending requests and the low priority refresh requests are executed by the memory 120 only when there fails to be any other pending requests.

To ensure that the required number of refresh cycles are performed during the wake-up operation, the predetermined threshold number is initialized to a start up refresh value upon completion of the reset interval. In a typical example, the predetermined threshold number is set to 3 and the required number for refreshes to be performed is set to 8. Thereby, the value of the counter 112 is initialized to a refresh value of 11. Accordingly, the required wake-up operation is performed by initializing the refresh processor 110 to ensure that the required number of refreshes is executed as high priority requests by the memory 120 after powering on.

FIGS. 4(a) and 4(b) illustrate flow charts of the concurrent processes performed by the refresh controller. In FIG. 4(a), the timer is initialized at step S10 by being reset to zero. At step S20, it is determined whether 15 microseconds have elapsed. If 15 .mu.sec have not elapsed, checking for whether 15 .mu.sec have elapsed at step S20 is repeatedly cycled until the 15 .mu.sec have elapsed. After it is determined at step S20 that the 15 .mu.sec have elapsed, the counter 112 is incremented at step S30. Concurrently with incrementing the counter when the timer overflows, the refresh requests are prioritized as shown in FIG. 4(b). At step S110, the counter 112 is set to the predetermined threshold number+8 (the required number of refresh cycles). It is determined at step S120 whether the counter 112, as incremented in the process shown in FIG. 4(a), is not zero. If the counter 112 is zero, step S120 is repeatedly cycled until the counter 112 is incremented and becomes non-zero. When the counter 112 is determined to be non-zero at step S120, the value of the counter 112 is compared with the predetermined threshold number. If the value of the counter 112 is greater than or equal to the predetermined threshold number, a high priority request is issued at step S140. If the counter is less than the predetermined threshold number, a low priority request is issued at step S150. Next, it is determined at step S160 whether the refresh was performed. If the refresh was not performed, step S160 is repeatedly cycled until the refresh is performed. After performing the refresh at step S160, the counter 112 is decremented by 1 at step S170 and proceeds back to step S120.

The system and method described in the embodiments of the present invention ensure that required number of refresh requests are executed by a memory during a wake-up operation after powering on the memory. The system and method for these embodiments are especially applicable to dynamic memories where the refresh requests make certain that the bits stored at the dynamic node will not decay and thereby remain reliable. Therefore, a counter of a refresh processor is initialized to a refresh value which ensures that the required number of refreshes is executed as high priority requests after powering on the memory. By utilizing the counter of the refresh processor, the complexity of the circuitry is reduced and the required number of refreshes during the wake-up period is more reliably performed.

The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.