Field Edge Manufacture of a T-Gate LDD Pocket Device

1. Field of the Invention

The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of making a T-gate LDD pocket device in the fabrication of integrated circuits.

2. Description of the Prior Art

FIG. 1 illustrates a typical lightly doped drain (LDD) device of the prior art. Gate electrode 16 has been formed over gate silicon oxide layer 14 on the surface of semiconductor substrate 10. Lightly doped regions 20, heavily doped source and drain regions 22, and P+ regions 24 have been ion implanted into the semiconductor substrate at the gate edges.

There are a number of problems with this type of device structure. One problem is that the gate edge is stressed by high electrical field-induced leakage. Also, the thin gate oxide at the gate edge over the source/drain region induces a large capacitance during device operation. This thin gate oxide is easily damaged by electro-static discharge (ESD) at the N-region, and the high heat at the junction edge melts or otherwise adversely affects thin gate silicon oxide and polysilicon. The P+ pocket implantation after the N-implantation degrades the doping concentration of the N- region and reduces channel resistance, saturation current, and device operation speed. An improved LDD pocket device without the aforementioned problems is desired.

When the prior art MOS FET devices are used for ESD protection circuit purposes, these devices are easily damaged at the N- region gate oxide. The prior art gate over the source/drain region is too large. The N- implant will diffuse sideways by process heating, so the gate easily overlaps the N- region. The ESD will cause damage and device failure at the drain edge where the gate silicon oxide will break down due to the high heat developed by the ESD effects.

U.S. Pat. No. 5,108,937 to Tsai et al shows the formation of FOX structures and the removal of some of the FOX structures followed by formation of MOS FET devices. Large tilt angle implantation methods are generally known in the art.

Accordingly, it is a primary object of the invention to provide a process for fabricating an improved LDD pocket integrated circuit device.

It is another object of the present invention to provide a process for fabricating an integrated circuit device with a reduced gate edge electrical field.

It is further object of the invention to provide a process for fabricating an integrated circuit device which reduces the size of the gate over the source/drain capacitor.

Yet another object is to provide a process for fabricating an integrated circuit device with improved gate to drain leakage characteristics.

Yet another object is to provide a process for fabricating an integrated circuit device which protects the N- region from degradation.

A still further object of the invention is to provide a process for fabricating an integrated circuit device with improved device operation speed, channel resistance, and saturation current.

Yet another object of the invention is to provide a T-gate LDD pocket device with reduced gate edge electrical field, improved gate to drain leakage characteristics, and improved device operation speed, channel resistance, and saturation current.

In accordance with the objects of the invention, a new method of field edge manufacturing of a T-gate LDD pocket device integrated circuit is described. Field oxide regions are formed in and on the surface of a semiconductor substrate. The T-gate device will be formed between the field oxide regions. A gate oxide layer is formed on the surface of the semiconductor substrate between the field oxide regions. A layer of polysilicon is deposited over the surface of the gate oxide layer. Portions of the polysilicon layer are etched away leaving the polysilicon layer only between and over the inner edges of the field oxide regions. The remaining polysilicon layer is covered with a photoresist mask wherein the inner edges of the field oxide regions underlying the polysilicon layer are protected by the photoresist mask. The field oxide regions not covered by said photoresist mask are etched away to form the T-gate device. A first set of ions having a first conductivity type are implanted at a tilt angle to form lightly doped regions at the surface of the semiconductor substrate from which the field oxide regions have been removed and underlying the inner edges of the remaining field oxide regions. A second set of ions of the first conductivity type are implanted to form first heavily doped regions at the surface of the semiconductor substrate from which the field oxide regions have been removed. Spacers are formed on the sidewalls of the T-gate device wherein the spacers protect the lightly doped regions from degradation. A third set of ions of a second conductivity type wherein the second conductivity type is opposite to the first conductivity type are implanted to form pocket heavily doped regions underlying the first heavily doped regions to complete the fabrication of the T-gate LDD pocket device in the manufacture of an integrated circuit.

According to the objects of the present invention, a new T-gate LDD pocket device integrated circuit is described. The device comprises a layer of gate silicon oxide on the surface of a semiconductor substrate. A field oxide tip is on either end of the gate silicon oxide layer wherein each field oxide tip has a concave shape with respect to the gate silicon oxide layer. A polysilicon gate overlies the gate silicon oxide layer and the field oxide tips wherein the edges of the gate overlying the field oxide tips are upturned. Silicon oxide spacers are formed on the sidewalls of the gate and the field oxide tips. Lightly doped regions of a first conductivity type lie within the semiconductor substrate underlying the field oxide tips. Heavily doped regions of the first conductivity type lie within the semiconductor substrate on either side of the region underlying the polysilicon gate. Pocket regions of a second conductivity type underlie the heavily doped regions wherein the second conductivity type is opposite to the first conductivity type.

In the accompanying drawings forming a material part of this description, there is shown:

FIG. 1 is a cross-sectional representation of an integrated circuit of the prior art.

FIGS. 2 through 7 are cross-sectional representations of a preferred embodiment of the present invention.

FIG. 8 is a cross-sectional representation of a completed device of the present invention.

FIGS. 2 through 7 illustrate the formation of an N channel FET integrated circuit device. However, it is well understood by those skilled in the art that a P channel FET integrated circuit device could also be formed by simply substituting opposite polarities to those given for the N channel embodiment. Also, a CMOS FET could in a similar way be formed by making both N channel and P channel devices upon the same substrate.

Referring now more particularly to FIG. 2, there is shown a semiconductor substrate 10, preferably composed of silicon having a (100) crystallographic orientation. Field oxide regions 12 are formed as is conventional in the art. The T-gate device of the present invention is to be formed between the field oxide regions. A layer of gate silicon oxide 14 is deposited or thermally grown on the surface of the semiconductor substrate between the field oxide regions to a thickness of between about 80 to 250 Angstroms. A layer of polysilicon 16 is deposited by chemical vapor deposition to a thickness of between about 1500 to 4000 Angstroms and is doped in situ or ion implanted after deposition as is conventional in the art.

Referring now to FIG. 3, the polysilicon layer 16 is etched to form the polysilicon gate overlying the gate silicon oxide layer and the two bird's beak inner edges of the field oxide regions. The polysilicon gate is covered with a photoresist mask. The bird's beak edges of the field oxide regions underlying the polysilicon gate are protected by the photoresist mask. The field oxide regions not covered by the photoresist mask are etched away, as shown in FIG. 4, leaving field oxide tips underlying the edges of the polysilicon gate. The T-gate device has now been formed.

Referring now to FIG. 5, lightly doped regions 20 are formed by implanting ions 19 into the semiconductor substrate at a tilt angle of between about 30.degree. to 45.degree. and rotating the substrate for uniformity. The lightly doped regions extend under the field oxide tips 12. For an N-implantation, phosphorus ions are implanted at a dosage of between about 1 E 13 to 1 E 14 atoms/cm.sup.2 and energy of between about 30 to 80 KeV. For P-implantation, not shown, BF.sub.2 ions are implanted at a dosage of between about 1 E 13 to 1 E 14 atoms/cm.sup.2 and energy of between about 30 to 80 KeV.

Referring now to FIG. 6, ions 21 are implanted at no tilt angle; that is, a tilt angle of between about 0.degree. to 7.degree.; to form heavily doped regions 22. For an N+ implantation, arsenic ions are implanted at a dosage of between about 1 E 15 to 1 E 16 atoms/cm.sup.2 and energy of between about 50 to 100 KeV. For a PMOS integrated circuit device, not shown, BF.sub.2 ions are implanted with a dosage of between about 1 E 15 to 1 E 16 atoms/cm.sup.2 and energy of between about 30 to 80 KeV.

Next, a layer of silicon oxide is deposited over the surface of the semiconductor substrate and etched away to leave spacers 26 on the sidewalls of the T-gate.

Referring now to FIG. 7, the pocket implant will now be performed. The pocket region 24 is formed by implanting ions 23 at a tilt angle of between about 30.degree. to 45.degree. and rotating the substrate to provide for uniform coverage. The pocket regions are formed underlying the heavily doped regions, but not underlying the lightly doped regions because of the presence of the spacers 26. The thick field edge gate oxide and spacer will prevent the pocket regions 24 from degrading the lightly doped regions 20. For a P+ implantation, boron ions are implanted at a dosage of between about 2 E 13 to 4 E 13 atoms/cm.sup.2 and energy of between about 60 to 80 KeV. For a PMOS integrated circuit device, not shown, phosphorus P.sub.31 ions are implanted with a dosage of between about 1 E 13 to 1 E 14 atoms/cm.sup.2 and energy of between about 50 to 80 KeV. This completes formation of the T-gate LDD pocket device. Further processing continues as is conventional in the art to provide electrical connections between device elements of the integrated circuit.

The device formed by the method of the present invention has a reduced gate edge electrical field. The gate length over the source and drain capacitors 22 is reduced. Therefore, the source and drain capacitances are reduced as seen from relationship C=e.sub.o A/d where A is area and d is distance. The thick gate edge gate oxide composed of the field oxide tips and spacers improves gate to drain leakage characteristics or ESD damage at the drain N- region. The surface step difference between the heavily doped 22 and lightly doped 20 regions and the thick gate oxide edge blocks the degradation of the lightly doped region 20 by the pocket region 24.

P+ pocket can keep the N- region that didn't attack by the P+ implant. The P+ implant is for punchthrough stop. Submicron N+ regions can easily be punched through by applied voltage, so the P+ implant is added to the channel to prevent this punch through shorting. In prior art LDD devices, the N- concentration is degraded by the P+ pocket implant. In the present process, the edge thick gate silicon oxide will block and reduce the N- degradation. These improvements result in a device with improved device operation speed, channel resistance, and saturation current.

The T-gate LDD pocket device integrated circuit of the present invention illustrated in FIG. 8 comprises a gate silicon oxide layer 14 on the surface of a semiconductor substrate 10. A field oxide tip 12 is on either end of the gate silicon oxide layer wherein each field oxide tip has a concave shape with respect to the gate silicon oxide layer. A polysilicon gate 16 overlies the gate silicon oxide layer and the field oxide tips wherein the edges of the gate overlying the field oxide tips are upturned. Silicon oxide spacers 26 are formed on the sidewalls of the gate and the field oxide tips. Lightly doped regions 20 of a first conductivity type lie within the semiconductor substrate underlying the field oxide tips 12. The dopant concentration of the lightly doped regions is between about 1 E 13 to 1 E 14 atoms/cm.sup.3 for N- regions and between about 1 E 13 to 1 E 14 atoms/cm.sup.3 for P- regions. Heavily doped regions 22 of the first conductivity type lie within the semiconductor substrate on either side of the region underlying the polysilicon gate. The dopant concentration of the heavily doped regions is between about 1 E 15 to 1 E 16 atoms/cm.sup.3 for N+ regions and between about 1 E 15 to 1 E 16 atoms/cm.sup.3 for P+ regions. Pocket regions 24 of a second conductivity type underlie the heavily doped regions 22 wherein the second conductivity type is opposite to the first conductivity type. The dopant concentration of the pocket regions is between about 2 E 13 to 4 E 13 atoms/cm.sup.3 for P+ regions and between about 1 E 13 to 1 E 14 atoms/cm.sup.3 for N+ regions.

While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.