Method and Apparatus for Determining an Instantaneous Phase Difference Between Two Signals

This invention relates in general to phase detection, and more specifically to a method and apparatus for determining an instantaneous phase difference between two signals.

Classical frequency synthesizers, which can be programmed to two or more frequencies, inherently have slow warm-up times during the reprogramming process. The same is true during initial power-up of the frequency synthesizer. The warm-up time for a programmable frequency synthesizer is considered the time taken by the frequency synthesizer to switch from one operating frequency to a second operating frequency within a desired frequency lock range (e.g., .+-.10 Hz from the desired second operating frequency), or the time period needed to achieve a desired power-up frequency within a desired frequency lock range. The slow warm-up time arises from the use of phase detectors which do not measure instantaneous phase such as, for example, the source-sink-float (SSF) phase detector. To compensate for the phase detector delay, other circuit parameters in the frequency synthesizer are adjusted in ways which complicate design as well as increase cost. In addition, phase detector delay affects the phase margin and gain bandwidth of the phase-locked loop in such a way as to extend the warm-up period.

Thus, what is needed is a method and apparatus for determining an instantaneous phase difference between two signals. Preferably, the method and apparatus must measure instantaneous phase while maintaining low power consumption.

An aspect of the present invention is a method of determining an instantaneous phase difference between a reference signal operating at a desired reference frequency and a controlled signal operating asynchronously at a controlled frequency. The method comprises the steps of deriving the reference signal by frequency dividing a first signal operating at a first frequency by a counter comprising an output having K sequential states, wherein K is an integer value equal to the first frequency divided by the desired reference frequency, and wherein the output changes by no more than one bit between any adjacent states of the K sequential states, recording the output of the counter at a time concurrent with a first predetermined event occurring in the controlled signal, thereby generating a recorded count value corresponding to a current state of the counter when the counter is not executing a change from the current state to a next sequential state at said time, and generating the recorded count value selected from (a) the recorded count value corresponding to the current state and (b) the recorded count value corresponding to the next sequential state, when the counter is executing a change from the current state to the next sequential state at said time, decoding the recorded count value to produce a sequential state number S.sub.E corresponding to the first predetermined event, and determining the instantaneous phase difference (in degrees) to be equal to ##EQU1## wherein S.sub.P is a predetermined sequential state number corresponding to a second predetermined event occurring in the reference signal.

Another aspect of the present invention is a communication device, comprising a receiver for receiving a signal including information, a processing system coupled to the receiver for control thereof and for processing the information, an information interface coupled to the processing system for conveying the information to a user, user controls coupled to the processing system for providing control of the communication device by the user, an oscillator for providing a first signal operating at a first frequency, a voltage controlled oscillator (VCO) coupled to the processing system for generating a controlled signal operating asynchronously at a controlled frequency, and an apparatus coupled to the VCO for determining an instantaneous phase difference between a reference signal operating at a desired reference frequency, and the controlled signal. The apparatus comprises a counter coupled to the oscillator for deriving the reference signal by frequency dividing the first signal, the counter comprising an output having K sequential states, wherein K is an integer value equal to the first frequency divided by the desired reference frequency, and wherein the output changes by no more than one bit between any adjacent states of the K sequential states. The apparatus further comprises a register coupled to the counter for recording the output of the counter at a time concurrent with a first predetermined event occurring in the controlled signal, thereby generating a recorded count value corresponding to a current state of the counter when the counter is not executing a change from the current state to a next sequential state at said time, and generating the recorded count value selected from (a) the recorded count value corresponding to the current state and (b) the recorded count value corresponding to the next sequential state, when the counter is executing a change from the current state to the next sequential state at said time. The apparatus also comprises a decoder coupled to the register for decoding the recorded count value to produce a sequential state number S.sub.E corresponding to the first predetermined event, wherein the processing system is coupled to the decoder for determining the instantaneous phase difference (in degrees) to be equal to ##EQU2## wherein S.sub.P is a predetermined sequential state number corresponding to a second predetermined event occurring in the reference signal.

FIG. 1 is an electrical block diagram of a communication device employing a frequency synthesizer which utilizes an instantaneous phase detector in accordance with the preferred embodiment of the present invention.

FIG. 2 is a flow chart depicting operation of the frequency synthesizer of FIG. 1 in accordance with the preferred embodiment of the present invention.

FIG. 3 is a timing diagram depicting operation of the instantaneous phase detector in accordance with the preferred embodiment of the present invention.

FIG. 1 is an electrical block diagram of the communication device 100 in accordance with the preferred embodiment of the present invention. The communication device 100 includes a receiver antenna 122 for intercepting radio frequency (RF) signals comprising messages from a transmitting station (not shown). The receiver antenna 122 is coupled to a receiver 124 applying conventional demodulation techniques for receiving the RF signals. Once the RF signals have been demodulated, the receiver 124 generates demodulated message information which is presented to a processing system 126 for processing.

A conventional power switch 128, coupled to the processing system 126, is used to control the supply of power to the receiver 124, thereby providing a battery saving function.

To perform the necessary functions of the communication device 100, the processing system 126 includes, a microprocessor 136, a random access memory (RAM) 140, a read-only memory (ROM) 142, and an electrically erasable programmable read-only memory (EEPROM) 138.

Preferably, the microprocessor 136 is similar to the M68HC08 micro-controller manufactured by Motorola, Inc. It will be appreciated that other similar processors can be utilized for the microprocessor 136, and that additional processors of the same or alternative type can be added as required to handle the processing requirements of the processing system 126. It will also be appreciated that other types of memory, e.g., EEPROM or FLASH, can be utilized for the ROM 142, as well as the RAM 140. It will be further appreciated that the RAM 140 and the ROM 142, singly or in combination, can be integrated as an integral portion of the processing system 126.

The processing system 126 is programmed by way of the ROM 142 to process incoming messages transmitted by the transmitting station. During message processing, the processing system 126 decodes in a conventional manner an address in the demodulated message information, compares the decoded address with one or more addresses stored in the EEPROM 138, and when a match is detected, the processing system 126 proceeds to process the remaining portion of the message.

Once the processing system 126 has processed the message, it stores the message in the RAM 140, and a call alerting signal is generated to alert a user that a message has been received. The call alerting signal is directed to a conventional audible or tactile alerting device 132 for generating an audible or tactile call alerting signal.

The message can be accessed by the user through user controls 130, which provide functions such as lock, unlock, delete, read, etc. More specifically, by the use of appropriate functions provided by the user controls 130, the message is recovered from the RAM 140, and then conveyed to the user by way of an information interface comprising a display 134 for displaying the message, e.g., a conventional liquid crystal display (LCD).

The processing system 126 is also coupled to a frequency synthesizer providing the function of a phase-locked loop (PLL) utilized for clock generation to the microprocessor 136 core circuitry.

The frequency synthesizer comprises a voltage-controlled oscillator (VCO) 114, a divide by N frequency counter 118 (herein described as the N counter 118), an oscillator 102, a decoder 112, and an instantaneous phase detector 104, comprising a divide by K frequency counter 106 (herein described as the K counter 106) and a register 108. It will be appreciated that the frequency synthesizer, not including the oscillator 102 and the VCO 114, can be integrated as an integral portion of the processing system 126.

The oscillator 102 is a conventional reference oscillator used for supplying a first signal 103 operating at a first frequency coupled to the instantaneous phase detector 104. The instantaneous phase detector 104 divides the first signal by K to produce a reference signal operating at a desired reference frequency. The instantaneous phase detector 104 then measures the instantaneous phase between the reference signal and a controlled signal (supplied by the VCO 114 and the N counter 118, as will be described below) operating asynchronously at a controlled frequency.

The VCO 114 is a conventional VCO controlled by the processing o system 126 preferably with a digital-to-analog converter (not shown). The N counter 118 is a conventional counter with N sequential states. The N counter 118 is utilized by the frequency synthesizer for generating at the output of the VCO 1.14 a desired signal 116 operating at N/K times the frequency of the first signal 103. In performing this function, the N counter 118 generates a strobe signal 120, coupled to the instantaneous phase detector 104, providing a marker that defines the controlled signal operating at the controlled frequency and asynchronous to the first signal 103. The strobe signal 120 triggers the instantaneous phase detector 104 to measure instantaneous phase.

The strobe signal 120 is also coupled to the processing system 126 serving as an interrupt trigger to the microprocessor 136. The interrupt informs the processing system 126 that a new instantaneous phase measurement is available for processing.

The instantaneous phase detector 104 comprises a divide by K frequency counter 106 (herein described as the K counter 106), and a register 108. The K counter 106 preferably is a conventional Gray Code counter. As is well known by one of ordinary skill in the art, the Gray Code counter provides state transitions with a single bit change between adjacent states. This feature requires minimal power consumption for instantaneous phase detection. It will be appreciated that, alternatively, the K counter 106 can utilize a Johnson counter which also provides single bit changes during state transitions.

The output of the K counter 106 is coupled to a register 108 with ##EQU3## (rounded upward to the next integer value) bits of information.

The register 108 is also coupled to the strobe signal 120 provided by the N counter 118. When the edge of the strobe signal 120 is active (e.g., rising edge), the sequential state of the K counter 106 is recorded by the register 108. The recording of the output of the K counter 106 may occur in one of two ways, and corresponds to a first predetermined event, e.g., a low-to-high transition, occurring in the controlled signal. First, the sampling of the K counter 108 may occur when the K counter 108 is not sequentially switching states. In this case, the sampling of the K counter value encounters no metastability. In a second scenario, the sampling of the K counter 106 occurs when the K counter is sequentially switching states. In this second case, the K counter value sampled is subject to metastability conditions.

Since the K counter employs a Gray Code sequential state assignment, the value sampled by the register 108 can only be in error by a single sequential state. That is, the value lies somewhere between the previous state of the counter and the present state of the counter after the transition. Therefore, the instantaneous phase detector 104 is subject to a maximum of a single bit error during phase sampling. It is important to note that the higher the resolution of the K counter 106 (i.e., higher K) the lower the inaccuracy in the measured phase sampled by the instantaneous phase detector 104.

The recorded digitized phase error logged by the register 108 is provided to the processing system 126 by way of the decoder 112. The decoder 112 decodes the recorded count value to produce a sequential state number S.sub.E corresponding to the first predetermined event.

It will be appreciated that both the reference signal and the controlled signal can be output by the K counter 106 and the N counter 118, respectively, as usable output signals. In the preferred embodiment, however, the reference signal and the controlled signal are internal signals only, and are not usable, generated output signals. It will be further appreciated that, in an alternative embodiment, the phase detection roles of the K counter 106 and the N counter 118 can be swapped. That is, the K counter can generate a strobe signal upon the occurrence of an event (e.g., rising edge) occurring in the reference signal for registering the count of the N counter at the time of the event. The registered count of the N counter relative the same event occurring in the controlled signal (e.g., full count of N) can then be used to determine the phase error.

FIG. 2 is a flow chart 200 depicting operation of the frequency synthesizer of FIG. 1 in accordance with the preferred embodiment of the present invention. The flow chart 200 begins with step 202 where the oscillator 102 provides the first signal reference 103 to the instantaneous phase detector 104. In step 204, the instantaneous phase detector 104 divides the first signal reference by K to generate a desired reference frequency. In step 206, the output of the K counter 106 is recorded by the register 108 at a time concurrent with the strobe signal 120 generated by the N counter 118. Subsequently, in step 207 the processing system 126 is prompted to perform phase error processing. In step 208, the processing system 126 invokes the decoder 112 to decode the register value to produce a sequential state number S.sub.E corresponding to the first predetermined event. In step 210, the processing system 126 determines the instantaneous phase difference using ##EQU4## where S.sub.P is a predetermined sequential state number corresponding to a second predetermined event occurring in the reference signal. In step 214 the processing system 126 adjusts the VCO 114 frequency accordingly. The adjustment is proportional to the phase error calculated above. The processing system 126 then continues to step 206 for further phase error processing.

FIG. 3 is a timing diagram depicting operation of the instantaneous phase detector 104 in accordance with the preferred embodiment of the present invention. FIG. 3 shows the first signal 103 of the oscillator 102, the first signal 103 divided by K (i.e., the reference signal), the VCO 114 divided by N (i.e., the controlled signal), the strobe signal 120, and the VCO 114 desired output signal 116. In this example the OSC.div.K and the VCO.div.N signals happen to be 180.degree. out of phase. Starting at time boundary 302 (the rising edge of the controlled signal) the strobe signal 120 is activated. At this point in time the register 108 stores the current state of the K counter 106. This count translates to S.sub.E by the decoder 112, as described above. Assuming for instance that K=100, then for this example S.sub.E= 50 (i.e., 180.degree. phase difference). At the arrival of boundary 304 (i.e., the next rising edge of OSC.div.K signal) S.sub.P= 100, i.e., the full count of the K counter 106, or equivalently the next clock cycle of OSC+K signal. Inserting these numbers into the above equation results in a calculated phase error of ##EQU5## which corresponds to the phase error shown in the FIG. 3 example. Note the numbers used for S.sub.E and S.sub.P correspond to modulo K numbers incremented by one (i.e., 0 corresponds to 1, 1 corresponds 2, etc.). In addition, the reference signal and controlled signals can be internal or conceptual signals shown by way of illustration, they do not have to be actually generated and output.

Thus, it should be apparent by now that the present invention provides a method and apparatus for determining an instantaneous phase difference between two signals. In particular, the invention advantageously provides a novel method and apparatus utilizing a Gray Code counter (or the like) which provides minimal power consumption, and instantaneous phase determination with a maximum of a single bit of indeterministic error. This error can be minimized by increasing the resolution of the K counter 106, as described above. Furthermore, in providing an instantaneous phase measurement, the present invention advantageously provides an improved warm-up time during power-up, or frequency switching which prior art systems (such as sink-source-float phase detectors) have not been able to achieve.