Adaptive Duty-Cycle Limiting for Overload Protection of Integrated Circuits

The invention relates generally to integrated circuits and more particularly to protection circuits for integrated circuits.

Integrated circuits often incorporate power devices designed to drive external loads. External loads may exhibit fault conditions, such as internal short circuits or open circuits, or impedance changes due to aging or component failure. Certain fault conditions may place electrical overstresses upon the integrated circuit which is driving the faulty load. For example, suppose an integrated circuit IC.sub.1 of FIG. 1 contains a series-pass element M.sub.1 which is connected between a low-impedance voltage source V.sub.in and a resistive load R.sub.L. Under normal operating conditions, the series-pass element M.sub.1 is either on or off, and in neither case does the integrated circuit dissipate large amounts of power. If M.sub.1 is on, there will be little voltage across it, and if it is off, then little current will flow through it. Consequently, thermal dissipation within the integrated circuit is limited to a value which is nondestructive. However, if the load should fail, and consequently exhibit a low resistance to the flow of current, a potentially destructive condition occurs within the series-pass element M.sub.1. Because the resistance of this element is now large when compared to that of the faulty load, the majority of the voltage drop is across M.sub.1, and large amounts of current flow. The junction temperature of the integrated circuit will rapidly rise, and unless the fault is quickly removed, the integrated circuit will be destroyed.

Prior-art implementations of integrated circuit power drivers were typically protected by means of current limiting. A typical current limiting technique involves the placement of a current sense element in series with the series pass element, thereby allowing the integrated circuit to sense the flow of current through this device. If an excessive current flow is detected, the series pass device is disabled, protecting the circuit. This technique has the disadvantage of requiring an external reset, since with the series-pass element disabled, the integrated circuit cannot tell if the fault has cleared. Since many loads may exhibit momentary short-circuiting, this technique is not widely applicable. Techniques have been developed which monitor the load and restore normal operation when the fault is cleared. Some of these techniques rely upon linear regulation of the series-pass element, while others rely upon digital switching of the pass element.

An typical prior-art linear current limit circuit is shown in FIG. 2. A NMOS power device M.sub.1 is driven by a CMOS inverter IV.sub.1 through a limiting resistor R.sub.1. The current flowing through the power device is sensed by R.sub.2. When the voltage across R.sub.2 is sufficient to turn NPN transistor Q.sub.1 on, this transistor will pull down upon the gate of M.sub.1. Because of the presence of resistor R.sub.1, the voltage at the gate of M.sub.1 will drop, causing the voltage V.sub.out to also drop. Because the load now has a lower voltage across it, the current drawn by the load will decrease. At some point, the negative feedback around Q.sub.1 will bring the circuit into equilibrium, with a constant current flowing through the load. The constant current limit is set by adjusting the value of resistor R.sub.2.

Linear current limit circuits are often supplemented by overtemperature sensors integrated onto the integrated circuit. Due to the relatively long thermal time constants of the silicon chip, a thermal sensor cannot be relied upon as a sole means of protection. By the time the thermal sensor has detected a fault, excess power may have resulted in localized overheating and device failure. However, a thermal sensor can be combined with a linear current limit to provide a superior protection scheme. In such a scheme, the linear current limit is deliberately set to a relatively high current value, one which would eventually lead to overheating of the integrated circuit.

Some integrated circuits have multiple output drivers, or channels. These integrated circuits often require that each channel have independent protection circuitry, so that if a load driven by one channel fails, the other channels will continue to operate normally. This has historically been implemented using independent current limits and thermal shutdown circuits for each channel; this solution requires careful layout of the thermal sense elements to minimize thermal interactions between different channels which are integrated onto a common substrate.

Unfortunately, a linear current limit circuit is often difficult to implement. The feedback loop containing Q.sub.1 is a high-gain loop, and will tend to oscillate unless it is stabilized. This circuit may also interfere with the driving capabilities of the inverter IV.sub.1, due to the resistance R.sub.1 which is incorporated as a part of the current limit circuit. In addition, independent thermal shutdown circuits become increasingly difficult as output specific on resistance, Rsp, also known as Rdson/Area becomes smaller. As die area shrinks, thermal interaction between channels increases and the integrity of independent thermal shutdown becomes questionable. For this reason, digital techniques for overcurrent protection have been developed. These digital solutions prevent an output in a fault condition from heating an adjacent output, causing an inadvertant shutdown of an output not exhibiting a fault condition. A typical digital current limiting technique uses pulse-width-modulation (PWM) to limit the power dissipation through the series-pass element.

FIG. 3 shows a typical digital current limit circuit. A current sense resistor R.sub.1 is inserted in the current path through power transistor M.sub.1. A voltage is developed across this resistor which is proportional to the current flowing through the power device. This voltage is sensed by comparator C.sub.1. When the voltage exceeds the voltage of the offset voltage source V.sub.ofs, the output of comparator C.sub.1 goes high, indicating an overcurrent condition. This sets flip-flop FF.sub.1, whose non-inverting output Q now goes high. T1 is a 2.sup.n Ripple Counter made up of n D Flip/Flops with an active low clear (CLRZ). When CLRZ is low, Qmsb of T1 is low. T1 is clocked by a constant frequency pulse train on input OSC. T2 is a 2.sup.x Ripple Counter made up of x D Flip/Flops with an active low preset (PREZ).

When PREZ is low, Qmsb of T2 is high. T2 is also clocked by the input OSC. When Q of FF1 goes high, T1 and T2 are enabled. The number of flip/flops in T2 and T1 is chosen such that x>n. When T1 counts to 2.sup.n clocks of input OSC, a monostable, MONO1 is fired, clocking the input CLK of FF2. This causes the inverting output of FF2, QZ, to go low. The gate drive G1 to M1 is disabled, causing M1 to turn off. T2 continues to count OSC cycles, and when it reaches 2.sup.x counts, Qmsb of T2 goes low, clearing FF1 and FF2. This causes Q of FF1 to go low, and QZ of FF2 to go high. T1 and T2 are cleared and preset respectively, and gate drive, G1 is once again enabled. FIG. 4 represents a timing diagram demonstrating the duty cycle control of M1. If a short circuit condition is maintained, the output M1 is essentially turned off and on with a duty cycle equal to 2.sup.n /2.sup.x. By setting this oscillator's duty cycle to a small value (perhaps 1%), the power dissipation in M1 can be limited to a safe value. When the power transistor is on with a short circuit condition, a very large current will flow, limited only by the drive capacity of transistor M.sub.1 (for a MOS transistor, this means that current flow is limited only by the rdson of the transistor). This current would very quickly overheat the power device and destroy it, but the duty cycle control will disable the power transistor before overheating reaches a critical level. The low duty cycle then allows the power transistor time to cool down before another pulse of power is delivered. If a sufficiently small duty cycle is generated, this circuit can indefinitely operate in current limit without thermal runaway.

Duty-cycle control limits are not suitable for driving certain types of loads, such as incandescent lamps, which exhibit a time-dependent response. These loads require a large initial current in order to achieve a lower, steady-state operating current level. If the initial current level (called the inrush current) exceeds the current limit trip-point of a PWM current sense scheme, the driver will go into over-current detect mode and will begin to pulse-width-modulate the load. This may limit power flow into the load to a value insufficient for the load to heat up and achieve its lower, steady-state operating current level in the required time. In this case, the duty cycle output protection circuit prevents the integrated circuit from operating normally, which is clearly an undesirable circumstance.

What is needed is a more sophisticated form of duty-cycle control.

An over current protection scheme for integrated circuits having multiple outputs employs a global thermal sense circuit and a current sense circuit which is connected to a duty cycle control logic circuit. When over current is sensed, the duty cycle control logic circuit places the output in a high duty cycle mode to provide sufficient power to the load. If the over current condition persists and the junction temperature rises to the thermal sense trip point, the duty cycle control logic circuit places the output in a lower duty cycle mode. The scheme thus can adaptively respond to the load, allowing a brief inrush current event upon startup of the load, while restricting long-term power dissipation to a lower value. Loads such as incandescent bulbs can be turned on (heated up) quickly while still protecting the integrated circuit in unison with the current sense duty cycle circuitry. Multiple outputs can drive incandescent bulbs normally and also be protected against short circuit conditions.

FIG. 1 shows a prior-art power device integrated circuit;

FIG. 2 shows a prior-art linear current limit circuit for the circuit of FIG. 1;

FIG. 3 shows a prior-art digital current limit circuit for the circuit of FIG. 1;

FIG. 4 is a timing diagram for the circuit of FIG. 3;

FIG. 5 is a current limit circuit in accordance with the invention;

FIG. 6 is a thermal sense circuit usable with the circuit of FIG. 5;

FIG. 7 is an alternative embodiment of current limit circuit in accordance with the invention; and

FIG. 8 is another embodiment of current limit circuit in accordance with the invention.

As shown in the following description, the invention provides a method for protecting power devices on an integrated circuit from destructive overloads, while providing short-duration high-current drive to satisfy the inrush requirements of time-dependent loads such as incandescent lamps. The invention can be applied to integrated circuits which contain multiple independent channels, as well as integrated circuits which incorporate only one power device. In the case where the integrated circuit implements multiple channels, each channel can be given independent protection, should this be required for the application.

The primary means of protection is pulse-width-modulated current limiting circuitry (duty-cycle control circuitry) provided on a per-channel basis. This circuitry will be supplemented by a secondary protection scheme which will limit long-term overload currents to a level which will not damage the integrated circuit.

FIG. 5 shows a conceptual block diagram of how the invention operates. The integrated circuit incorporates a series-pass element M.sub.1, here shown as an NMOS power transistor. Alternative implementations include PMOS power transistors, bipolar transistors and other power switching elements. Current flowing through the power transistor is sensed by a current sense element. In this circuit, the current sense element is a resistor R.sub.1 inserted in the source lead of the power transistor. Alternative implementations for current sense elements exist, including schemes which use the rds.sub.on of a MOS transistor as a sense resistor. The invention is equally applicable to any current sensing scheme, regardless of the exact details of the implementation.

A voltage is developed across this resistor which is proportional to the current flowing through the power device. This voltage is sensed by comparator C.sub.1. When the voltage exceeds the voltage of the offset voltage source V.sub.ofs, the output of comparator C.sub.1 goes high, indicating an overcurrent condition. This sets flip-flop FF.sub.1, whose non-inverting output Q now goes high. T1 is a 2.sup.n Ripple Counter made up of nD Flip/Flops with an active low clear (CLRZ). When CLRZ is low, Qmsb of T1 is low. T1 is clocked by a constant frequency pulse train at input OSC. T2 is a 2.sup.x Ripple Counter made up of D Flip/Flops with an active low preset (PREZ). When PREZ is low, Qmsb of T2 is high. T2 is clocked by the input OSC. When Q of FF1 goes high, T1 and T2 are enabled. The number of flip/flops in T2 and T1 is chosen such that x>n. When T1 counts to 2.sup.n clocks of input OSC, a monostable, MONO1 is fired, clocking the input CLK of FF2. This causes the inverting output of FF2, QZ, to go low, disabling the gate drive, G1 by causing it to go low. T2 continues to count OSC cycles, and when it reaches 2.sup.x counts, Qmsb of T2 goes low, clearing FF1 and FF2. This causes Q of FF1 to go low, and QZ of FF2 to go high. T1 and T2 are cleared and preset respectively, and gate drive, G1 is once again enabled. Therefore, this scheme ensures that the duty cycle of M.sub.1 will be limited to the duty cycle of signal X when the part experiences a fault condition.

The duty cycle control signal, X, is generated by timing intervals in ripple counter T1 and T2. The pulse width, t.sub.pw, is determined by T1 and the period, .tau., is determined by T2. The duty cycle of signal X is given by:

The time-average current delivered to the load, I.sub.avg, is proportional to the duty cycle, d, and the peak instantaneous current delivered to the load, I.sub.pk :

Therefore, by adjusting the pulse width of T1, the average current delivered to the load can be controlled. By setting T1 to deliver a suitable pulse width (i.e, a higher duty cycle such as, for example, a duty-cycle in about the 8 to 12% range), the circuit can provide sufficient current to satisfy the inrush requirements of the load. However, the average current passing through the power transistor M.sub.1 will still be limited by the duty cycle imposed by T1 and T2. Thus, if the load were to become shorted, the power dissipation within the power device M.sub.1 would become: ##EQU1##

where rds.sub.on is the on-resistance of transistor M.sub.1. By adjusting the duty cycle to a suitable value for a given value of input voltage and transistor rds.sub.on, power dissipation within the integrated circuit can be limited to a value which will not be immediately destructive. However, because the resistance of the power switch is small compared to the resistance of the load, average power dissipation within the integrated circuit will still be quite large, even with duty cycle control. If this power dissipation were allowed to continue indefinitely, the temperature of the integrated circuit would rise, and it could eventually exceed the safe operating limits for the part.

Therefore, the invention includes a thermal sense circuit TS.sub.1 which monitors the temperature of the die. This sensor can then adjust the number of counts in T2 to further restrict power dissipation within the die to a safe level, preventing runaway thermal failure. The output of the thermal circuit can be utilized to increase the number of counts in T2, for example, by increasing the counts from 2.sup.x to 2.sup.x+1. This would cause the duty cycle of signal X to be cut in half. Additional counts can be added to sufficiently reduce the duty-cycle to protect the IC. In this case, control signal Y might be a binary signal, with a logic one indicating a narrow pulse width (yielding, for example, a 1% duty cycle) and a logic zero might indicate a wider pulse width (yielding, for example, an 8% duty cycle). A thermal sense circuit which could generate control signal Y for this scheme is shown in FIG. 6. The thermal sense element is a circuit which generates a voltage proportional to absolute temperature (VPTAT). This circuit would then generate a voltage which is linearly proportional to temperature. This voltage is then sent to a Schmitt trigger ST.sub.1. So long as the voltage is beneath an upper threshold voltage, V.sub.H, corresponding to an upper threshold temperature T.sub.H, the output would be low, allowing the longer pulse width. Once the voltage exceeds V.sub.H, the Schmitt trigger is tripped, generating a high output to reduce the pulse width generated by the one-shot. Now the voltage must drop back below a lower voltage threshold V.sub.L, corresponding to a lower temperature limit T.sub.L, before the Schmitt trigger returns the output to a low voltage. This circuit has the effect of providing thermal hysteresis (equal to T.sub.H -T.sub.L), which prevents `chattering` between the two values of duty cycle.

FIG. 7 demonstrates an alternate embodiment of the invention. In FIG. 7, the thermal sense circuit output Y feeds into ripple counter T1. The output Y can be used as a binary signal decreasing the number of counts in T1 from 2.sup.n to 2.sup.n-1 or less. By decreasing the number of counts in T1, the pulse width of duty cycle control signal X is decreased, for example from 8% to 1%.

FIG. 8 demonstrates another embodiment of the invention. In this scheme, the pulse width is determined by an analog delay circuit, T1. Similar to the other embodiments, a voltage is developed across resistor R which is proportional to the current flowing through the power device M1. This voltage is sensed by comparator C.sub.1. When the voltage exceeds the voltage of the offset voltage source V.sub.ofs, the output of comparator C.sub.1 goes high, indicating an overcurrent condition. This sets flip-flop FF.sub.1, whose non-inverting output Q now goes high. T2 is a 2.sup.x Ripple Counter made up of x D Flip/Flops with an active low present (PREZ). When PREZ is low, Qmsb of T2 is high. T2 is clocked by the input OSC. When Q of FF1 goes high, the delay circuit T1 and ripple counter T2 are enabled. When T1 delay circuit times out, it clocks FF2. This causes the inverting output of FF2, Qz to go low, disabling the gate drive, G1 by causing it to go low. T2 continues to count OSC cycles, and when it reaches 2.sup.x counts, Qmsb of T2 goes low, clearing FF1 and FF2. This causes Q of FF1 to go low, and QZ of FF2 to go high. Therefore, this scheme also ensures that the duty cycle of M.sub.1 will be limited to the duty cycle of signal X when the part experiences a fault condition.

By use of an analog delay circuit, the thermal sense input can be used as an analog voltage input to the delay circuit. The thermal sense circuit provides a voltage linearly proportional to temperature, which forms control signal Y1. The delay circuit T.sub.1 is then constructed so as to produce a delay time inversely proportional to temperature. A VPTAT circuit could be used as the thermal sensor, and a charge-discharge oscillator can be set so as to produce a pulse width inversely proportional to temperature, thus serving as analog delay circuit T1. This arrangement can be used to form a negative-feedback control loop, for as the temperature of the die increases, the thermal sensor output voltage will rise, forcing the delay circuit to produce a narrower pulse, which in turn restricts the average current flowing through power device M.sub.1, reducing the device temperature. Schemes of this sort will normally exhibit a time lag due to thermal inertia of the die, which can be seen as introducing a phase lag in the control loop. Compensation may be necessary if the phase lag is excessive, or otherwise oscillations may occur during current limit. Compensation can be introduced by (for example) inserting a low-pass R-C filter network into the thermal sensor, so as to produce a dominant pole in the s-domain transfer function of the loop, thus ensuring unconditional stability.

While the invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various other embodiments of the invention will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications of the embodiments as fall within the true scope and spirit of the invention. For example, the protection schemes would also apply to PMOS devices utilized as high side series switch, or power NMOS devices utilitzed in Low side drive applications. In every case, the power switch is protected from overload conditions by means of pulse-width modulating its conduction time whenever the instantaneous current exceeds a threshold value. In addition, the pulse width used to modulate the conduction time is itself a function of the die temperature, as monitored by a thermal sensor, plus possibly other inputs. The addition of a thermal sense circuit ensures that the die can be protected from thermal destruction by adjustment of the duty cycle of the power switch while allowing a larger duty cycle to be used to start up a time-dependent load such as an incandescent lamp.