Transmission Modulator for Cable Television Upstream Data Transmission

This invention relates generally to upstream data transmission in a two-way cable system and particularly to a system in which each potential user or subscriber is assigned a unique transmission time slot for upstream data transmission.

Cable television systems utilize a central provider of program information which serves a large number of end users generally referred to as subscribers. The central provider portion of the cable television system usually called the "headend" provides a plurality of program information as well as other information to the subscribers via a multiple branch distribution network which may define several tiers of distribution facilities.

In addition to actual programming information, the cable television system is required to carry additional management and operating data provided by the headend to the large number of end users or subscribers. Communication from the headend to the subscribers is generally referred to as "downstream" communication. In some cable television systems referred to as one-way, all information and data is transferred downstream. In other cable television systems referred to as two-way systems, communication is also provided from the various subscribers throughout the network to the headend in what is referred to as "upstream" communication. Examples of subscriber originated upstream information may include program purchasing requests, opinion poll responses, and subscriber terminal status information.

Because of the large number of subscribers being serviced by the headend, the capacity of the system to provide upstream communication is correspondingly limited. As a large number of subscriber terminals attempt to communicate upstream with the same headend facility, the system's capacity to simultaneously receive such communications is quickly exceeded. As a result, in all two-way cable television systems, some form of allotment or conflict resolution is applied to upstream communication. Upstream communication in cable television systems is provided using out-of-band communication. Such out-of-band communication uses a separate communication capability outside the standard television broadcast channel and thus is not limited to the vertical blanking interval or other time restraint. Instead, a separate carrier, usually between five and thirty megahertz, is modulated with upstream data at the decoder and transmitted to the headend.

In virtually all two-way cable television systems, certain types of upstream communication are extremely important if not essential and therefore cannot be unduly restricted or delayed by conflict resolution systems without degrading the effectiveness of the entire cable television system. Thus, such effective operation of cable television systems requires that a certain amount of guaranteed access for upstream communication must be provided to each subscriber terminal.

U.S. Pat. No. 4,553,161 issued to Citta sets forth an UPSTREAM DATA PACKET TIME SLOT SYNCHRONIZATION WITH DOWNSTREAM VBI FOR TWO-WAY CATV SYSTEM in which synchronization of upstream data packet time slots with the vertical blanking interval of a video signal transmitted downstream from the headend is provided in a two-way cable television system. Coded data transmitted during the designated vertical blanking interval from the headend is compared with system data stored in each subscriber terminal for generating a match signal. The match signal is used to interrupt a microcomputer which then divides the next video signal raster scan field into equal time slots during any one of which an upstream data packet may be transmitted.

While the prior art systems such as the above-described system in U.S. Pat. No. 4,553,161 have provided a form of guaranteed minimal upstream access for two-way cable television systems, there remains nonetheless a continuing need in the art for evermore improved upstream data transmission systems which provide flexibility and dynamic response capability as the operating circumstances of the cable television system change.

Accordingly, it is a general object of the present invention to provide an improved upstream data transmission system for cable television. It is a more particular object of the present invention to provide an improved upstream data transmission system for cable television which is able to respond dynamically to operating changes within the cable television system using headend controlled programmable system parameters.

The features of the present invention, which are believed to be novel, are set forth with particularity in the appended claims. The invention, together with further objects and advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings, in the several figures of which like reference numerals identify like elements and in which:

FIG. 1 sets forth a general block diagram of a cable television subscriber decoder constructed in accordance with the present invention;

FIG. 2 sets forth a block diagram of the upstream transmitter of the present invention upstream data transmission system;

FIG. 3 sets forth exemplary timing diagrams illustrating the operation of the present invention upstream data transmission system; and

FIG. 4 sets forth a block diagram of the upstream data transmitter of the present invention upstream data transmission system.

FIG. 1 sets forth a block diagram of a cable television subscriber terminal constructed in accordance with the present invention and generally referenced by numeral 10. Subscriber terminal 10 includes a tuner 12 coupled to a cable television distribution system (not shown) by a cable 11. The output of tuner 12 is coupled to an intermediate frequency filter 13 and thereafter to the input of an intermediate frequency amplifier and demodulator circuit 14. The output of demodulator 14 is coupled to an analog to digital converter 15, the output of which is coupled to the input of a digital logic circuit 16. A decryption circuit 17 receives the output of logic circuit 16 and is coupled to a transport demultiplexor circuit 18. The outputs of demultiplexor 18 are coupled to respective video and audio decompression circuits 19 and 30. Video decompression circuit 19 includes a random access memory 20 coupled thereto. The output of video decompression circuit 19 is coupled to a digital to analog converter 21 having an output 22 which is coupled to the video display of subscriber terminal 10. Correspondingly, the output of audio decompression circuit 30 is coupled to a digital to analog converter 31 having an output 32 coupled to the audio system of subscriber terminal 10 (not shown).

Subscriber terminal 10 further includes a microprocessor 40 having a channel selection output 41 coupled to tuner 12 and having a bidirectional data coupling to demodulator 14, digital logic circuit 16, decryption circuit 17 and demultiplexor 18. Subscriber terminal 10 further includes an upstream transmitter 50, the structure of which is set forth below in FIG. 2 in greater detail. Upstream transmitter 50 includes an input 51 coupled to output 43 of microprocessor 40 together with a symbol clock input 52 coupled to logic circuit 16, a frame sync signal input 53 also coupled to digital logic circuit 16, and a superframe synchronization signal input 54 coupled to demultiplexor 18.

In operation, a plurality of broadcast signals are coupled by cable 11 to the input of tuner 12 which in response to a channel selection signal supplied by microprocessor 40 couples a selected signal to intermediate frequency filter 13. Filter 13 may be constructed in accordance with conventional fabrication techniques and may, for example, include a conventional surface acoustic wave filter or its equivalent. The output of filter 13 is demodulated by intermediate frequency amplifier and demodulator circuit 14. Demodulator 14 may be constructed in accordance with conventional fabrication techniques and may, for example, include a synchronous demodulator. The essential function of demodulator 14 is to recover the baseband analog signal modulated upon the carrier selected by tuner 12. While different transmitting signal formats and methods may be utilized in communicating data through a cable television system, the example shown in FIG. 1 utilizes a digital vestigial sideband system in which N-level symbols having a symbol rate of approximately 10.76 megahertz are transmitted and received together with a data frame sync signal having a frequency of approximately 41.2 kilohertz resulting in data frames of approximately 24.3 milliseconds in duration. The demodulated baseband analog signal at the output of demodulator 14 comprises successive N-level symbols equally spaced by the period of the symbol clock signal. The analog to digital conversion performed by converter 15 is clocked at the symbol clock frequency to accurately recover the amplitudes of each symbol in the form of a multibit value. The output of converter 15 is processed by digital logic circuit 16 to recover the frame sync signal in synchronism with the received frame and to generate the symbol clock signal for operating converter 15. The output data signal of digital logic circuit 16 typically comprises compressed video and audio information and is further processed by decryption circuit 17 and thereafter demultiplexed in demultiplex circuit 18 to provide input video and audio signals to decompression circuits 19 and 30 respectively. Circuits 19 and 30 perform conventional video and audio decompression operations upon the applied video and audio data to produce decompressed video and audio signals which are converted to corresponding analog signals within digital to analog converters 21 and 31. The analog signals thus provided are applied to the video display and audio system (not shown) respectively.

The structure of upstream transmitter 50 is set forth below in FIG. 2 in greater detail. However, suffice it to note here that in accordance with the present invention, upstream transmitter 50 is coupled to cable 11 for upstream transmission and operates in response to a symbol clock input at input 52 from digital logic circuit 16 together with a frame sync signal input at input 53 also received from digital logic circuit 16. Upstream transmitter 50 further responds to a superframe sync signal at input 54 which is provided by transport and demultiplexor 18. In further accordance with the present invention, a programmable width signal is coupled from output 43 of microprocessor 40 to input 51 of upstream transmitter 50. Upstream transmitter 50 utilizes the width signal, the superframe sync signal, the symbol clock and the frame sync signal to properly time upstream communication applied to cable 11 from subscriber terminal 10 by generating a plurality of time slots each of which is uniquely assigned to a respective subscriber. In accordance with an important aspect of the present invention set forth below in greater detail, the time slot width and timing location of the uniquely assigned time slot for subscriber terminal 10 as well as all other subscriber terminals on the cable television system is programmably controllable by the headend manipulation of the width and superframe sync signals applied to the subscriber terminals. Thus, in accordance with the present invention, the subscriber terminals such as subscriber terminal 10 are guaranteed access to the headend during their respective uniquely assigned time slots. In further accordance with the present invention, the uniquely assigned time slots for each subscriber terminal are programmably controlled from the headend to accommodate dynamic changes within the cable television system.

In accordance with an important aspect of the present invention, the upstream carrier signals and time slots are synchronized with the symbol clock. This allows the use of a plurality of upstream carrier signals at different frequencies which are all locked to the symbol which make the most efficient use of the available upstream bandwidth. Thus, with each carrier signal locked to a common reference, different subscriber terminals may readily transmit at different upstream carrier frequencies.

In addition, because the symbol clock is used in creating the subscriber time slots, the proper relative timing between time slots at each subscriber terminal is assured. That is to say, all time slots are synchronized to the common reference of the symbol clock.

FIG. 2 sets forth a block diagram of upstream transmitter 50 shown in FIG. 1. Upstream transmitter 50 includes a slot width down counter 60 having a load input 61, a clock input 62, an output 63 and a preset input 64. A slot counter 65 includes a clear input 66, an input 67, a clock input 68 and an output 69. A frame counter 80 includes a clock input 81, an input 82, a clear input 83 and an output 84. A symbol clock input 52 is coupled to input 62 of counter 60, input 67 of counter 65 and input 82 of counter 80. A superframe sync input 54 is coupled to clear input 83 of counter 80. A frame sync input 53 is coupled to load input 61 of counter 60, clear input 66 of counter 65 and clock input 81 of frame counter 80. Output 63 of counter 60 is coupled to clock input 68 of slot counter 65.

Microprocessor 40 includes an output 49 coupled to preset input 64 of counter 60. Microprocessor 40 further includes a tuning voltage output 56, a Q signal output 59, a data output 57 and a status signal coupling 58. A comparator 85 includes an input 86 coupled to output 69 of counter 65, an input 87 coupled to output 84 of frame counter 80, an input 89, and an output 88. A timing and control circuit 100 includes an input 101 coupled to output 88, an output 102, and a transmission clock signal input 103. Timing and control circuit 100 further includes a data input 105 coupled to data output 57 and an input 106 coupled to status line input 58 of processor 40. Timing and control circuit 100 also includes a data output 111 and an address output 110 coupled to inputs 131 and 132 of a memory 130. Timing and control circuit 100 further includes a data output 109 and an address output 108 coupled to inputs 136 and 137 respectively of a memory 135. A multiplex circuit 140 includes an input 141 coupled to output 107 of circuit 100, inputs 142 and 143 coupled to outputs 133 and 138 of memories 130 and 135 respectively, and an output 144. A slot register 115 includes an output 116 coupled to input 89 of comparator 85, an enable input 117 coupled to output 102 of circuit 100, and an input 118 coupled to output 144 of multiplex 140. A time multiplex circuit 125 includes an input 126 and an output 127. A transmission modulator 120 includes a transmission clock output 121 coupled to input 103 of circuit 100 and a transmission enable input 122 coupled to output 104 of timing and control circuit 100. Transmission modulator 120 further includes a transmission data input 124 coupled to output 127 of multiplex circuit 125 and an output 123 coupled to cable 11 (seen in FIG. 1).

In operation, processor 40 provides a programmable slot width number to preset input 64 of down counter 60. Down counter 60 responds to the next frame sync signal applied to load input 61 to set down counter 60 to the programmable slot width number. Thereafter, down counter 60 responds to symbol clock signals at input 62 to count downwardly from the slot width number and produces an output signal at output 63 each time a zero count is obtained. Thereafter, slot width down counter 60 recycles producing a plurality of successive output signals at output 63 each of which corresponds to the time interval in which counter 60 counts downwardly from the programmable slot width number. The succession of outputs from slot width counter 60 is applied to clock input 68 of counter 65 which is cleared each time a frame sync signal is applied to clear input 66. Counter 65 responds to the applied clock signals to produce an output at output 69 which corresponds to the sequentially established time slots created by slot width counter 60. Thus, the output of slot counter 65 at output 69 provides a time slot identifying number which is applied to input 86 of comparator 85. Frame counter 80 receives frame sync signals at clock input 81 and counts the applied frame sync signals to produce an output at output terminal 84. The output number at terminal 84 indicates the number of frame sync intervals which have occurred following the most recent superframe sync signal. The output count of frame counter 80 is coupled to input 87 of comparator 85.

Thus, the output of counter 65 comprises a succession of eight-bit slot identifying numbers occurring within each data frame sync interval. Correspondingly, the output of frame counter 80 comprises an eight-bit running count identifying each successive frame which has occurred following the previous superframe sync signal. As a result, the combination of eight-bit output counts of counters 65 and 80 when combined form a 16-bit number which identifies a plurality of periodically recurring time slots coextensive with one or more data frames of the received vestigial sideband signals. Each time slot therefore is uniquely identified by the combined number formed by the outputs of counters 65 and 80 in which the output of counter 65 forms the eight least significant bits of the number while the output of counter 80 forms the eight most significant bits of the time slot identifying number. This combined number is utilized by comparator 85 to provide sequential identification of each time slot within each superframe as the vestigial sideband signal is received.

In further accordance with the present invention, each subscriber terminal within the cable television system is assigned a unique time slot for upstream data transmission. Thus, the proper operation of upstream transmitter 50 requires the proper timing of its upstream communication to the occurrence of its uniquely assigned time slot.

Accordingly, upstream transmitter 50 initiates upstream data transmission by initially storing the sixteen-bit time slot identifying number which is uniquely assigned to transmitter 50 within memory 130 using timing and control circuit 100. In transferring the sixteen-bit time slot identifying number to memory 130, the eight least significant bits and eight most significant bits are loaded into different memory locations to be accessed separately. The remaining memory locations within memory 130 are filled with the data to be transmitted upstream. Thereafter, the eight most significant bits which correspond to the frame identifying portion of the time slot identifying number are coupled by multiplexor 140 to register 115. Comparator 85 generates an internal match signal when the eight most significant bits of the time slot identifying number at input 89 match the eight most significant bits from counter 80. In response thereto, the eight least significant bits comprising the time slot identifying number from memory 130 are coupled through multiplexor 140 to slot register 115. Thereafter, slot register 115 applies the eight least significant bits to input 89 of comparator 85. Comparator 85 performs a comparison of the eight least significant bits of the time slot identifying number at input 89 to the current eight least significant bits at input 86 and produces an output signal at output 88 when a match occurs. In response to the match signal, timing and control circuit 100 then causes the stored data within memory 130 to be outputted to multiplexor 140 and thereafter to time multiplexor 125. Multiplexor 125 converts the data to a serial data stream which is applied to modulator 120 forming the transmission data. Concurrently, timing and control circuit 100 enables transmission modulator 120 causing the serial bit stream of transmission data to be transmitted upstream upon cable 11 (seen in FIG. 1) during the time slot uniquely assigned to upstream transmitter 50.

To further enhance the effectiveness of upstream transmitter 50, a second memory 135 identical to memory 130 and coupled to data and address outputs 109 and 108 respectively is also coupled to multiplex circuit 40. The purpose of providing memory 135 is to utilize an alternating memory access for timing and control circuit 100 in which one memory may be loaded with data while the other is outputting data to transmitted upstream. This improves the effectiveness and throughput capability of the present invention system.

The operation of transmission modulator 120 is set forth below in greater detail. However, suffice it to note here that the serial data stream of transmission data is suitably modulated upon a carrier signal within the allowable range of upstream communication frequencies for processing by the cable system headend.

FIG. 3 sets forth exemplary timing diagrams illustrative of the operation of the present invention upstream data transmission system. For purposes of references, a frame sync signal 150 comprises a plurality of periodic reference sync signals such as pulses 151, 152 and 153 occurring at the beginning of each data frame. Pulses 151 through 153 correspond to recognizable symbol combinations within the transmitted data frame which are recognized as frame sync signals. Timing diagram 155 illustrates a plurality of time slots formed by slot width counter 60 and slot counter 65 utilizing a programmable slot width number which divides each frame sync interval into eight time slots. Thus, as can be seen in diagram 155, eight time slots (corresponding to the output of slot counter 65) are created within each interval between successive frame sync signals such as signals 151 through 153. A pair of alternative superframe sync signals 160 and 165 are shown for purposes of comparison and illustration. However, it will apparent to those skilled in the art that different superframe sync signals may be utilized in accordance with the present invention. For purposes of illustration, superframe sync signal 160 generally coincides with frame sync signal 150 and thus a plurality of superframe sync intervals 161, 162 and so on are formed which generally coincide with frame sync intervals. Alternatively, superframe sync signal 165 produces a superframe interval which includes two successive frame sync intervals.

As described above, each subscriber terminal within the cable system is assigned a unique time slot in the form of a sixteen-bit time slot identifying number having the eight least significant bits identifying the time slot and the eight most significant bits identifying the frame number. As is also described above, the slot width or number time slots formed within each frame sync interval as well as the number of frames within each superframe interval may be varied to provide the necessary number of uniquely assigned time slots for the subscriber terminals within the cable system. Thus, for example, in the event superframe sync signal 160 is used, a total of eight time slots are available. The number of time slots available may be increased by adjusting the programmable slot width number to cycle counter 60 (seen in FIG. 2) more quickly and thereby divide each frame sync interval into a greater number of narrower time slots. Conversely, the programmable slot width number applied to counter 60 in FIG. 2 may be increased to divide each frame sync interval into a smaller number of time slots such as illustrated in timing diagram 170 in which four time slots per frame sync interval are provided. It will be understood by those skilled in the art that while timing diagrams 155 and 170 show alternative time slots numbering eight and four respectively during each frame sync interval, for purposes of illustration, in practice a substantially greater number of time slots per frame sync interval will most likely be utilized to accommodate a large number of subscribers.

Thus, timing diagrams 155 and 170 illustrate the use of different programmable slot width numbers to provide different numbers of available time slots for assignment to each subscriber. In addition, the superframe interval may be adjusted to provide additional uniquely assignable time slots as the superframe sync interval is lengthened. For example, in the event the slot width number is used which produces timing diagram 155 having eight time slots within each frame sync interval and superframe sync signal 160 is used, a total of eight uniquely assignable time slots are provided which would of course accommodate eight subscriber terminals. If, however, superframe sync signal 165 is utilized a total of sixteen uniquely assignable time slots are provided during interval 166 of the superframe sync signal. In such case, the first eight time slots occur within the first frame of the superframe sync interval while an additional eight time slots occur during the second frame sync interval of the superframe signal. Thus, changing from superframe signal 160 to superframe signal 165 doubles the number of uniquely assignable time slots available. If, for example, shaded time slot 156 is to be identified, the sixteen-bit time slot identifying number would comprise an eight-bit frame count most significant bit number equal to decimal one and an eight-bit slot count least significant bit number equal to decimal three would uniquely identify time slot 156.

As mentioned above, an important objective of the present invention is the utilization of programmable slot width together with programmable superframe signal values to provide dynamic configuration of the present invention upstream data transmission system. Thus, in accordance with the present invention, the headend is able to provide a sufficient number of uniquely assignable time slots for each subscriber terminal as system needs change by simply changing either or both the slot width or superframe signal values. As a result, the system is completely flexible and able to accommodate changes in system needs such as an increased number of subscriber terminals each requiring a unique assigned time slot for upstream data transmission.

FIG. 4 sets forth a block diagram of transmission modulator 120 in greater detail. As is seen in FIG. 2, transition modulator 120 operates in response to a serial bitstream of data during the uniquely assigned time slot for the subscriber terminal to modulate a selected carrier with the upstream data for transmission to the cable system headend via the system network. The timing of upstream data transmission is controlled by the upstream transmitter shown in FIG. 2 in accordance with the above-described time slot allotment leaving the function of transmission carrier modulation to transmission modulator 120. Thus, transmission modulator 120 utilizes a discrete time oscillator 230 together with a phase lock loop 240 to provide a carrier signal at a selected frequency which is locked to a network reference such as the network symbol clock signal. Modulator 265 receives the generated carrier signal together with the to-be-transmitted data and produces the modulated carrier used for upstream communication.

More specifically, transmission modulator 120 includes a discrete time oscillator 230 having a voltage controlled oscillator 200 having a tuning voltage input 201 coupled to output 56 of microprocessor 40 (seen in FIG. 2). Discrete time oscillator 230 further includes a latch circuit 210 having a clock input 211 coupled to output 202 of oscillator 200, a Q output 213 and a D input 212. A summer 205 includes an input 206, an input 207 coupled to output 59 of microprocessor 40, seen in FIG. 2, an input 208 coupled to cue output 213 of latch 210, and an output 209. Output 209 of summer 205 is coupled to an input 216 of a sine wave lookup table 215. In addition, output 209 is further coupled to the D input 212 of latch 210. Sine lookup table 215 includes an output 217 coupled to an input 219 of a comparator type slicing circuit 218.

Transmission modulator 120 further includes a phase lock loop 240 having a phase detector 242 having inputs 243 and 244 and an output 245. A frequency dividing circuit 241 is coupled between output 220 of slicer 218 and input 243 of phase detector 242. A second frequency dividing network 251 is coupled to input 244 of phase detector 242. Output 245 of phase detector 242 is coupled to an input 248 of a latch circuit 247 via a low pass filter 246. Latch 247 includes a clock input 249 coupled to the input of frequency dividing network 251 and an output 250 coupled to input 206 of summer 205. Transmission modulator 120 includes a clock signal input 121 coupled to the input of frequency divider network 251 and which comprises the symbol clock from input 52 seen in FIG. 2.

As is mentioned above, transmission modulator 120 includes an input 124 which receives the serial bit stream of data for upstream transmission. Transmission modulator 120 further includes a signal constellation coding circuit 260 which may for example comprise a conventional byphase shift key coding circuit which appropriately codes the serial bit data stream of upstream transmission data and applies it to an input 257 of a low pass filter 255. Filter 255 includes a clock signal input 256 coupled to symbol clock input 121. Output 258 of low pass filter 255 is coupled to input 262 of a modulator 265. Modulator 265 includes an input 261 coupled to output 217 of sine wave lookup table 215 and an output 263. A channel filter 264 couples output 263 to an input 267 of a variable attenuator 266. Attenuator 266 includes an output 268 coupled to cable 11 (seen in FIG. 1).

In operation, microprocessor 40 (seen in FIG. 2) produces initial values of the tuning voltage and value "q" for application to input 201 of oscillator 200 and to input 207 of summing network 205. These initial values of tuning voltage and input signal "q" to summing network 205 are programmable values selected to generate an output carrier having one of a plurality of frequencies within the upstream communication bandwidth of the system. Typically, such upstream communications are modulated upon carriers having frequencies within a range of 5-30 Megahertz. Oscillator 200 is a voltage controlled oscillator producing an output signal having a frequency determined by the tuning voltage input. Thus, the output signal of oscillator 200 is applied to the clock input of latch 210 having a Q output applied to one input of summing network 205. With the value q input to summing network 205 established by microprocessor 40 (seen in FIG. 2), an output combined signal is applied to sine wave lookup table 215. For purposes of speed and efficiency, only a predetermined number of the most significant bits within the output data of summer 205 are required for input to sine wave lookup table 215. Sine wave lookup table 215 responds to the input data at input 216 to produce a stream of digital values which are converted by slicer 218 to an output square wave or clock signal at the frequency of the sine wave produced by the values of lookup table 215. The output square wave signal from slicer 218 is applied to a divide by M frequency divider 241 which forms one input to phase detector 242.

Concurrently, the input symbol clock signal received at input 121 is frequency divided within divider 251 using a divide by N frequency division and applied to the remaining input of phase detector 242. The combination of frequency dividers 241 and 251 together with phase detector 242 is used to provide a carrier frequency for upstream communication which is locked to a network reference signal which is common to all subscriber terminals. Thus, as each transmission modulator within the cable television system uses carrier frequencies for upstream data communication which are all locked to a common network reference, the available bandwidth of upstream frequencies will be used with maximum efficiency. In the example shown in FIG. 4, the common network reference selected is that of the symbol clock signal. Thus, it is anticipated that other transmission modulators similar to transmission modulator 120 within the host cable television system will utilize different upstream carrier frequencies each locked to the common network reference provided by the symbol clock signal.

Accordingly, the values of M and N selected for frequency dividers 241 and 251 are selected to satisfy the expression fc=fs2.sup.M /2.sup.N in which fc is the frequency of the upstream transmission carrier and fs is the frequency of the symbol clock reference signal. Phase detector 242 provides a frequency and phase comparison of the frequency divided input signals at inputs 243 and 244 and produces an output error signal representing the phase and frequency difference between the divided carrier signal and the divided symbol clock signal. This error signal is filtered by low pass filter 246 and applied to data input 248 of latch 247. Latch 247 is clocked by the symbol clock signal. The output signal of latch 247 representing the phase and frequency error signal is applied to input 206 of summing network 205. The application of the output error signal of latch 247 to input 206 of summing network 205 closes the control loop for discrete time oscillator 230 and phase lock loop 240 which operates to frequency and phase lock the carrier signal produced by discrete time oscillator 230 to the symbol clock signal.

Thus, in the event the frequency of carrier signal is less than its desired value, a positive error signal will be developed at the output of latch 247. In response, the output of summer 205 will increase at a more rapid rate thereby increasing the carrier frequency output signal of lookup table 215. Conversely, in the event the frequency of the carrier signal produced by discrete time oscillator 230 is greater than its desired value, a negative error signal will be produced at the output of latch 250 which in turn will decrease the rate of signal increase at the output of summer 205 thereby decreasing the frequency of carrier signal at the output of lookup table 215. When the carrier signal and symbol clock signal are properly phase and frequency locked, the value of error signal at the output of latch 250 will be zero.

The carrier frequency signal produced by discrete time oscillator 230 is applied to one input of modulator 265. The transmission data is properly coded by coding circuit 260 and filtered by filter 255 for application to the remaining input of modulator 265. The output of modulator 265 comprises a carrier having the carrier frequency produced by discrete time oscillator 230 modulated with the properly coded transmission data. Channel filter 264 filters the undesired modulation components from the modulated carrier signal and applies the desired modulated carrier to cable 11 (seen in FIG. 1) through a programmable attenuator 266 for upstream communication.

It should be noted that the frequency of the carrier signal is controlled by programmable values of tuning voltage as well as frequency divider values M and N. Thus, the carrier frequency of transmission modulator 120 is readily established or changed using the programmable values providing substantial flexibility for the present invention upstream data transmission system.

What has been shown is an upstream data transmission system for cable television in which a plurality of uniquely assignable time slots are provided for use by each subscriber terminal in a guaranteed access upstream data transmission. The number and width of the time slots is programmable by the system headend and is readily changed by downloading of a pair of program values. The system further utilizes an upstream transmission modulator having a carrier signal which is phase and frequency locked to a common network reference signal to provide maximum efficiency of upstream transmission bandwidth use. The frequency of carrier for each transmission modulator is programmable and may be controlled by a downloaded programmable value set.

While particular embodiments of the invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from the invention in its broader aspects. Therefore, the aim in the appended claims is to cover all such changes and modifications as fall within the true spirit and scope of the invention.