US 5,545,955 AGrant
MOS Gate Driver for Ballast Circuits
Issue Date:1996-08-13
•22 Claims
•4 Drawing Sheets
Abstract
A monolithic MOS gate driver chip is described for driving high side and low side power MOSFETs in a gas discharge lamp ballast circuit. The chip includes a timer circuit for generating a square output at the natural frequency of resonance of the lamp ballast. Dead time circuits are provided in the chip to prevent the simultaneous conduction of both high side and low side MOSFETs. The chip may be housed in a right pin DIP package.
Metadata
Assignee
- International Rectifier Corporation
Inventor
- Peter N. Wood
Application Information
Application Number:US 2061236
Filing Date:1994-03-04
Priority Date:1994-03-04
Art Unit:252
Classifications
IPC:
H05B 3702
Field of Search:
315224;244;DIG. 4;DIG. 5;DIG. 7;243;219;209 R;291;307;308;294;260;250
Patent Drawings (4 sheets)
Description
Background of the Invention
This invention relates to a gate driver circuit for MOS gated devices, and more specifically relates to a monolithic gate driver circuit for MOS gated circuit devices, particularly those used in lamp ballast circuits.
Electronic ballasts for gas discharge circuits are coming into widespread use because of the availability of power MOSFET switching devices to replace previously used power bipolar transistor devices. Most electronic ballasts use two power MOSFET switches in a totem pole (half bridge) topology, with the gas discharge tube circuits consisting of L-C series resonant circuits in which the lamp or lamps are connected across one of the reactances of the L-C circuit. The power MOSFET switches are then driven to conduct alternately by inputs from secondary windings on a current transformer, the primary winding of which conducts the current of the lamp circuits. The primary winding current alternates at the resonant frequency of the resonant circuit.
Such prior art circuits have numerous drawbacks. For example, such circuits:
1. Are not self-starting and require a DIAC type device to initially pulse the circuit into operation.
2. They have poor switch times.
3. They are labor intensive due particularly to the need for a toroidal current transformer.
4. The circuits are not amenable to dimming.
5. The circuits are not amenable to mass production manufacture.
Brief Summary of the Invention
The present invention provides a novel monolithic MOS gate driver which permits the driving of low side and high side power MOSFETS or IGBTs (or any other MOS gated type device) from logic level, ground referenced inputs. Such circuits are particularly well adapted for the driving of gas discharge lamp ballast circuits.
More specifically, the MOS gate driver of the invention can be used for the drive of lamp ballast circuits or, more generally, any desired MOS gated circuit, and provides the following features:
1. It provides gate drive voltage signals for two MOS gated power semiconductors such as power MOSFETs or IGBTs, one designated as a "Low-side switch" and the other as a "High-side switch". The two power switches are commonly connected in a totem pole or half-bridge circuit.
2. It provides level shifting circuits with a voltage offset capability up to about 600 volts to translate ground (substrate) referenced signals via an isolated portion of the silicon die to facilitate the drive function of the high side switch.
3. A logic circuit referenced to ground (substrate) that consists of comparators, a voltage regulator to control the magnitude of the output signals when the driver is supplied from non-regulated d-c supplies, undervoltage lockout circuits to prevent marginal operation of the MOS power switches, both low side and high side, a dead band delay circuit that prevents "shoot through" currents from flowing in the MOS power switches, and a logic function that allows the high side and low side drive outputs to alternate on a 50% time basis.
4. An additional logic output is provided so that the driver can self-oscillate at a frequency determined by external resistors and capacitors R.sub.T and C.sub.T, respectively, where the frequency of oscillation f.sub.o is set by the relationship: ##EQU1##
5. The monolithic die can be packaged in a conventional 8-pin DIP or SMD package.
Detailed Description of the Drawings
FIG. 1 shows a prior art electronic ballast using a current transformer drive.
FIG. 2 shows a generalized electronic ballast for gas discharge lamps, which uses the monolithic circuit of the present invention.
FIG. 3 shows a circuit diagram of a "double 40" fluorescent ballast, which uses the monolithic MOS gate driver of the invention.
FIG. 4 shows a circuit diagram of a high pressure sodium ballast, using the novel MOS gate driver of the present invention.
FIG. 5 is a block diagram of the novel monolithic gate driver shown in FIGS. 2, 3 and 4.
Detailed Description of the Drawings
Referring first to FIG. 1, there is shown a prior art ballast using a current transformer drive. The circuit employs power MOSFETs 20 and 21 connected in a "totem pole", a half-bridge circuit, and driven from a d-c power source at terminals 22 and 23. The output circuit includes a gas discharge tube 24 of any desired type which is connected to a series L-C circuit consisting of inductor 25 and capacitors 26-27. A current transformer 28 has a primary winding 29 in series with tube 24 and secondary windings 30 and 31 connected to the gates of MOSFETs 20 and 21, respectively. A diac 32 is connected from the node between resistor 33 and capacitor 34 and the gate of MOSFET 21 to provide a starting pulse to start the circuit into oscillation. Once started, the circuit will operate at the resonant frequency of inductor 25 and capacitor 26.
More specifically, after MOSFET 21 turns on, oscillation is sustained, and a high frequency (30 to 80 kHZ) excites the L-C circuit. The sinusoidal voltage across capacitor 27 is magnified by the circuit Q at resonance, and develops a sufficient magnitude to strike the lamp 24.
The circuit of FIG. 1 is a holdover from known ballast designs using bipolar transistors and is not well suited to power MOSFETs because of poor waveforms.
The novel monolithic chip of the invention permits the drive of a ballast circuit which is self-starting, has improved switching time, is amenable to dimming, and avoids labor intensive inductor components such as the current transformer 28 of FIG. 1.
FIG. 2 shows the novel monolithic MOS gate driver 40 of the invention in the ballast circuit of a gas discharge lamp. More specifically, the circuit of FIG. 2 has a gas discharge lamp 24 associated with the series L-C circuits 25, 26, 27 as in FIG. 1. Two power MOSFETs 20 and 21 are also connected to d-c source terminals 22 and 23 as in FIG. 1. Power MOSFETs 20 and 21 may be any power device which has a MOS gate, for example, an IGBT or a MOS gated thyristor. The chip 40 of FIG. 2 provides drive signals to the MOSFETs 20 and 21 which avoids the drawbacks of the prior art circuit of FIG. 1.
More specifically, chip 40 may be housed in an 8-pin DIP or surface mount package, and has the following pinouts:
H.sub.O --an output pin to the gate of the high side MOSFET 20;
V.sub.S --a pin to the center tap of the totem-pole or half bridge connected MOSFETs 20 and 21.
L.sub.O --an output pin to the gate of the low side MOSFET 21.
G--a pin connected to the negative terminal 23 of the d-c source.
C.sub.T --a single input control pin which is connected to the node between timing capacitor C.sub.T and timing resistor R.sub.T. The other side of capacitor C.sub.T is connected to inductor 25. Control signals to single pin C.sub.T controls both outputs H.sub.O and L.sub.O.
R.sub.T --a pin which is connected to the other terminal of timing resistor R.sub.T.
V.sub.CC --a pin which receives a chip operating voltage from the node between resistor 41 and capacitor 42.
V.sub.B --a pin connected to the node of diode 43 and capacitor 44, which acts as a "bootstrap" circuit to provide power for the operation of the high side switch.
Also provided in FIG. 2 are two back-to-back diodes 50 and 51 in series with the lamp circuit. These diodes 50 and 51 form a zero-crossing detector for lamp 24.
In operation, and before tube 24 strikes, the resonant circuit consists of inductor 24 and both capacitors 26 and 27. The capacitance of capacitor 27 is lower than that of capacitor 26 so that it operates at a higher a-c voltage than that of capacitor 26. This voltage on capacitor 27 strikes the lamp 24. After lamp 24 strikes, capacitor 27 is effectively short circuited by the lamp voltage drop and the frequency of the resonant lamp circuit now depends on inductor 25 and capacitor 26.
This causes a shift to a lower resonant frequency during normal operation, synchronized by the zero crossing of the a-c current at diodes 50 and 51, and using the resultant voltage to control the oscillator within chip 40. As will be shown, the oscillation frequency of the circuit is synchronized by the addition of resistor R.sub.T and capacitor C.sub.T.
The chip 40 provides offset voltage capability up to or higher than 600 volts d-c and has a "front end" capability similar in function to that of the well known CMOS 555 timer i.c.
Chip 40 also has interior circuitry to provide a nominal 1 microsecond dead time between outputs of the alternating high side and low side outputs for driving switches 20 and 21.
As will also be later shown, the chip 40 will be supplied at terminal 22 by a rectified a-c voltage and, therefore, is designed for a minimum quiescent current, and has a 15 volt interval shunt regulator. Thus, a single one-half watt dropping resistor 41 can be used.
In addition to the quiescent current there are two other components of d-c supply current that are a function of the actual application circuit.
1) Current due to charging the input capacitance of the power switches.
2) Current due to charging and discharging the junction isolation capacitance of the gate driver chip.
Both components of current are charge related and therefore follow the rules:
It can readily be seen, therefore, that to charge and discharge the power switch input capacitances, the required charge is a product of the gate drive voltage and the actual input capacitances and the input power required is directly proportional to the product of charge and frequency and voltage squared: ##EQU2##
When designing an actual ballast circuit and because of the above relationships, the following should be observed:
1) Select the lowest operating frequency consistent with minimizing inductor size.
2) Select the smallest die size for the power switches consistent with low conduction losses. (This reduces the charge requirements.)
3) Use the lowest possible d-c voltage.
In summary, the circuit of FIG. 2, when driven by chip 40, provides a self-oscillating square wave generator with dead time control and level shifting for the MOS gated devices in the circuit. Unlike the prior art current transformer driver, the novel system provides clean "text book" waveforms to minimize switch losses. In many cases, smaller size MOSFETs can be selected or, alternatively, heat sinks may be reduced or eliminated.
FIG. 3 shows an exemplary ballast circuit which could employ the chip 40 of the FIG. 2 for a "double 40" fluorescent lamp ballast. In FIG. 3, components similar to those of FIG. 2 have the same identifying numerals. The lamp circuit in FIG. 3 employs two 40 watt fluorescent lamps 60 and 61 in a common reflector which have respective series inductors 62 and 63 and series capacitor 64. Each of tubes 60 and 61 have parallel capacitors 66 and 67, respectively, and parallel positive temperature coefficient thermistors 68 and 69, respectively. A snubber consisting of capacitor 70 and resistor 70a is connected from the node between MOSFETs 20 and 21 to the neutral line.
The input a-c circuit includes an a-c source having two a-c terminals L.sub.1 and L.sub.2 and a neutral terminal N. A conventional filter circuit including 30 microhenry inductors 71a and 71b is connected to a single phase full wave rectifier 74 having a positive output connected to resistor 41 and a negative terminal connected to capacitor 42, providing a 320 volt d-c output from a 220 volt a-c input. The input filter further includes capacitors 75, 76 and 77 as well as d-c capacitors 78 and 79.
Note that chip 40 of FIG. 3 operates directly off the d-c bus through dropping resistor 41 and oscillates at around 45 kHz in compliance with the following relationship: ##EQU3##
Power for the high side switch gate drive comes from bootstrap capacitor 44 (0.1 .mu.F) which is charged to approximately 14 volts whenever pin V.sub.S is pulled low during the low side power switch conduction. The bootstrap diode 43 (11DF4) blocks the d-c bus voltage when the high side switch conducts. Diode 43 is a fast recovery diode (<100 nSec) to ensure that the bootstrap capacitor 44 is not partially discharged as the diode 43 recovers and blocks the high voltage bus.
The high frequency output from the half bridge 20-21 is a square wave with very fast transition times (approximately 50 nSec). In order to avoid excessive radiated noise from the fast wave fronts, a 0.5 watt snubber 70-70a (10.OMEGA. and 0.001 .mu.F, respectively), is used to slow down the switch times to approximately 0.5 .mu.Sec. Note that there is a built-in dead time of 1 .mu.Sec to prevent shoot-through currents in the half bridge.
The fluorescent lamps 60 and 61 are operated in parallel, each with its own L-C resonant circuit. Any number of tube circuits can be driven from the single pair of MOSFETs 20 and 21 sized to suit the power level.
The reactance values for the lamp circuit are selected from L-C reactance tables or from the equation for series resonance: ##EQU4##
The Q of the lamp circuits is fairly low because of the need for operation from a fixed frequency which, of course, can vary because of R.sub.T and C.sub.T tolerances. Fluorescent lamps do not normally require very high striking voltages so a Q of two or three is sufficient. "Flat" Q curves tend to result from larger inductors and small capacitor ratios where: ##EQU5## and R tends to be larger as more turns are used.
Soft-starting with tube filament pre-heating is accomplished by P.T.C. thermistors 68 and 69 across each lamp. In this way the voltage across the lamp gradually increases as the P.T.C. thermistor self-heats until finally the striking voltage with hot filaments is reached and the lamp strikes.
The following table gives the values of components used for a preferred embodiment of FIG. 3:
FIG. 4 shows another embodiment of the invention for the drive of a high pressure sodium lamp ballast. The circuit of FIG. 4 has the synchronization circuit of FIG. 2 and also has an automatic shut-down circuit. In FIG. 4, components similar to those of FIGS. 2 and 3 have similar identifying numerals. In FIG. 4, the lamp is a high pressure sodium lamp 90 having a parallel capacitor 91 and an inductor 92. Inductor 92 has a tap which is part of a shut-down circuit, and includes resistor 93, diodes 94 and 95 and capacitor 96.
In FIG. 4, the synchronizing circuit consists of the zero crossing detector diodes 50 and 51 which synchronize the self-oscillation frequency to the true resonance of the LC circuit 91, 92. The Q of the series resonant circuit is made to be about 20 and provides sufficient voltage to strike lamp 90. The synchronizing capability of the chip 40 allows the series tuned circuit of FIG. 4 to resonate at high Q to provide the 3 kv starting voltage for lamp 90 without the use of a separate igniter.
In a hot restrike situation, where Q is insufficient to provide the necessary restrike voltage, the shutdown circuit including diodes 95 and 96 provides a d-c bias voltage which prevents the voltage at pin C.sub.T from reaching the 1/3 V.sub.CC valley switching point. Thus, the circuit provides "burps" of oscillation until restrike is accomplished (approximately 90 seconds) and sustained, and destructive high MOSFET currents avoided.
FIG. 5 is a block diagram of the circuit of chip 40 of the preceding FIGS. 2, 3 and 4. The eight pinouts of chip 40 are repeated in FIG. 5. All circuit blocks to be described in FIG. 5 are integrated into a common silicon chip. The first circuit block is the clamp circuit 100, consisting of a plurality of zener diodes. These are connected from pin V.sub.CC and pin V.sub.SS which is connected to the silicon substrate which acts as the chip ground. A digital supply line and analog supply line both extend from pin V.sub.CC. An analog ground line and a digital ground line are also connected to pin V.sub.SS.
The next group of circuit blocks form a timer circuit. These include divider circuit 101 connected to the analog supply line to the analog ground, N comparator 102, P comparator 103 and an RS latch 104. Two taps from divider 101 are connected to the positive inputs of comparators 102 and 103. Input pin C.sub.T is connected to the negative input of comparator 103. The output of comparators 102 and 103 are connected to the RS latch 104 as shown.
The RS latch 104 is also connected to undervoltage lock-out circuit 105 which is integrated into the chip circuit. Thus if V.sub.CC reduces too low, the RS latch 104 is locked out.
A bias circuit 106 provides bias outputs to the RS latch 104, the lockout circuit 105, and to dead time delay circuits 107 and 108 in the high side and low side circuit lines. Time delay circuits 107 and 108 provide a dead time or delay of about 1 microsecond between the turn on of the high side or low side switch after the turn off of the other. This dead time ensures that a "shoot through" circuit cannot be formed in which both power MOSFETs 20 and 21 are simultaneously on.
The output of dead time circuit 108 is applied to low side delay circuit 109 and low side driver 110 which is connected to pin L.sub.O.
The output of dead time circuit 107 is applied to level shift pulse generator 111 in the high side output line. The high side line also includes a high side bias supply circuit 112 which drives a dv/dt filter circuit 113 which filters noise from the pulse passed by circuit 113, and an under-voltage analog lockout circuit 114. The input to the high side bias circuit 112 is connected to pin V.sub.B.
The output of lockout circuit 114 and dv/dt filter 113 is applied to latch circuit 115 and its output is connected to buffer 116 which contains gain stages and drives pin H.sub.O. Note that pin V.sub.SS is connected to circuits 113, 114, 115 and 116.
Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.
Claims
Certificate of Correction present
The claims shown below may not include correction changes. Use the corrected PDF for authoritative text.
What is claimed is:
1. An integrated circuit formed in a silicon substrate for driving first and second MOS gated power devices which are connected in a half bridge circuit which has first and second d-c terminals and a common terminal at the node between said first and second MOS gated power devices; said integrated circuit including timer circuit means having an input control terminal C.sub.T which is connectable to a low logic level signal referenced to the potential of said substrate; latch circuit means coupled to said timer circuit means for controlling the frequency at which said first and second MOS devices are switched on and off and having an output which is switched in response to a predetermined signal applied to said input control terminal; a high side dead time delay circuit and a low side dead time delay circuit each coupled to said latch circuit means for delaying the transmission of a latch output signal for a predetermined time delay following the switching of the output of said latch circuit means; a high side level shifting means and a high side driver circuit means and a low side driver circuit means; said high side driver circuit means, and said low side driver means coupled to said high side dead time circuit and said low side dead time circuit respectively and having high side and low side output pins respectively which produce outputs for turning on and off said first and second MOS gated power devices in response to control signals at said input control terminal C.sub.T ; said dead time delay circuits preventing the simultaneous conduction of said first and second MOS gated power devices.
2. The integrated circuit of claim 1 wherein said MOS gated power devices are MOS devices which are selected from the group consisting of power MOSFETs, IGBTs and MOS gated thyristors.
3. The integrated circuit of claim 1 wherein said predetermined time delay is about 1 microsecond.
4. The circuit of claim 1 which further includes a source of operating voltage V.sub.CC coupled to said first and second d-c terminals for providing operating power for each of said circuit means in said integrated circuit; said integrated circuit having a V.sub.CC pin extending therefrom for connection to at least one of said first or second d-c terminals.
5. The circuit of claim 4 which further includes resistor means for coupling said V.sub.CC pin to said first d-c terminal.
6. The integrated circuit of claim 4 wherein said predetermined time delay is about 1 microsecond.
7. The integrated circuit of claim 5 wherein said predetermined time delay is about 1 microsecond.
8. The device of claim 4 which further includes undervoltage trip circuit means coupled to and monitoring the voltage at said V.sub.CC pin and having an output coupled to said latch circuit means and to said high side and low side dead time circuits for disabling said latch circuit means and delay circuits when the voltage at said V.sub.CC pin falls below a given value.
9. The integrated circuit of claim 8 wherein said predetermined time delay is about 1 microsecond.
10. The circuit of claim 9 which further includes a source of operating voltage V.sub.CC coupled to said first and second d-c terminals for providing operating power for each of said circuit means in said integrated circuit, said integrated circuit having a V.sub.CC pin extending therefrom for connection to at least one of said first or second d-c terminals.
11. The circuit of claim 7 which further includes resistor means for coupling said V.sub.CC pin to said first d-c terminal.
12. The circuit of claim 8 which further includes resistor means for coupling said V.sub.CC pin to said positive terminal.
13. The device of claim 1 wherein said timer circuit has a second input control terminal R.sub.T for controlling the frequency at which said MOS gated devices are turned on and off; said terminals C.sub.T and R.sub.T being connected to an external timing capacitor of value C.sub.T and timing resistor of value R.sub.T respectively for setting the oscillation frequency f.sub.o of said timing circuit to be: ##EQU6##
14. The integrated circuit of claim 13 wherein said predetermined time delay is about 1 microsecond.
15. The circuit of claim 13 which further includes a source of operating voltage V.sub.CC coupled to said first and second d-c terminals for providing operating power for each of said circuit means in said integrated circuit; said integrated circuit having a V.sub.CC pin extending therefrom for connection to at least one of said first or second d-c terminals.
16. The circuit of claim 13 which further includes resistor means for coupling said V.sub.CC pin to said first d-c terminal.
17. The device of claim 13 which further includes undervoltage trip circuit means coupled to and monitoring the voltage of said V.sub.CC pin and having an output coupled to said latch circuit means and to said high side and low side dead time circuits for disabling said latch circuit means and delay circuits when the voltage at said V.sub.CC pin falls below a given value.
18. An electronic ballast circuit including, in combination, at least one gas discharge lamp, at least one L-C circuit in series with said gas discharge lamp, first and second series connected MOS gate controlled power switching devices having respective gate terminals and connected in a half bridge circuit arrangement, a pair of d-c power terminals connected in series with said first and second series connected switching devices; said lamp and L-C series circuit connected across said second power switching device, and a gate drive circuit having an input terminal for receiving input logic level signals for alternately switching on and off both of said first and second MOS gated devices at a given frequency of oscillation; said gate drive circuit having output terminals H.sub.O and L.sub.O coupled to the respective gates of said discrete devices; said gate drive circuit having a terminal V.sub.CC which provides the operating power for its internal circuitry; and an external resistor for connecting said terminal V.sub.CC to one of said pair of terminals.
19. An electronic ballast circuit including, in combination, at least one gas discharge lamp, at least one L-C circuit in series with said gas discharge lamp, first and second series connected MOS gate controlled power switching devices having respective gate terminals and connected in a half bridge circuit arrangement, a pair of d-c power terminals connected in series with said first and second series connected switching devices, said lamp and L-C series circuit connected across said second power switching device, and a gate drive circuit having an input terminal for receiving input logic level signals for alternately switching on and off both of said first and second MOS gated devices at a given frequency of oscillation; said gate drive circuit having output terminals H.sub.O and L.sub.O coupled to the respective gates of said power switching devices; said gate drive circuit having an oscillation timer circuit having first and second input pins R.sub.T and C.sub.T respectively, and a discrete resistor and a discrete capacitor connected to pins R.sub.T and C.sub.T respectively to set said given frequency of oscillation at a given frequency and at the frequency of oscillation of said L-C circuit.
20. An electronic ballast circuit including, in combination, at least one gas discharge lamp, at least one L-C circuit in series with said gas discharge lamp, first and second series connected MOS gate controlled power switching devices having respective gate terminals and connected in a half bridge circuit arrangement, a pair of d-c power terminals connected in series with said first and second series connected switching devices; said lamp and L-C series circuit connected across said second power switching device, and a gate drive circuit having an input terminal for receiving input logic level signals for alternately switching on and off both of said first and second MOS gated devices at a given frequency of oscillation; said gate drive circuit having output terminals H.sub.O and L.sub.O coupled to the respective gates of said power switching devices; said gate drive circuit having a terminal V.sub.CC which provides the operating power for its internal circuitry; and an external resistor for connecting said terminal V.sub.CC to one of said pair of terminals; said gate drive circuit having an oscillation timer circuit having first and second input pins R.sub.T and C.sub.T respectively, and a discrete resistor and a discrete capacitor connected to pins R.sub.T and C.sub.T respectively to set said given frequency of oscillation at a given frequency and at the frequency of oscillation of said L-C circuit.
21. An electronic ballast circuit including, in combination, at least one gas discharge lamp, at least one L-C circuit in series with said gas discharge lamp, first and second series connected MOS gate controlled power switching devices having respective gate terminals and connected in a half bridge circuit arrangement, a pair of d-c power terminals connected in series with said first and second series connected switching devices; said lamp and L-C series circuit connected across said second power switching device, and a monolithic gate drive circuit having an input terminal for receiving input logic level signals for alternately switching on and off both of said first and second MOS gated devices at a given frequency of oscillation; said gate drive circuit having output terminals H.sub.O and L.sub.O coupled to the respective gates of said discrete devices; said gate drive circuit having a terminal V.sub.CC which provides the operating power for its internal circuitry; and an external resistor for connecting said terminal V.sub.CC to one of said pair of terminals; said integrated circuit including timer means having an input control terminal C.sub.T which is connectable to a low logic level signal referenced to the potential of said substrate; latch circuit means coupled to said timer circuit means for controlling the frequency at which said first and second power switching devices are switched on and off and having an output which is switched in response to a predetermined signal affixed to said input control terminal; a high side dead time delay circuit and a low side dead time circuit each coupled to said latch circuit means for delaying the transmission of a latch output signal for a predetermined time delay following the switching of the output of said latch circuit means; a high side level shifting means and a high side driver circuit means and a low side driver circuit means; said high side driver circuit means and said low side driver circuit means coupled to said high side dead time circuit and said low side dead time circuit means respectively and having high side and low side output pins respectively which produce outputs for turning on and off said first and second MOS gated power devices in response to control signals at said input control terminal C.sub.T ; said dead time delay circuits preventing the simultaneous conduction of said first and second MOS gated power devices.
22. An electronic ballast circuit including, in combination, at least one gas discharge lamp, at least one L-C circuit in series with said gas discharge lamp, first and second series connected MOS gate controlled power switching devices having respective gate terminals and connected in a half bridge circuit arrangement, a pair of d-c power terminals connected in series with said first and second series connected switching devices; said lamp and L-C series circuit connected across said second power switching device, and a gate drive circuit having an input terminal for receiving input logic level signals for alternately switching on and off both of said first and second MOS gated devices at a given frequency of oscillation; said gate drive circuit having output terminals H.sub.O and L.sub.O coupled to the respective gates of said MOS power switching devices; said gate drive circuit having an oscillation timer circuit having first and second input pins R.sub.T and C.sub.T, respectively, and a discrete resistor and a discrete capacitor connected to pins R.sub.T and C.sub.T, respectively, to set said frequency of oscillation at a given frequency and at the frequency of oscillation at a given frequency and at the frequency of oscillation of said L-C circuit; said integrated circuit including timer means having an input control terminal C.sub.T which is connectable to a low logic level signal referenced to the potential of said substrate; latch circuit means coupled to said timer circuit means for controlling the frequency at which said first and second discrete devices are switched on and off and having an output which is switched in response to a predetermined signal affixed to said input control terminal; a high side dead time delay circuit and a low side dead time circuit each coupled to said RS latch circuit for delaying the transmission of a latch output signal for a predetermined time delay following the switching of the output of said latch circuit means; a high side level shifting means and a high side driver circuit means and a low side driver circuit means; said high side driver circuit means and said low side driver circuit means coupled to said high side dead time circuit means and said low side dead time circuit means respectively and having high side and low side output pins respectively which produce outputs for turning on and off said first and second MOS gated power devices in response to control signals at said input control terminals C.sub.T ; said dead time delay circuits preventing the simultaneous conduction of said first and second MOS gated power devices.
Patent Citations (2)
Non-Patent Literature (3)
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