Electronic Commutation Switch for Cylindrical Array Antennas

1. Field of the Invention

The invention pertains to the field of electronically scanned antennas and more particularly to commutation switches for electronically scanned cylindrical arrays.

2. Description of the Prior Art

A cylindrical array comprises a multiplicity of individual radiating elements arranged in columns and rings. In such an array, a directive antenna beam is formed by simultaneously exciting the columns with an amplitude and phase distribution (illumination function) that produces the desired antenna pattern. This beam may be electronically scanned about the cylinder axis by commuting the illumination function around the columns of the cylindrical array with the utilization of electronic switching circuits.

A binary commutation switch for commuting the illumination function around the columns of the cylindrical array, thereby scanning the antenna about the axis of the cylinder, is disclosed by Giannini in U.S. Pat. No. 3,816,830. In accordance with the Giannini disclosure a multiplicity of 2.times.2 transfer switches form a N.times.N commutation switch, where N=2.sup.n and n is an integer. The total number of 2.times.2 switches in the N.times.N commutation switch is Nn/2. Single pole-two-throw (SP2T) and single-pole-three-throw (SP3T) switches may be coupled to each output port of the N.times.N commutation switch to respectively scan cylindrical array antennas with 2N and 3N columns. In general, SPMT switches may be added to the N.times.N commutation switch to scan a cylindrical array of MN columns, where M is the number of antenna columns switchably coupled to each output port of the commutation switch.

Utilization of the Giannini commutation switch in large cylindrical arrays requires a significant number of transfer switches, appreciably adding to cost of the array. A commutation switch which provides an appreciable reduction in the number of transfer switches is therefore desirable.

In a first embodiment of the invention a commutation circuit for scanning an array of N columns, with symmetric or antisymmetric illumination functions, comprises two N/2.times.N/2 commutation switches. This arrangement reduces the number of transfer switches by N/2 with the concomitant increase in reliability, and reduction in cost, complexity, and signal loss. The reduction in the number of transfer switches is realized by recognizing that a commutation switch can provide two types commutations, one being the inverse of the other.

In a second embodiment of the invention transfer switches having a number of ports that are not related to a binary number are employed in a commutation switch. These non-binary transfer switches are capable of the two types of commutations wherein one commutation is the inverse of the other. Thus, a 3.times.3 transfer switch may be employed to provide a N.times.N commutation switch in which N=3.sup.n, n being an integer. This commutation switch contains N/3 individual 3.times.3 transfer switches and may be combined with SPMT switches at each output port to increase the elements that can be fed by the commutation switch.

The 3.times.3 transfer switch may be combined with 2.times.2 transfer switches to form a N.times.N commutation switch in which N=2.sup.m.3.sup.n, where m and n are integers, thus allowing a much wider choice of N. These commutation switches contain mN/2 individual 2.times.2 switches and nN/3 individual 3.times.3 switches. The 2.times.2 and 3.times.3 switch arrangement may also be combined with SPMT switches at each output jport to increase the number of antenna colummns which can be fed.

FIG. 1 is schematic diagram of a 4.times.4 transfer switch.

FIGS. 2A and 2B are schematic diagrams of the input-output connections for the states of a 2.times.2 transfer switch.

FIG. 3 is a representation of the circuit topology of a 2.times.2 transfer switch.

FIGS. 4A-4D are representations of commutation states of the 4.times.4 transfer switch shown in FIG. 1.

FIGS. 5A-5D are representations of commutation switch inversion states corresponding to the commutation states shown in FIGS. 4A-4D.

FIG. 6 is a schematic diagram of an 8.times.8 commutation switch in accordance with the prior art.

FIGS. 7A-7C are schematic diagram of an 8.times.8 commutation switch in accordance with the invention.

FIGS. 8A-8D are schematic diagrams of 3.times.3 transfer switches in various state conditions.

FIG. 9 is a schematic diagram of a 3.times.3 commutation switch utilizing one single pole three throw (SP3T) switch.

FIG. 10 shows a diode arrangement.

FIG. 11 is a representation of the circuit topology of a square lattice 3.times.3 transfer switch.

FIG. 12 is a representation of an area about an interconnection region in a square lattice 3.times.3 transfer switch.

FIG. 13 is a cross sectional view, partially in schematic format, of the section A--A shown in FIG. 12.

FIG. 14 is a representation of the circuit topology of a rectangular lattice 3.times.3 transfer switch.

FIG. 15 is a representation of an area about an interconnection region including the switching diode location.

FIG. 16 is a cross sectional, partially in schematic format, of the section B--B shown in FIG. 15.

This 4.times.4 transfer switch comprises four 2.times.2 transfer switches 12a-12d. Each 2.times.2 switch has two states representing the two possible interconnections of its input and output ports and designated state 0 and state 1 as illustrated in FIG. 2. Such a 2.times.2 transfer switch may be realized in stripline using four diodes 13a-13d in the circuit topology shown in FIG. 3. The diodes 13a-13d may be shunted between the circular stipline 14 and located such that the distance between the diode and the adjacent input and output ports is a quarter wavelength (g/4). Thus when a diode is biased in the conducting state an open circuit is seen by the input and output ports looking into the stripline segment towards the conducting diode. When a diode is biased in the non-conducting state, the input and output posts adjacent to the diode are electrically coupled. It should be apparent that a state matrix for the 4.times.4 transfer switch shown in FIG. 1 in terms of the 2.times.2 transfer switches of which it is composed and may be represented as ##EQU1## wherein each of the elements are 0 or 1 depending on the state of the corresponding 2.times.2 transfer switch. Consequently each diode has the capability of electronically making or breaking the connection between an input port and an output port depending on its bias condition. Therefore, if the connection is made at diodes 13aand 13d input 1 is connected to output 1 and input 2 is connected to output 2, and the switch is said to be in state 0. Conversely, if the connection is broken at diodes 13a and 13d while made at diode 13b and 13d, input 1 is connected to output 2 and input 2 is connected to output 1, and the switch is said to be in state 1.

Refer now to FIGS. 4A-4D wherein representations of four classical commutation states and the corresponding state matrix of the 4.times.4 transfer switch depicted in FIG. 1 are shown. FIG. 4A illustrates the straight-through condition for which signal A, B, C, and D imposed at input ports 1 through 4 correspondingly appear at output ports 1 through 4 respectively.

FIG. 4B shows the first commutation condition for which the input signals A, B, C and D are sequenced to output ports 2, 3, 4, and 1 respectively. Similarly, the second and third commutation condition are illustrated in FIGS. 4C and 4D. The stated interconnections can be verified by tracing paths from input to output through the circuit topology of FIG. 1 for the indicated state of each 2.times.2 transfer switch. FIGS. 5A-5D illustrates the inversion condition corresponding to each commutation condition of FIGS. 4A-4D. Note that the inversion effected by reversing the state of each constituent 2.times.2 switch interchanges the output ports so that A-D, D-A, B-C, and C-B. Further note that the state matrix and its inverse are complementary, that is the sum of the corresponding elements in the state matrix and its inverse is equal to 1.

FIG. 6 shows the circuit topology of an 8.times.8 commutation switch 20 designed in accordance with the prior art. This switch comprises two 4.times.4 transfer switches 15a and 15b respectively and four 2.times.2 transfer switches 16a-16d. The state matrix for this configuration may be given as ##STR1## where A, and B, are respectively the state matrices of the 4.times.4 transfer switches 15a and 15b and the elements a.sub.1 -d.sub.1 are the respective states of the 2.times.2 transfer switches 16a-16d. Given A, B, C, D, E, F, G and H as the sequence of signals at the input ports, the sequence of signals at the output ports for each of the eight commutation states is given as:

The corresponding state matrices for each of these sequences are as follows: ##STR2##

The state matrix for this 8.times.8 transfer switch is given as: ##EQU2## where A.sub.2 is the state matrix of transfer switch 17a and B.sub.2 is the state matrix of transfer switch 17b. Note the absence of the row of 2.times.2 transfer switches. The operation of this switch is explained with regard to symmetric and anti-symmetric input signal sequences: A,B,C,D,D,C,B,A and A',B',C',D',-D',-C',-B',-A', respectively. These sequences could represent simultaneous sum and delta illumination functions for a monopulse radar. The commutation switch states are accordingly given in terms of the output sequence as follows:

Both sequences are commuted in the same manner. The delta sequence, however, has a polarity reversal between adjacent states. In a monopulse radar, this will cause the sign of the error signal to change between adjacent beams. Although this will not alter system performance, the sign change must be recognized in the data processor to properly interpret track data. The corresponding state matrices for the switch are as follows: ##STR3##

It should be apparent that the normal commutation states of the 4.times.4 transfer switches shown in FIGS. 4A-4D and the inversion states shown in FIGS. 5A-5D are used to produce the above commutation states for the novel 8.times.8 switch.

It should also be apparent that the commutation switches shown in FIGS. 6 and 7 commute the signals at the eight input ports only about the eight output ports and without additional components can not provide the necessary couplings to elements of a cylindrical array to affect the desired beam scanning. Appropriate couplings to elements about the cylinder to realize beam scanning of a 16 element cylindrical array can be accomplished with the 8.times.8 commutation switch 30 of FIG. 7 by adding a switch bank 35 containing eight single pole two throw switches (SP2T).

Refer now to FIGS. 7A-7C wherein the couplings of the SP2T switches in the switch bank 35 are shown. As shown in FIGS. 7A through 7C, the first secondary ports 35-1 through 35-8 of SP2T switches 35a through 35h are respectively coupled to array elements 36-1 through 36-8 via lines 37-1 through 37-8, while the second secondary ports 35-9 through 35-16 are respectively coupled to array elements 36-9 through 36-16 via lines 37-9 through 37-16. The primary ports of the SP2T switches 35a through 35h are respectively coupled to the output ports 30-1 through 30-8 of commutation switch 30 (FIG. 7). When the commutation switch 30 is in State 1, the primary ports of SP2T switches 35a through 35h may be coupled to the respective secondary ports 35-1 through 35-8 and therefrom to array elements 36-1 through 36-8, respectively, thereby coupling the signal sequence of State 1 array elements as shown in FIG. 7A.

When the commutation switch 30 is in State 2, the primary port of SP2T switch 35a is coupled to the secondary port 36-9 thereby coupling the signals A and A' via line 37-9 to array element 36-9. Thus the beam has been scanned and the signal sequence has been maintained, though as previously stated the delta sequence has a polarity reversal.

Refer now to FIG. 7C to provide the proper array element coupling for the State 3 sequences the primary ports of SP2T switches 35a and 35b are respectively coupled to the secondary ports 36-9 and 36-10. Consequently, the signal pairs B, -B' and A, -A' are respectively coupled via lines 37-9 and 37-10 to array element 36-9 and 36-10, establishing the signal sequences at the array elements 36-3 to 36-10 shown in FIG. 7C. It is apparent that the signal sequences are maintained for the scan angle of State 3 and the proper polarity of the delta sequence is provided. Though the above example of cylindrical array scanning considered eight active array elements and a sixteen element cylindrical array, it should be recognized that the number of radiating and array elements is not restricted. Any binary number N.sub.1 of active array elements and any number N.sub.2 of cylindrical array elements may be chosen, provided N.sub.2 /N.sub.1 is an integer M and SPMT switches are utilized to provide scanning and proper signal sequencing.

Although the principles of the invention are illustrated with respect to a comparatively simple 8.times.8 commutation switch, it will be recognized by those skilled in the art that the invention is applicable to all commutation switches in which the number of elements N is a binary number.

Commutation and inversion capabilities may be implemented in non-binary transfer switches, as for example, a 3.times.3 transfer switch which requires but 9 diodes. The principles of the non-binary switch will hereafter be explained with reference to a 3.times.3 switch, although it will be recognized that 4.times.4, 5.times.5 and larger switches may be designed using the same principles.

A 3.times.3 transfer switch manifesting the desired commutation and inversion properties may be built using six single-pole-three-throw (SP3T) switches as shown in FIGS. 8A-8D. A SP3T switch has the property of electronically interconnecting a primary port to any one of three secondary ports. As shown in the figures, a 3.times.3 transfere switch may comprise three input SP3T switches and three output SP3T switches. The primary ports of the input SP3T switches constitute the input ports of the transfere switch and the primary ports of the output switches constitute the output ports of the transfer switch, while the secondary ports of the input and output switches are interconnected such that there is a route between each input switch and each output switch. This architecture facilitates all possible interconnections between the input port and the output ports.

The 3.times.3 transfer switches shown in FIGS. 8A-8D are identical. These Figures show the transfer switch in four different states; the states shown in FIGS. 8C and 8D being the inversion states of those shown in FIGS. 8A and 8B, respectively. Referring to FIGS. 8A-8D, three input SP3T switches 18a-18c are coupled to three output SP3T switches 19a-19c. The first secondary port of switch 18a is coupled via line 20a to the first secondary port of output switch 19a, while the second and third secondary ports are respectively coupled via lines 20b, and 20c to the first secondary ports of output switches 19b and 19c. Similarly, the first, second, and third secondary ports of input switch 18b are respectively coupled via lines 21a-21c to the second secondary port of output switches 19a, 19b, and 19c. In like manner the first, second, and third secondary ports are respectively coupled via lines 22a-22c to the third secondary port of output switches 19a-19c. The three primary ports 18d-18f of the input SP3T switches 18a-18c and the three primary ports 19d-19f of the output SP3T switches 19a-19f, respectively serve as the input and output ports of the 3.times.3 transfer switch.

A major disadvantage of this architecture, as shown in FIG. 10, is that it contains eighteen diodes, since three diodes are needed in each SP3T switch. The diodes 23a-23c may be respectively shunted between the secondary output lines 24a-24c and a ground plane not shown. Connections to the secondary ports are made by applying a cut-off bias to the diode corresponding to the secondary port which is to be coupled to the primary port and applying a conducting bias to the diodes associated with the other two secondary ports. The three diodes 23a-23c are positioned a quarter wavelength (.lambda.g/4) from the junction 25 of a line 26 leading to the primary port and the three lines 24a-24c leading to the secondary ports. Thus, when a conducting bias is applied to a diode an open circuit is presented at the junction for that line and only the line associated with the diode biased beyond cut-off couples a signal from the primary port to a secondary port. Consequently, when a connection is made, as for example, by diode 23a, the connection is broken at diodes 23b and 23c and the primary port 27 is coupled to secondary port 28a. Alternatively, making the connection only at diodes 23b or 23c will coupled the primary port to secondary ports 28b or 28c, respectively. When six SP3T switches operate as a 3.times.3 transfer switch as shown in FIGS. 8A, the diodes associated with the secondary ports coupled to the respective primary ports are similarly biased for all meaningful states of the transfer switch. The diode pairs associated with interconnected secondary ports may therefore, in principle, be replaced by a single diode, thereby reducing the number of diodes to nine per transfer switch, creating the transfer switch shown in FIG. 9.

Referring to the figure, the first secondary ports 31a-31c of SP3T switches 32a-32c are coupled to a first output port 33, while the second secondary ports 34a-34c of each of the SP3T switches are coupled to a second output port 33b and the third secondary ports 35a-35c of each of the SP3T switches are coupled to a third output port 33c.

There are practical difficulties in implementing this reduced complexity configuration. It is desirable for improved performance to utilize diodes shunt-mounted between the secondary ports of each SP3T switch and a ground plane, not shown. The diodes in the SP3T switches should, therefore, be located an odd multiple of .lambda.g/4 from the output ports 33a-33c so that the diodes biased for a short-circuit will reflect an open circuit at associated output port. For maximum bandwidth, the electrical length between the junction and the diodes should be .lambda.g/4 where .lambda.g is the wavelength in the transmission lines at the center frequency of the operating band. This presents a significant topological problem, especially at higher frequencies.

Refer now to FIG. 11, wherein circuit topology on a two layer printed circuit board constituted in accordance with the invention is shown for a 3.times.3 transfer switch. The routing of transmission lines 41a-41c printed on the upper layer is depicted as solid lines while the routing of transmission lines 2a-42c printed on the lower layer is depicted as dashed lines. Nine diodes 43a-43c are located at the inter-deck connections which are arranged in a substantially square lattice. The two-layer construction, nominally square lay-out of diodes, and inter-deck connections allows the interconnection of each row of diodes to junctions 44a, 44b, and 44c on the upper layer through .lambda.g/4 line lengths while simultaneously allowing the interconnection of each column of diodes to junctions 45a, 45b, and 45c on the lower layer also through .lambda.g/4 line lengths.

This transfer switch may be operated to commute and invert the sequence of signals at the input ports as needed to implement the invention. Referring again to FIG. 11, let A, B, and C represent the sequence of signals at input ports 47A, 47B, and 47C, respectively. Each diode has two states: State 1 which makes the connection and state 0 which breaks the connection. A connection is broken when a diode is in the conducting, state thereby creating a short to ground as will be subsequently explained. A state matrix may, therefore, be defined for all meaningful bias conditions of the diodes. The state matrices and associated signal sequences at the output ports are tabulated below for commutation and inversion respectively:

The output sequence refers to the signals exiting from output ports 48A through 48C, respectively, assuming signals A, B, and C enter the switch through input ports 47A, 47B, and 47C, respectively. The state matrices represent the state of each diode arranged as: ##EQU3## in accordance with the reference numerals in FIG. 11. Noting that for proper operation, each junction must be connected to one and only one open-circuited diode, only the six listed switch states are meaningful and follow the rule that the sum of all rows and all columns is equal to unity.

Consider state matrix 1, for which the diodes 43a, 43e, and 43i are in the non-conducting state, all other diodes being in the conducting state. Consequently, due to the quarter wavelength spacing of the diodes from the junctions 44a-44c and 45a-45c, open circuits are reflected at the junctions for all paths except those through the inter-deck connections at the locations of diodes 43a, 43e, 43i. Therefore, a signal A at input port 47A follows a path along transmission 42ato the junction 45a, therefrom through the inter-deck connection at the location of non-conducting diode 43 to the junction 44a, and therefrom along transmission line 41a to the output port 48. Similarly, input port 47B is coupled to output port 48B and input port 47C is coupled to output port 48C. The input port-output port couplings for state matrix 2-6 may be similarly traced.

Refer now to FIGS. 12 and 13 wherein like elements bear the same reference numerals. FIG. 12 is a top view of a region about an inter-deck connection 51 with a co-located diode 52, while FIG. 13 is a cross-sectional view through the cross-section A--A of FIG. 12. These figures are representative of all inter-deck connections. The circuit board comprises an upper dielectric layer 49a and a lower dielectric layer 49b separated by a ground plane 49c. A conductor 53 soldered to a transmission line 54 on the upper layer extends into an inter-deck passageway 55 to a d.c. blocking capacitor 56, formed by providing a small gap between conductor 53 and a conductor 57, which is coupled to a terminal 58 to receive d.c. bias voltages. Diode 52 is coupled between the printed circuit board ground plane 49c and the conductor 57. A conductor 59 soldered to a transmission line 61 on the lower layer 49b extends into the inter-deck passageway 55 to a second d.c. blocking capacitor 62, formed by providing a small gap between the conductors 57 and 59. The capacitors 56 and 62 are designed to provide a short circuit for the signals of interest and a d.c. open circuit to diode 52 bias voltages. Thus providing signal coupling between the transmission lines 53 and 61 while blocking d.c. from those transmission lines.

Collocating the diodes 43a-43i with the inter-deck connections of the circuit board, as shown in FIGS. 11-13, presents difficulty in assembly and requires the development of a special diode package to ease this problem. This difficulty may be overcome by rectangularizing the inter-deck lattice, as shown in FIG. 14. This topology spaces the rows of the inter-deck 10% closer as compared to the square lattice of FIG. 11. The diodes 72a-72i may all be located on the lower layer approximately 0.03 .lambda.g from the inter-deck connections, while maintaining the .lambda.g/4 spacing between the diodes 72a-72i and the lower-layer junctions 74a-74c. This obviates the need for packaged diodes allowing the use of lower-cost chip diodes. To maintain the .lambda.g/4 electrical length from the diodes to the 72a-72 to the upper layer junctions 73a-73c, the line lengths on the upper layer may be correspondingly 0.03 .lambda.g shorter.

FIG. 15 is a top view of a region about an inter-deck connection 72 and a diode 73 location. FIG. 16 is a cross sectional view through the cross-section B--B in FIG. 15. In FIGS. 15 and 16 like elements bear the same reference numeral. A conductor 74 extends through a passageway 71 and is configured so that it may be soldered to a transmission line 75 on the upper layer and a transmission line 76 on the lower layer. A bore hole 77 of suitable diameter extends through the transmission line 76 and lower layer dielectric 78 to a metallic ground plane 79. Diode 73 is coupled to the ground plane 79 and, via a capacitor 81, to the transmission line 76. A terminal 82 for providing d.c. bias voltage to the diode 73 is coupled, via lead line 83, to a location between the capacitor 81 and the diode 73.

While the invention has been described in its preferred embodiments, it is to be understood that the words which have been used are words of description rather than limitation and that changes may be made within the purview of the appended claims without departing from the true scope and spirit of the invention in its broader aspects.