Digitally Controlled High Resolution Hybrid Phase Synthesizer

The present invention relates to components in synchronous digital communication systems and, more particularly, to digitally controlled circuitry having selectable phase resolution for clock recovery.

In digital communication systems, information is transferred between sending and receiving terminals over a transmission line or, more generally, a communication channel in a format suitable for that channel. The format can be a baseband signal or, using a digitally modulated carrier, a bandpass signal. In either case, the signal is characterized by a fundamental baud or symbol rate, i.e., the clock frequency of the data.

In synchronous digital communications, it is frequently necessary to extract a coherent clock signal from a received input data stream. This process is known as clock recovery. The recovered clock enables the receiving terminal to optimally sample the received digitally encoded communication signals. Clock recovery circuits commonly are employed, for instance, in conjunction with analog data communications over telephone or radio channels.

Conventional clock recovery circuits typically employ phase-locked loops ("PLL's"). A typical PLL has a voltage-controlled crystal oscillator (VCXO) whose phase is locked onto a frequency component of its input signal. The PLL also has a phase detector for comparing the phase of the oscillator with the phase of the input signal, and for developing a voltage proportional to the phase differential, which commonly is referred to as a "phase error". This voltage is filtered and applied as a control voltage to the oscillator so as to adjust the oscillator's frequency. Due to negative feedback, the phase error is driven to a value which is preferably small, and the oscillator's frequency consequently is kept equal to the input frequency. However, the aforementioned VCXO is disadvantageous in that it is not versatile (it is not readily adaptable in other circuit schemes) and has a long delivery time on frequency. Further, high resolution Digital-to-Analog converters which are required to drive VCXO's are complex and expensive to implement.

In contrast, crystal oscillators provide both inherent stability characteristics and do not need the requirement of the aforementioned Digital-to-Analog converter required to drive the voltage controlled crystal oscillator.

It is thus an object of the present invention to provide a variable phase shifter which employs a crystal oscillator to be incorporated into clock extraction circuitry and is adaptable for the implementation of a wide range of crystal oscillators.

The present invention is directed towards a digitally control high resolution phase synthesizer incorporating an incremental phase shifter. The phase synthesizer is configured to be implemented into clock extraction circuitry and is adapted to generate an output square wave which has a variable phase relationship to generated quadrature square waves and an input reference signal.

The phase synthesizer includes a reference signal source and frequency dividing means for dividing a frequency of the reference signal source by a predetermined divide ratio. Preferably, the divide ratio of the reference signal source is four (4) and the reference signal source includes a crystal oscillator. Further, the phase synthesizer includes an accumulator circuit for receiving a 6-bit input signal and for generating a carry signal in dependence upon the input signal. Preferably, the four (4) least significant bits of the input signal is determinative for either generating a logic "HIGH" or logic "LOW" carry signal.

A multiplexer is provided for generating an adjacent pair of signals from the signal generated from the aforementioned frequency dividing means. The carry signal is also inputted into the multiplexer and is determinative for generating the adjacent pair of signals. Shifting means is coupled to the multiplexer and is adapted for shifting the adjacent pair of signals generated from the multiplexer by a prescribed amount. Circuit weighing means is coupled to the shifting means and is adapted to derive a signal having a phase within the phase range defined by the phases of the adjacent pair of signals. Preferably, the circuit weighing means includes a finite impulse response filter having a plurality of summing resistors.

The foregoing features of the present invention will become more readily apparent and may be understood by referring to the following detailed description of an illustrative embodiment of an apparatus according to the present invention, taken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a simplified block diagram of the phase synthesizer embodying the present invention;

FIG. 2 illustrates the phase synthesizer of FIG. 1 in accordance with a preferred embodiment of the subject invention;

FIG. 3 illustrates a preferred embodiment for the integrator/limiter circuit of FIG. 1;

FIG. 4 illustrates the phase synthesizer of FIG. 1 in accordance with another preferred embodiment of the subject invention;

FIG. 5A and 5B illustrate a timing diagram of representative signals utilized in the incremental phase shifter of FIG. 1; and

FIG. 6 illustrates yet another preferred embodiment of the phase synthesizer of FIG. 1 in accordance with the subject invention.

Referring now to the drawings, in which like reference numerals identify similar or identical elements, FIG. 1 illustrates a simplified block diagram of a phase synthesizer 10 for recovering a clock signal from digital communication signals in accordance with the present invention. The phase synthesizer 10 includes a master crystal oscillator (MCO) 20 coupled to a counting circuit 30. The counting circuit 30 is coupled to quadrant select switch circuitry 40 which is coupled to a hybrid weighting circuit 50. The hybrid weighting circuit 50 is coupled to a conventional integrator circuit 60 and limiter circuit 70.

The counting circuit 30 is driven by the MCO 20 to generate a four (4) phase square wave output at F.sub.out designated, respectively, .o slashed..sub.0, .o slashed..sub.1, .o slashed..sub.2 and .o slashed..sub.3. F.sub.out is preferably 1/4 the periodic frequency of the MCO 20, and the period of each respective wave .o slashed..sub.0, .o slashed..sub.1, .o slashed..sub.2 and .o slashed..sub.3 is to equal "T". Typically, MCO 20 has an operating frequency of 49.408 MHz, thus each respective wave .o slashed..sub.0, .o slashed..sub.1, .o slashed..sub.2 and .o slashed..sub.3 of F.sub.out is to correspondingly have a frequency of 12.352 MHz with T=1/12.352 MHz. An adjacent pair of phases from the four (4) phases (.o slashed..sub.0, .o slashed..sub.1, .o slashed..sub.2 and .o slashed..sub.3) of F.sub.out is selected by the Quadrant Select switches 40 to represent one of the four (4) quadrants of the four (4) phase signal F.sub.out. The two elements of the aforementioned adjacent pair of signals are designated LO and HI, respectively. The hybrid weighting circuit 50 combines weighted amounts of LO and HI to generate a wave with a phase between the phase of the LO and HI pair.

It is appreciated, either element, HI or LO, may be utilized as a reference value, as will be described in greater detail below. For example, if LO is used as a reference value, then the weighted output (W) equals w(HI)+(l-w)LO, wherein w corresponds to a selected incremental value. Output W is then integrated by integrator circuit 60 and limited in limiter circuit 70 to have a phase value of LO+(w.circle-solid.T)/4+ (a constant), wherein the constant corresponds to a fixed offset. For example, if the increments of w are 1/16 of the frequency of the MCO 20, then the phase synthesizer 10 generates 64 phases of a square wave output which is equivalent to 16 phases of the MCO 20 output.

Turning to FIG. 2, there is illustrated a preferred embodiment of the phase synthesizer 10 (FIG. 1), designated generally at 100, adapted for implementation in preferably a medium scale integration logic chip. As mentioned above, the MCO 20 operating at preferably 49.408 MHz is divided by four (4) by the counting circuit 30 to give rise to 4 phases (.o slashed..sub.0, .o slashed..sub.1, .o slashed..sub.2 and .o slashed..sub.3) of a 12.352 MHz signal. The cycles of the two square waves LO or HI are selected in the 4-stage shift register 110 and output, as shown in FIG. 5, as 4 Stage Register Outputs "D" and "A" into a 64-bit shift register 120, via a 1/8 multiplexer 130. The 64-bit shift register 120 operates at the clock rate corresponding to the MCO 20 (49.408 MHz). It is to be appreciated that it is to be understood that the clock rate for the MCO 20 is not to be limited to 49.408 MHz, but rather may operate at any suitable clock rate.

The input (N.sub.phase) to the phase synthesizer 100 is preferably a 6-bit binary number (P.sub.0, P.sub.1, P.sub.2, P.sub.3, P.sub.4, P.sub.5 and P.sub.6) representing a selected phase of the square wave output. The two (2) most significant bits (p.sub.4,p.sub.5) of N.sub.phase are utilized in the 1/8 multiplexer 130 to select the quadrant or which pair of the aforementioned four (4) quadrature outputs is to be output to give rise to the values of LO and HI (the adjacent phases from these signals). It is to be appreciated that for any setting of N.sub.phase, the sequence in the 64-bit stage shift register 120 will be periodic with 16 cycles of F.sub.out, as shown in FIG. 5A.

The four least significant bits (P.sub.0, P.sub.1, P.sub.2 and P.sub.3) of the aforementioned 6-bit binary number N.sub.phase are used to update an arithmetic accumulator circuit 150 and adder circuit 160. The rate of the carries output (C), as illustrated in FIG. 5A, from the adder circuit 160 is proportional to the number fed into the accumulator 150 and is utilized to generate the particular square wave (LO or HI), as is also illustrated in FIG. 5A, to be outputted from the multiplexer 130. For example, if the carry (C) is "0", then the output from the multiplexer 130 is LO. If the carry (C) is "1", then the output from the multiplexer 130 is HI. The number of carries (C) outputted from the accumulator 150 in 16 clock cycles is equal to the value of the 4 least significant bits (P.sub.0, P.sub.1,P.sub.2, P.sub.3) of the input signal N.sub.phase.

The square waves (LO or HI) are outputted serially from the multiplexer 130 and are inputted into the 64-stage shift register 120. Every 4th stage of 64-stage shift register 120 is coupled to a summing resistor, wherein there are 16 respective summing resisters (r.sub.1, r.sub.2, . . . r.sub.16) coupled to the shift register 120. The summing resistors (r.sub.1, r.sub.2, . . . r.sub.16) constitute a finite impulse response filter whose output is the weighted sum of W=w.circle-solid.HI+(l-w).circle-solid.LO, wherein the outputted signals from the summing resistors are, respectfully, illustrated in FIG. 5A. The common node 170 of the aforementioned resistors (r.sub.1, r.sub.2, . . . r.sub.16) is coupled to the input of the integrator circuit 60 whose output as shown in FIG. 5A (Average of 64-stage shift Register Outputs with the signal magnification shown in FIG. 5B) and is coupled to the input of the limiter circuit 70. The output of the limiter circuit 70 generates a square wave (f.sub.o /4) of approximately 12.352 MHz.

FIG. 3 illustrates a preferred embodiment integrataor/limiter circuit of the integrator circuit 60 and limiter circuit 70 of FIG. 2, designated generally at 61. Integrator/limiter circuit 61 preferably employs voltage inverters 62, 64, 66 and 68 in series with one another. The aforementioned voltage inverters are preferably model number 74HCUO4, commercially available from National Semiconductor. The voltage inverters 62, 64, 66 and 68 are each provided with a predetermined gain enabling them to function as amplifiers in conjunction with the associated resistors and capacitors of circuit 61. The integrator/limiter circuit 61 further includes a first capacitor 71 coupled intermediate the summing resistors (r.sub.1, r.sub.2, . . . r.sub.16) and a second capacitor 72 coupled in parallel to inverter 62 and a resistor 74 coupled in parallel to inverters 62, 64 and 66. It is noted capacitor 71 functions as a DC blocking capacitor and capacitor 71 in conjunction with resistor 74 function as a high pass filter operative to suppress any direct current. It is to be appreciated that the aforementioned and described circuit arrangement 61 is not to be understood to be the only integrator/limiter circuit arrangement, as it is to be understood that one ordinarily skilled in the art may implement numerous integrator/limiter circuit arrangements to generate W=w*HI+(l-w)*LO.

Turning to FIG. 4, there is illustrated another preferred embodiment of the phase synthesizer 10 (FIG. 1), designated generally at 101. In particular, phase synthesizer 101 is adapted for implementation in a DSP Timing Recovery Phase Locked Loop (PLL) scheme. An N-bit number (N.sub.f, line 200) having sign extension, as is conventional, is added into an M-bit wide accumulator circuit 220, via input register 210, periodically at a block rate R.sub.b, line 215. The number N.sub.r loaded into the input register 210 is preferably between -1/2 to 1/2. The number N.sub.f loaded into the input register 210 is determined by an associated Digital Signal Processor (DSP) (not shown).

With the number N.sub.f set to either its maximum or minimum, wherein-1/2<N.sub.f <1/2, it takes 2.sup.9 counts for the accumulator circuit 220 to complete a full cycle. Therefore, with the periodic rate (R) being equal to F.sub.out /16 (the counting circuit 30 has a divide ratio of 16), the maximum deviation (resolution) of F.sub.out is +1/2.sup.-28, or one part in 8192 and a minimum deviation (resolution) of F.sub.out is +1/2.sup.-28, or one part in 2.6.circle-solid.10.sup.8. Further, by changing the value of "R" to F.sub.out/2 (the counting circuit 30 has a divide ratio of 2), a maximum deviation of 1/1024 can be obtained while still maintaining excellent resolution.

Therefore, the value of N.sub.f (line 215) is viewed as having a Phase component (n.sub.f) and a frequency component (n.sub.f). The phase (n.sub..o slashed.) and frequency components (n.sub.f) are added together before they are output from the Digital Signal Processor. The frequency components (n.sub.f) is a steady (or slowly changing) value, whereas the phase component (n.sub.526 ) is used on a block by block basis to correct the timing phase error. Preferably, the Digital Signal processor stores the frequency component (n.sub.526 ) and adds a new phase correction on every clock tick of the clock rate R.sub.B. Thus, considering the phase component (n.sub.526 ) alone, a number (n.sub.526 ) is outputted at f.sub.out which corresponds to a frequency offset (f.sub..o slashed.) which is the output for one period of the block rate (R.sub.B), i.e., .DELTA.t.sub.b. The added phase due to this output is then F.sub..o slashed. .circle-solid..DELTA.t.sub.b. Further, in the implementation of second order phase lock loops, the frequency and phase errors can be dealt with independently.

Yet another preferred embodiment of the phase synthesizer 10 (FIG. 1) in accordance with the subject invention is illustrated in FIG. 6 and is designated generally by reference numeral 300. The incremental phase shifter 300 performs the same function as the phase synthesizer 100 of FIG. 2, that is, the output of the limiter circuit 70 is equal to f.sub.o/4, wherein f.sub.o corresponds to the frequency of the crystal oscillator 20.

Phase synthesizer 300 includes the provision of the crystal oscillator (MCO) 20, counting circuit 30, 4-stage shifter register 110, integrator circuit 60 and limiter circuit 70 which all perform identical functions in correspondence to their implementation in the phase synthesizer 100 of FIG. 2. However, phase synthesizer 300 includes the provision of 4 to 1 multiplexers (MUXs), 2 to 1 MUXs and accompanying latch and summing resistors, as will be described below, which are operative to provide a weighted input W of the 6-bit binary number (p.sub.0, p.sub.1, p.sub.2, p.sub.3, p.sub.4, P.sub.5) (N.sub.phase) to the integrator circuit 60.

In reference to FIG. 6, the phase synthesizer 300 includes a first 4 to 1 MUX 302 wherein its respective inputs are coupled to the respective outputs of the 4-stage shift register 110. A second 4 to 1 MUX 304 is further coupled at its inputs to the respective outputs of the 4-stage shift register 110. The address selectors 306 and 308 of MUX 302, as well as the address selectors 310 and 312 of MUX 304 are coupled to the two (2) most significant bits (p.sub.4, p.sub.5) of the 6-bit binary number N.sub.phase. MUX 302 is operative to determine and output, via line 314, the aforementioned HI phase value in dependence upon the values of p.sub.4 and p.sub.5. MUX 304 is operative to determine and output, via line 316, the aforementioned LO phase value in dependence upon the values of p.sub.4 and p.sub.5.

The phase synthesizer 300 further includes 2 to 1 MUXs, 318, 320, 322 and 324. The respective inputs 326, 328, 330 and 332 of the later MUXs are coupled to the HI phase value, via line 314, of MUX 302. The respective inputs 334, 336, 338 and 340 of MUXs 318, 320, 322 and 324 are coupled to the LO phase value, via line 316, of MUX 304. The respective address selectors 342, 344, 346 and 348 of MUXs, 318, 320, 322 and 324 are respectively coupled to the four (4) least significant bits (p.sub.3, p.sub.2, p.sub.1, P.sub.0) of the 6-bit binary number N.sub.phase. Therefore, MUXs 318, 320, 322 and 324 are operative to output either the HI or LO phase value in dependence upon the value of respectively address selectors 342(p.sub.3), 344(p.sub.2), 346(p.sub.1) and 348(p.sub.0).

Latching devices 350, 352, 354 and 356 are further provided and are respectively coupled to the outputs of MUXs 318, 320, 322 and 324 and are operative to latch and stabilize the outputs of the later mentioned MUXs. Latching device 358 is additionally provided and has its input coupled to the LO phase value, via line 316. Therefore, the output value of latch device 358 is always equal to the LO phase value.

With continued reference to FIG. 6, summing resistors 360, 362, 366 368 and 370 respectively coupled to the outputs of latching devices 350, 352, 354, 356 and 358. In particular, the conductances of the aforementioned summing resistors are listed below:

wherein the aforementioned weighted output W at node 370 (the input to integrator circuit 60) equals:

An example of the sequence of operation of the phase synthesizer 300, in correlation with the output W at node 370 is illustrated in the below listed table:

As mentioned above, the respective phase values of HI and LO are determined by MUXs 302 and 304 from the output of the 4-bit shift register 110 in dependence upon the two (2) most significant bits (p.sub.4 4, p.sub.5) of the 6-bit binary number N.sub.phase. An example of the sequence of operation of MUXs 302 and 304 is illustrated in the below listed table:

The weighted output W is then integrated by the integrator circuit 60 and limited in limiter circuit 70 so as to have a value of LO+(N.circle-solid.T)/4+(a constant), wherein the constant corresponds to a fixed offset and LO is used as a reference value. Therefore, the output of the limiter circuit 70 generates the aforementioned square wave f.sub.o /4 of approximately 12.352 MHz, wherein the clock rate of the MCO 20 is approximately 49.408 MHz.

What has been described is merely illustrative of the application of the principles of the present invention. Other arrangements and methods can be implemented by those skilled in the art without departing from the spirit and scope of the invention.